stm32/dma: add double buffered mode for DMA, update DCMI.
This commit is contained in:
Dario Nieuwenhuis
parent
173c65b543
commit
efc70debb3
@ -434,9 +434,13 @@ where
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result
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}
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#[cfg(not(dma))]
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async fn capture_giant(&mut self, _buffer: &mut [u32]) -> Result<(), Error> {
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todo!()
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/*
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panic!("capturing to buffers larger than 0xffff is only supported on DMA for now, not on BDMA or GPDMA.");
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}
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#[cfg(dma)]
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async fn capture_giant(&mut self, buffer: &mut [u32]) -> Result<(), Error> {
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use crate::dma::TransferOptions;
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let data_len = buffer.len();
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@ -460,16 +464,24 @@ where
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let r = self.inner.regs();
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let src = r.dr().ptr() as *mut u32;
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unsafe {
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channel.start_double_buffered_read(request, src, m0ar, m1ar, chunk_size, TransferOptions::default());
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}
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let mut transfer = unsafe {
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crate::dma::DoubleBuffered::new_read(
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&mut self.dma,
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request,
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src,
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m0ar,
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m1ar,
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chunk_size,
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TransferOptions::default(),
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)
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};
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let mut last_chunk_set_for_transfer = false;
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let mut buffer0_last_accessible = false;
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let dma_result = poll_fn(|cx| {
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channel.set_waker(cx.waker());
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transfer.set_waker(cx.waker());
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let buffer0_currently_accessible = unsafe { channel.is_buffer0_accessible() };
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let buffer0_currently_accessible = transfer.is_buffer0_accessible();
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// check if the accessible buffer changed since last poll
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if buffer0_last_accessible == buffer0_currently_accessible {
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@ -480,21 +492,21 @@ where
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if remaining_chunks != 0 {
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if remaining_chunks % 2 == 0 && buffer0_currently_accessible {
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m0ar = unsafe { m0ar.add(2 * chunk_size) };
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unsafe { channel.set_buffer0(m0ar) }
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unsafe { transfer.set_buffer0(m0ar) }
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remaining_chunks -= 1;
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} else if !buffer0_currently_accessible {
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m1ar = unsafe { m1ar.add(2 * chunk_size) };
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unsafe { channel.set_buffer1(m1ar) };
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unsafe { transfer.set_buffer1(m1ar) };
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remaining_chunks -= 1;
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}
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} else {
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if buffer0_currently_accessible {
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unsafe { channel.set_buffer0(buffer.as_mut_ptr()) }
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unsafe { transfer.set_buffer0(buffer.as_mut_ptr()) }
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} else {
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unsafe { channel.set_buffer1(buffer.as_mut_ptr()) }
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unsafe { transfer.set_buffer1(buffer.as_mut_ptr()) }
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}
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if last_chunk_set_for_transfer {
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channel.request_stop();
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transfer.request_stop();
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return Poll::Ready(());
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}
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last_chunk_set_for_transfer = true;
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@ -542,7 +554,6 @@ where
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unsafe { Self::toggle(false) };
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result
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*/
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}
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}
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@ -1,7 +1,8 @@
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use core::future::Future;
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use core::marker::PhantomData;
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use core::pin::Pin;
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use core::sync::atomic::{fence, Ordering};
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use core::task::{Context, Poll};
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use core::task::{Context, Poll, Waker};
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use embassy_cortex_m::interrupt::Priority;
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use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
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@ -440,3 +441,159 @@ impl<'a, C: Channel> Future for Transfer<'a, C> {
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}
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}
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}
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// ==================================
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#[must_use = "futures do nothing unless you `.await` or poll them"]
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pub struct DoubleBuffered<'a, C: Channel, W: Word> {
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channel: PeripheralRef<'a, C>,
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_phantom: PhantomData<W>,
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}
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impl<'a, C: Channel, W: Word> DoubleBuffered<'a, C, W> {
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pub unsafe fn new_read(
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channel: impl Peripheral<P = C> + 'a,
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_request: Request,
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peri_addr: *mut W,
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buf0: *mut W,
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buf1: *mut W,
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len: usize,
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options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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assert!(len > 0 && len <= 0xFFFF);
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let dir = Dir::PeripheralToMemory;
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let data_size = W::bits();
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let channel_number = channel.num();
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let dma = channel.regs();
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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let mut this = Self {
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channel,
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_phantom: PhantomData,
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};
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this.clear_irqs();
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(&mut *this.channel, _request);
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let ch = dma.st(channel_number);
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ch.par().write_value(peri_addr as u32);
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ch.m0ar().write_value(buf0 as u32);
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ch.m1ar().write_value(buf1 as u32);
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ch.ndtr().write_value(regs::Ndtr(len as _));
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ch.fcr().write(|w| {
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if let Some(fth) = options.fifo_threshold {
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// FIFO mode
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w.set_dmdis(vals::Dmdis::DISABLED);
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w.set_fth(fth.into());
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} else {
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// Direct mode
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w.set_dmdis(vals::Dmdis::ENABLED);
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}
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});
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ch.cr().write(|w| {
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w.set_dir(dir.into());
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w.set_msize(data_size.into());
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w.set_psize(data_size.into());
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w.set_pl(vals::Pl::VERYHIGH);
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w.set_minc(vals::Inc::INCREMENTED);
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w.set_pinc(vals::Inc::FIXED);
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w.set_teie(true);
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w.set_tcie(true);
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#[cfg(dma_v1)]
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w.set_trbuff(true);
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#[cfg(dma_v2)]
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w.set_chsel(_request);
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w.set_pburst(options.pburst.into());
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w.set_mburst(options.mburst.into());
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w.set_pfctrl(options.flow_ctrl.into());
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w.set_en(true);
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});
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this
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}
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fn clear_irqs(&mut self) {
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let channel_number = self.channel.num();
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let dma = self.channel.regs();
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let isrn = channel_number / 4;
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let isrbit = channel_number % 4;
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unsafe {
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dma.ifcr(isrn).write(|w| {
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w.set_tcif(isrbit, true);
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w.set_teif(isrbit, true);
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})
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}
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}
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pub unsafe fn set_buffer0(&mut self, buffer: *mut W) {
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let ch = self.channel.regs().st(self.channel.num());
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ch.m0ar().write_value(buffer as _);
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}
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pub unsafe fn set_buffer1(&mut self, buffer: *mut W) {
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let ch = self.channel.regs().st(self.channel.num());
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ch.m1ar().write_value(buffer as _);
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}
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pub fn is_buffer0_accessible(&mut self) -> bool {
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let ch = self.channel.regs().st(self.channel.num());
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unsafe { ch.cr().read() }.ct() == vals::Ct::MEMORY1
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}
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pub fn set_waker(&mut self, waker: &Waker) {
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STATE.ch_wakers[self.channel.index()].register(waker);
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}
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pub fn request_stop(&mut self) {
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let ch = self.channel.regs().st(self.channel.num());
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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unsafe {
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ch.cr().write(|w| {
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w.set_teie(true);
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w.set_tcie(true);
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})
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}
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}
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pub fn is_running(&mut self) -> bool {
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let ch = self.channel.regs().st(self.channel.num());
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unsafe { ch.cr().read() }.en()
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}
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/// Gets the total remaining transfers for the channel
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/// Note: this will be zero for transfers that completed without cancellation.
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pub fn get_remaining_transfers(&self) -> u16 {
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let ch = self.channel.regs().st(self.channel.num());
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unsafe { ch.ndtr().read() }.ndt()
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}
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pub fn blocking_wait(mut self) {
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while self.is_running() {}
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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core::mem::forget(self);
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}
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}
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impl<'a, C: Channel, W: Word> Drop for DoubleBuffered<'a, C, W> {
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fn drop(&mut self) {
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self.request_stop();
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while self.is_running() {}
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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}
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}
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