max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge #685

Browse Source 
685: Fix STM32 timer interrupt bug r=Dirbaio a=chemicstry

Previously timer overflow interrupts were not firing correctly, because Update Interrupt Enable (UIE) was not set.

The timers still worked somewhat correclty, because overflow was handled together with other interrupts.

Co-authored-by: chemicstry <chemicstry@gmail.com>
This commit is contained in:
bors[bot] 2022-03-29 22:13:30 +00:00 committed by GitHub
commit f028b0064b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
embassy-stm32/src/time_driver.rs
View File

@ -172,8 +172,11 @@ impl RtcDriver {
// Mid-way point // Mid-way point
r.ccr(0).write(|w| w.set_ccr(0x8000)); r.ccr(0).write(|w| w.set_ccr(0x8000));
// Enable CC0, disable others // Enable overflow and half-overflow interrupts
r.dier().write(|w| w.set_ccie(0, true)); r.dier().write(|w| {
w.set_uie(true);
w.set_ccie(0, true);
});
let irq: <T as BasicInstance>::Interrupt = core::mem::transmute(()); let irq: <T as BasicInstance>::Interrupt = core::mem::transmute(());
irq.unpend(); irq.unpend();
@ -197,6 +200,7 @@ impl RtcDriver {
// miss interrupts. // miss interrupts.
r.sr().write_value(regs::SrGp(!sr.0)); r.sr().write_value(regs::SrGp(!sr.0));
// Overflow
if sr.uif() { if sr.uif() {
self.next_period(); self.next_period();
} }