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stm32: fix l4 re-export

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This commit is contained in:
xoviat 2023-08-27 09:50:02 -05:00
parent 3bf6081eb5
commit f28ab18d7b
3 changed files with 10 additions and 14 deletions
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20
embassy-stm32/src/rcc/l4.rs
View File

@ -9,7 +9,7 @@ use crate::gpio::sealed::AFType;
use crate::gpio::Speed; use crate::gpio::Speed;
use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw}; use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
use crate::pac::{FLASH, PWR, RCC}; use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::bd::{BackupDomain, RtcClockSource as RCS}; use crate::rcc::bd::{BackupDomain, RtcClockSource};
use crate::rcc::{set_freqs, Clocks}; use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz; use crate::time::Hertz;
use crate::{peripherals, Peripheral}; use crate::{peripherals, Peripheral};
@ -254,16 +254,11 @@ impl Default for Config {
pllsai1: None, pllsai1: None,
#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))] #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
hsi48: false, hsi48: false,
rtc_mux: RtcClockSource::LSI32, rtc_mux: RtcClockSource::LSI,
} }
} }
} }
pub enum RtcClockSource {
LSE32,
LSI32,
}
pub enum McoClock { pub enum McoClock {
DIV1, DIV1,
DIV2, DIV2,
@ -413,7 +408,7 @@ pub(crate) unsafe fn init(config: Config) {
RCC.apb1enr1().modify(|w| w.set_pwren(true)); RCC.apb1enr1().modify(|w| w.set_pwren(true));
match config.rtc_mux { match config.rtc_mux {
RtcClockSource::LSE32 => { RtcClockSource::LSE => {
// 1. Unlock the backup domain // 1. Unlock the backup domain
PWR.cr1().modify(|w| w.set_dbp(true)); PWR.cr1().modify(|w| w.set_dbp(true));
@ -429,17 +424,18 @@ pub(crate) unsafe fn init(config: Config) {
// Wait until LSE is running // Wait until LSE is running
while !RCC.bdcr().read().lserdy() {} while !RCC.bdcr().read().lserdy() {}
BackupDomain::set_rtc_clock_source(RCS::LSE); BackupDomain::set_rtc_clock_source(RtcClockSource::LSE);
} }
RtcClockSource::LSI32 => { RtcClockSource::LSI => {
// Turn on the internal 32 kHz LSI oscillator // Turn on the internal 32 kHz LSI oscillator
RCC.csr().modify(|w| w.set_lsion(true)); RCC.csr().modify(|w| w.set_lsion(true));
// Wait until LSI is running // Wait until LSI is running
while !RCC.csr().read().lsirdy() {} while !RCC.csr().read().lsirdy() {}
BackupDomain::set_rtc_clock_source(RCS::LSI); BackupDomain::set_rtc_clock_source(RtcClockSource::LSI);
} }
_ => unreachable!(),
} }
let (sys_clk, sw) = match config.mux { let (sys_clk, sw) = match config.mux {
@ -451,7 +447,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_msirgsel(true); w.set_msirgsel(true);
w.set_msion(true); w.set_msion(true);
if let RtcClockSource::LSE32 = config.rtc_mux { if let RtcClockSource::LSE = config.rtc_mux {
// If LSE is enabled, enable calibration of MSI // If LSE is enabled, enable calibration of MSI
w.set_msipllen(true); w.set_msipllen(true);
} else { } else {

2
examples/stm32l4/src/bin/rtc.rs
View File

@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) {
PLLMul::Mul20, PLLMul::Mul20,
None, None,
); );
config.rcc.rtc_mux = rcc::RtcClockSource::LSE32; config.rcc.rtc_mux = rcc::RtcClockSource::LSE;
embassy_stm32::init(config) embassy_stm32::init(config)
}; };
info!("Hello World!"); info!("Hello World!");

2
examples/stm32l4/src/bin/spe_adin1110_http_server.rs
View File

@ -84,7 +84,7 @@ async fn main(spawner: Spawner) {
None, None,
); );
config.rcc.hsi48 = true; // needed for rng config.rcc.hsi48 = true; // needed for rng
config.rcc.rtc_mux = rcc::RtcClockSource::LSI32; config.rcc.rtc_mux = rcc::RtcClockSource::LSI;
let dp = embassy_stm32::init(config); let dp = embassy_stm32::init(config);