rp: fix nvic prio bits (it's 2, not 3)

2022-08-22 16:22:37 +02:00
parent 1b95990258
commit f48391a685
2 changed files with 2 additions and 2 deletions
--- a/embassy-rp/src/gpio.rs
+++ b/embassy-rp/src/gpio.rs
@ -189,7 +189,7 @@ impl<'d, T: Pin> InputFuture<'d, T> {
        unsafe {
            let irq = interrupt::IO_IRQ_BANK0::steal();
            irq.disable();
-            irq.set_priority(interrupt::Priority::P6);
+            irq.set_priority(interrupt::Priority::P3);

            // Each INTR register is divided into 8 groups, one group for each
            // pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW,