This commit is contained in:
Grant Miller 2023-04-05 14:31:32 -05:00
parent 28b8ac4b62
commit f588105429
4 changed files with 20 additions and 130 deletions

View File

@ -7,21 +7,18 @@
#[cfg_attr(adc_v4, path = "v4.rs")]
mod _version;
#[cfg(not(any(adc_f1, adc_v1)))]
#[cfg(not(adc_f1))]
mod resolution;
#[cfg(not(adc_v1))]
mod sample_time;
#[allow(unused)]
pub use _version::*;
#[cfg(not(any(adc_f1, adc_v1)))]
#[cfg(not(adc_f1))]
pub use resolution::Resolution;
#[cfg(not(adc_v1))]
pub use sample_time::SampleTime;
use crate::peripherals;
#[cfg(not(adc_v1))]
pub struct Adc<'d, T: Instance> {
#[allow(unused)]
adc: crate::PeripheralRef<'d, T>,
@ -44,9 +41,9 @@ pub(crate) mod sealed {
}
}
#[cfg(not(any(adc_f1, adc_v2, adc_v4)))]
#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v4)))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {}
#[cfg(any(adc_f1, adc_v2, adc_v4))]
#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v4))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {}
pub trait AdcPin<T: Instance>: sealed::AdcPin<T> {}

View File

@ -1,4 +1,4 @@
#[cfg(any(adc_v2, adc_v3, adc_g0))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
pub enum Resolution {
TwelveBit,
@ -19,7 +19,7 @@ pub enum Resolution {
impl Default for Resolution {
fn default() -> Self {
#[cfg(any(adc_v2, adc_v3, adc_g0))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
{
Self::TwelveBit
}
@ -40,7 +40,7 @@ impl From<Resolution> for crate::pac::adc::vals::Res {
Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
#[cfg(any(adc_v2, adc_v3, adc_g0))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
}
}
@ -56,7 +56,7 @@ impl Resolution {
Resolution::TwelveBit => (1 << 12) - 1,
Resolution::TenBit => (1 << 10) - 1,
Resolution::EightBit => (1 << 8) - 1,
#[cfg(any(adc_v2, adc_v3, adc_g0))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
Resolution::SixBit => (1 << 6) - 1,
}
}

View File

@ -25,7 +25,7 @@ macro_rules! impl_sample_time {
};
}
#[cfg(adc_f1)]
#[cfg(any(adc_f1, adc_v1))]
impl_sample_time!(
"1.5",
Cycles1_5,

View File

@ -1,10 +1,8 @@
use core::marker::PhantomData;
use embassy_hal_common::into_ref;
use embedded_hal_02::blocking::delay::DelayUs;
use crate::adc::{AdcPin, Instance};
use crate::{pac, Peripheral};
use crate::adc::{Adc, AdcPin, Instance, Resolution, SampleTime};
use crate::Peripheral;
pub const VDDA_CALIB_MV: u32 = 3300;
pub const VREF_INT: u32 = 1230;
@ -15,39 +13,6 @@ fn enable() {
});
}
pub enum Resolution {
TwelveBit,
TenBit,
EightBit,
SixBit,
}
impl Default for Resolution {
fn default() -> Self {
Self::TwelveBit
}
}
impl Resolution {
fn res(&self) -> pac::adc::vals::Res {
match self {
Resolution::TwelveBit => pac::adc::vals::Res::TWELVEBIT,
Resolution::TenBit => pac::adc::vals::Res::TENBIT,
Resolution::EightBit => pac::adc::vals::Res::EIGHTBIT,
Resolution::SixBit => pac::adc::vals::Res::SIXBIT,
}
}
pub fn to_max_count(&self) -> u32 {
match self {
Resolution::TwelveBit => (1 << 12) - 1,
Resolution::TenBit => (1 << 10) - 1,
Resolution::EightBit => (1 << 8) - 1,
Resolution::SixBit => (1 << 6) - 1,
}
}
}
pub trait InternalChannel<T>: sealed::InternalChannel<T> {}
mod sealed {
@ -80,68 +45,9 @@ impl<T: Instance> sealed::InternalChannel<T> for Temperature {
}
}
mod sample_time {
#[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd)]
pub enum SampleTime {
/// 1.5 ADC clock cycles
Cycles1_5 = 0b000,
/// 7.5 ADC clock cycles
Cycles7_5 = 0b001,
/// 13.5 ADC clock cycles
Cycles13_5 = 0b010,
/// 28.5 ADC clock cycles
Cycles28_5 = 0b011,
/// 41.5 ADC clock cycles
Cycles41_5 = 0b100,
/// 55.5 ADC clock cycles
Cycles55_5 = 0b101,
/// 71.5 ADC clock cycles
Cycles71_5 = 0b110,
/// 239.5 ADC clock cycles
Cycles239_5 = 0b111,
}
impl SampleTime {
pub(crate) fn sample_time(&self) -> crate::pac::adc::vals::Smp {
match self {
SampleTime::Cycles1_5 => crate::pac::adc::vals::Smp::CYCLES1_5,
SampleTime::Cycles7_5 => crate::pac::adc::vals::Smp::CYCLES7_5,
SampleTime::Cycles13_5 => crate::pac::adc::vals::Smp::CYCLES13_5,
SampleTime::Cycles28_5 => crate::pac::adc::vals::Smp::CYCLES28_5,
SampleTime::Cycles41_5 => crate::pac::adc::vals::Smp::CYCLES41_5,
SampleTime::Cycles55_5 => crate::pac::adc::vals::Smp::CYCLES55_5,
SampleTime::Cycles71_5 => crate::pac::adc::vals::Smp::CYCLES71_5,
SampleTime::Cycles239_5 => crate::pac::adc::vals::Smp::CYCLES239_5,
}
}
}
impl Default for SampleTime {
fn default() -> Self {
Self::Cycles1_5
}
}
}
pub use sample_time::SampleTime;
pub struct Adc<'d, T: Instance> {
sample_time: SampleTime,
vref_mv: u32,
resolution: Resolution,
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(_peri: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
into_ref!(_peri);
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
into_ref!(adc);
enable();
// Delay 1μs when using HSI14 as the ADC clock.
@ -151,10 +57,8 @@ impl<'d, T: Instance> Adc<'d, T> {
delay.delay_us(1);
let s = Self {
adc,
sample_time: Default::default(),
vref_mv: VDDA_CALIB_MV,
resolution: Resolution::default(),
phantom: PhantomData,
};
s.calibrate();
s
@ -215,16 +119,10 @@ impl<'d, T: Instance> Adc<'d, T> {
self.sample_time = sample_time;
}
pub fn set_vref_mv(&mut self, vref_mv: u32) {
self.vref_mv = vref_mv;
}
pub fn set_resolution(&mut self, resolution: Resolution) {
self.resolution = resolution;
}
pub fn to_millivolts(&self, sample: u16) -> u16 {
((u32::from(sample) * self.vref_mv) / self.resolution.to_max_count()) as u16
unsafe {
T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
}
}
pub fn read<P>(&mut self, pin: &mut P) -> u16
@ -240,9 +138,7 @@ impl<'d, T: Instance> Adc<'d, T> {
pub fn read_internal(&mut self, channel: &mut impl InternalChannel<T>) -> u16 {
let channel = channel.channel();
unsafe {
self.read_channel(channel)
}
unsafe { self.read_channel(channel) }
}
unsafe fn read_channel(&mut self, channel: u8) -> u16 {
@ -258,17 +154,14 @@ impl<'d, T: Instance> Adc<'d, T> {
T::regs().cr().modify(|reg| reg.set_aden(true));
}
T::regs().cfgr1().modify(|reg| reg.set_res(self.resolution.res()));
T::regs().isr().modify(|reg| {
reg.set_eoc(true);
reg.set_eosmp(true);
});
// A.7.5 Single conversion sequence code example - Software trigger
T::regs()
.chselr()
.write(|reg| reg.set_chselx(channel as usize, true));
T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.sample_time()));
T::regs().chselr().write(|reg| reg.set_chselx(channel as usize, true));
T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.into()));
T::regs().cr().modify(|reg| reg.set_adstart(true));
while !T::regs().isr().read().eoc() {
// spin