add ValueArray type and respective write functions
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JuliDi
parent
e0747e937f
commit
fe7b72948a
@ -98,6 +98,14 @@ pub enum Value {
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Bit12(u16, Alignment),
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum ValueArray<'a> {
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Bit8(&'a [u8]),
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Bit12Left(&'a [u16]),
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Bit12Right(&'a [u16]),
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}
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pub struct Dac<'d, T: Instance, Tx> {
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channels: u8,
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txdma: PeripheralRef<'d, Tx>,
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@ -129,21 +137,19 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
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T::enable();
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T::reset();
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unsafe {
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T::regs().mcr().modify(|reg| {
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for ch in 0..channels {
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reg.set_mode(ch as usize, 0);
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reg.set_mode(ch as usize, 0);
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}
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});
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T::regs().mcr().modify(|reg| {
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for ch in 0..channels {
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reg.set_mode(ch as usize, 0);
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reg.set_mode(ch as usize, 0);
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}
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});
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T::regs().cr().modify(|reg| {
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for ch in 0..channels {
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reg.set_en(ch as usize, true);
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reg.set_ten(ch as usize, true);
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}
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});
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}
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T::regs().cr().modify(|reg| {
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for ch in 0..channels {
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reg.set_en(ch as usize, true);
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reg.set_ten(ch as usize, true);
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}
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});
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Self {
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channels,
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@ -161,13 +167,12 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
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}
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}
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/// Set the enable register of the given channel
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fn set_channel_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
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self.check_channel_exists(ch)?;
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_en(ch.index(), on);
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})
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}
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T::regs().cr().modify(|reg| {
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reg.set_en(ch.index(), on);
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});
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Ok(())
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}
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@ -179,112 +184,149 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
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self.set_channel_enable(ch, false)
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}
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/// Performs all register accesses necessary to select a new trigger for CH1
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pub fn select_trigger_ch1(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
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self.check_channel_exists(Channel::Ch1)?;
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unwrap!(self.disable_channel(Channel::Ch1));
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_tsel1(trigger.tsel());
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})
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}
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T::regs().cr().modify(|reg| {
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reg.set_tsel1(trigger.tsel());
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});
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Ok(())
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}
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/// Performs all register accesses necessary to select a new trigger for CH2
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pub fn select_trigger_ch2(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
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self.check_channel_exists(Channel::Ch2)?;
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unwrap!(self.disable_channel(Channel::Ch2));
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_tsel2(trigger.tsel());
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})
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}
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T::regs().cr().modify(|reg| {
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reg.set_tsel2(trigger.tsel());
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});
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Ok(())
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}
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/// Perform a software trigger on a given channel
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pub fn trigger(&mut self, ch: Channel) -> Result<(), Error> {
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self.check_channel_exists(ch)?;
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unsafe {
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig(ch.index(), true);
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});
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}
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig(ch.index(), true);
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});
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Ok(())
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}
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/// Perform a software trigger on all channels
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pub fn trigger_all(&mut self) {
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unsafe {
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig(Channel::Ch1.index(), true);
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reg.set_swtrig(Channel::Ch2.index(), true);
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})
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}
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig(Channel::Ch1.index(), true);
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reg.set_swtrig(Channel::Ch2.index(), true);
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});
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}
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pub fn set(&mut self, ch: Channel, value: Value) -> Result<(), Error> {
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self.check_channel_exists(ch)?;
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match value {
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Value::Bit8(v) => unsafe {
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T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v));
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},
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Value::Bit12(v, Alignment::Left) => unsafe {
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T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v));
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},
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Value::Bit12(v, Alignment::Right) => unsafe {
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T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v));
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},
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Value::Bit8(v) => T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v)),
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Value::Bit12(v, Alignment::Left) => T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v)),
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Value::Bit12(v, Alignment::Right) => T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v)),
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}
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Ok(())
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}
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/// Write `data` to the DAC via DMA.
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///
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/// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
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/// This will configure a circular DMA transfer that periodically outputs the `data`.
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///
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/// ## Current limitations
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/// - Only CH1 Supported
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///
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/// TODO: Allow an array of Value instead of only u16, right-aligned
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pub async fn write(&mut self, data: &[u16], circular: bool) -> Result<(), Error>
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pub async fn write_8bit(&mut self, data_ch1: &[u8], circular: bool) -> Result<(), Error>
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where
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Tx: Dma<T>,
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{
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self.write_inner(ValueArray::Bit8(data_ch1), circular).await
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}
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pub async fn write_12bit_right_aligned(&mut self, data_ch1: &[u16], circular: bool) -> Result<(), Error>
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where
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Tx: Dma<T>,
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{
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self.write_inner(ValueArray::Bit12Right(data_ch1), circular).await
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}
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pub async fn write_12bit_left_aligned(&mut self, data_ch1: &[u16], circular: bool) -> Result<(), Error>
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where
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Tx: Dma<T>,
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{
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self.write_inner(ValueArray::Bit12Left(data_ch1), circular).await
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}
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async fn write_inner(&mut self, data_ch1: ValueArray<'_>, circular: bool) -> Result<(), Error>
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where
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Tx: Dma<T>,
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{
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// TODO: Make this a parameter or get it from the struct or so...
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const CHANNEL: usize = 0;
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//debug!("Starting DAC");
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unsafe {
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T::regs().cr().modify(|w| {
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w.set_en(CHANNEL, true);
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w.set_dmaen(CHANNEL, true);
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});
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}
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// Enable DAC and DMA
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T::regs().cr().modify(|w| {
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w.set_en(CHANNEL, true);
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w.set_dmaen(CHANNEL, true);
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});
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let tx_request = self.txdma.request();
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// Use the 12 bit right-aligned register for now. TODO: distinguish values
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let tx_dst = T::regs().dhr12r(CHANNEL).ptr() as *mut u16;
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let tx_f = unsafe {
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Transfer::new_write(
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&mut self.txdma,
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tx_request,
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data,
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tx_dst,
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TransferOptions {
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circular,
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halt_transfer_ir: false,
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},
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)
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// Initiate the correct type of DMA transfer depending on what data is passed
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let tx_f = match data_ch1 {
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ValueArray::Bit8(buf) => unsafe {
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Transfer::new_write(
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&mut self.txdma,
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tx_request,
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buf,
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T::regs().dhr8r(CHANNEL).as_ptr() as *mut u8,
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TransferOptions {
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circular,
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halt_transfer_ir: false,
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},
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)
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},
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ValueArray::Bit12Left(buf) => unsafe {
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Transfer::new_write(
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&mut self.txdma,
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tx_request,
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buf,
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T::regs().dhr12l(CHANNEL).as_ptr() as *mut u16,
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TransferOptions {
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circular,
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halt_transfer_ir: false,
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},
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)
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},
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ValueArray::Bit12Right(buf) => unsafe {
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Transfer::new_write(
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&mut self.txdma,
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tx_request,
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buf,
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T::regs().dhr12r(CHANNEL).as_ptr() as *mut u16,
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TransferOptions {
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circular,
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halt_transfer_ir: false,
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},
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)
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},
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};
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//debug!("Awaiting tx_f");
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tx_f.await;
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// finish dma
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unsafe {
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// TODO: Do we need to check any status registers here?
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// TODO: Do we need to check any status registers here?
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T::regs().cr().modify(|w| {
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// Disable the DAC peripheral
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w.set_en(CHANNEL, false);
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// Disable the DMA. TODO: Is this necessary?
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w.set_dmaen(CHANNEL, false);
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});
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T::regs().cr().modify(|w| {
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// Disable the dac peripheral
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w.set_en(CHANNEL, false);
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// Disable the DMA. TODO: Is this necessary?
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w.set_dmaen(CHANNEL, false);
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});
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}
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Ok(())
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}
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}
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