2218d30c80
STM32: Remove vestigal build.rs cfgs, add new flashsize_X and package_X cfgs, use in F3 RCC
2023-11-25 00:29:45 +01:00
bbd12c9372
stm32: update metapac
2023-10-17 20:31:44 -05:00
b24520579a
rcc: ahb/apb -> hclk/pclk
2023-10-15 19:51:35 -05:00
b91d1eaca0
stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.
2023-10-11 04:12:38 +02:00
0cfa8d1bb5
stm32/rcc: use more PLL etc enums from PAC.
2023-10-11 00:12:33 +02:00
c28a6bdd0b
stm32: generate adc_common
2023-09-15 17:35:53 -05:00
08415e001e
stm32/f3: add high res for hrtim and misc.
2023-09-10 13:33:17 -05:00
f502271940
stm32: add initial adc f3 impl
2023-09-05 16:46:57 -05:00
48085939e7
stm32/rcc: rename common to bus
2023-08-27 08:35:13 -05:00
6e13f5b387
rustfmt
2023-06-30 18:33:22 -05:00
1fd5022e72
Refactor IWDG to use LSI frequency from RCC
2022-07-10 20:59:36 +03:00
c90968bb70
stm32/rcc: Modify only relevant CFGR bits and keep the settings previously done.
...
PLL settings remained intact because these bits are not writable when PLL is enabled,
but prescaler settings were overwritten by selecting PLL as sysclk (CFGR.SW[1:0]).
2022-05-12 09:09:39 +02:00
1a216958ac
stm32/rcc: Set flash prefetch buffer and half cycle access according to AHB clock prescaler
2022-05-12 09:09:39 +02:00
2abb04d4d1
stm32/rcc: fix f3 build failure.
2022-02-23 03:42:46 +01:00
39d06b59cd
Update stm32-data
2022-02-14 02:12:06 +01:00
8bb41a3281
stm32f3: fix nonexistent cfg tests
...
The rcc code was taken from stm32-rs which uses 'x' features, but
embassy uses features with full chip names.
Add these 'x' wildcards as cfgs and use them in rcc.
They will be useful for USB too.
2022-02-02 22:53:03 +03:00
2eb0cc5df7
stm32/rcc: remove Rcc struct, RccExt trait.
...
All the RCC configuration is executed in init().
2022-01-05 00:00:44 +01:00
b06e705a73
stm32/rcc: change family-specific code from dirs to single files.
...
Consistent with how other peripherals handle their versions.
2022-01-04 19:28:15 +01:00
