max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
2,555 Commits 67 Branches 32 Tags 16 MiB
3696226fe8
Commit Graph

2555 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
bors[bot]
5f39f13616
Merge #670 
670: Make UART futures Send r=Dirbaio a=chemicstry

This is a quick fix to make `Uart` futures implement `Send`.

Previously they were `!Send`, because pointer to the data register was held across an await point. Simple rearrange fixes the issue.

Co-authored-by: chemicstry <chemicstry@gmail.com>
 2022-03-17 18:09:57 +00:00
chemicstry
d26b751edc Add comments 2022-03-17 19:41:44 +02:00
chemicstry
051c6350ea Make UART futures Send 2022-03-17 18:23:47 +02:00
chemicstry
a9854924fa Revert settings.json 2022-03-17 02:22:04 +02:00
chemicstry
c24d482d51 Fix DMA channels 2022-03-17 01:54:56 +02:00
chemicstry
24a9e19062 More cleanup 2022-03-17 01:12:29 +02:00
chemicstry
f87c497315 Format 2022-03-17 00:03:24 +02:00
chemicstry
9d71acc49e Cleanup 2022-03-16 23:55:07 +02:00
chemicstry
224071f08e Add F7 example 2022-03-16 23:44:02 +02:00
chemicstry
f08f4df180 Cleanup 2022-03-16 20:33:46 +02:00
chemicstry
ea467e0acb Rename DMA trait 2022-03-16 20:30:57 +02:00
chemicstry
8a8e5c4b73 Fix SDMMC v2 and add H7 example 2022-03-16 20:20:39 +02:00
chemicstry
48fc48ea7d Fix BDMA 2022-03-16 19:41:34 +02:00
chemicstry
bf4a38ac06 Use RCC frequency instead of config 2022-03-16 19:09:37 +02:00
chemicstry
6d547b1143 SDIO working on stm32f4 2022-03-16 18:52:27 +02:00
chemicstry
34b5175d2c Add more options to DMA 2022-03-16 18:52:06 +02:00
bors[bot]
75e5b39799
Merge #668 
668: Update chiptool. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
 2022-03-15 22:19:59 +00:00
Dario Nieuwenhuis
3528f42868 Update chiptool. 2022-03-15 23:19:17 +01:00
bors[bot]
01f8aa19a5
Merge #667 
667: Remove duplicate stm32-metapac/src/common.rs with chiptool r=Dirbaio a=nviennot

There's a duplicate file common.rs with the chiptool crate. This PR makes the source of truth the one in chiptool.

This PR is a good pair with https://github.com/embassy-rs/chiptool/pull/4 

Co-authored-by: Nicolas Viennot <nicolas@viennot.biz>
 2022-03-15 20:54:12 +00:00
bors[bot]
a61f68144a
Merge #665 
665: Rebuild when the chip's JSON changes r=Dirbaio a=nviennot



Co-authored-by: Nicolas Viennot <nicolas@viennot.biz>
 2022-03-15 19:39:01 +00:00
chemicstry
2d224cf6a0 Update 2022-03-15 19:58:19 +02:00
bors[bot]
da9c0efaad
Merge #661 
661: Add support for splitting stm32 usart into TX and RX r=lulf a=lulf

* Keeps existing API for usart, but wraps it in Tx and Rx sub-types
* Adds split() method similar to nRF for getting indepdendent TX and RX
  parts
* Implements e-h traits for TX and RX types

Co-authored-by: Ulf Lilleengen <ulf.lilleengen@gmail.com>
 2022-03-15 10:08:01 +00:00
Ulf Lilleengen
e09bde9345 Add support for splitting stm32 usart into TX and RX 
* Keeps existing API for usart, but wraps it in Tx and Rx sub-types
* Adds split() method similar to nRF for getting indepdendent TX and RX
  parts
* Implements e-h traits for TX and RX types
* Add stm32h7 example
 2022-03-15 10:35:37 +01:00
Nicolas Viennot
cfa7f4e55b Remove duplicate stm32-metapac/src/common.rs with chiptool 2022-03-15 04:17:55 -04:00
Nicolas Viennot
680ed11038 Rebuild when the chip definition changes 2022-03-15 03:29:13 -04:00
bors[bot]
cb1be3983a
Merge #666 
666: stm32/spi: Clear rx fifo in blocking methods r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
 2022-03-15 03:14:07 +00:00
Dario Nieuwenhuis
1dc618f0e4 stm32/spi: fix blocking transfer hanging after async. 2022-03-15 04:13:33 +01:00
Grant Miller
49ef19c0b2 stm32/spi: Clear rx fifo in blocking methods 2022-03-14 21:55:37 -05:00
bors[bot]
ff1215c6f9
Merge #664 
664: stm32: more spi fixes r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
 2022-03-15 01:39:38 +00:00
Dario Nieuwenhuis
059b164234 stm32/spi: do not clear rxfifo in SPIv3, the hw already does it. 2022-03-15 02:37:08 +01:00
Dario Nieuwenhuis
4579192832 stm32/spi: fix hang in SPIv3 by not waiting for rxfifo empty in finish_dma. 2022-03-15 02:36:34 +01:00
Dario Nieuwenhuis
3d6592d22d stm32/spi: check zero-length trasnfers. 2022-03-15 02:14:24 +01:00
Dario Nieuwenhuis
06f35c2517 stm32/spi: more exhaustive test. 2022-03-15 02:14:24 +01:00
Dario Nieuwenhuis
306110f56e stm32/spi: implement async trasnfer_in_place 2022-03-15 00:40:48 +01:00
bors[bot]
8ef8ab1707
Merge #663 
663: stm32: Spi bugfixes r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
 2022-03-14 23:25:02 +00:00
Grant Miller
f1d6c95205 rustfmt 2022-03-14 18:22:41 -05:00
Grant Miller
71632648c7 Fix zero-length-slice bugs 2022-03-14 18:14:55 -05:00
Grant Miller
15c533fe2a Fix async write bug 2022-03-14 18:04:31 -05:00
bors[bot]
064170fce0
Merge #662 
662: stm32: Finish unifying spi versions r=Dirbaio a=GrantM11235

Notable changes:
- `set_word_size` is always called before disabling SPE. This is important because `set_word_size` may or may not re-enable SPE.
- The rx buffer is flushed on v1 as well. I don't know if this is required.
- All functions are now generic over word size

Co-authored-by: Grant Miller <GrantM11235@gmail.com>
 2022-03-14 22:20:52 +00:00
Grant Miller
6e00c58854 Make all functions generic over word size 2022-03-14 16:53:50 -05:00
Grant Miller
f0b62bc8e0 Use const REGS 2022-03-14 15:56:08 -05:00
Grant Miller
482ffea4dd Finish unification 2022-03-14 15:56:08 -05:00
Grant Miller
406b1b3dd2 Finish matching versions 2022-03-14 15:56:08 -05:00
Grant Miller
7cd6f00a90 Add set_txdmaen and set_rxdmaen functions 2022-03-14 15:56:08 -05:00
Grant Miller
444b37fcdf Add flush_rx_fifo function 2022-03-14 15:56:08 -05:00
Grant Miller
683c11f399 Call set_word_size before disabling SPE 2022-03-14 15:56:08 -05:00
bors[bot]
3ae0923d45
Merge #660 
660: Tell bors to delete merged branches r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
 2022-03-14 18:04:58 +00:00
Grant Miller
d137d1f707 Tell bors to delete merged branches 2022-03-14 12:59:48 -05:00
bors[bot]
db8050b388
Merge #627 
627: Update Rust nightly, embedded-hal 1.0, embedded-hal-async. r=Dirbaio a=Dirbaio

Includes the SpiDevice/SpiBus split.  https://github.com/rust-embedded/embedded-hal/pull/351
Includes the GAT where clause location change. https://github.com/rust-lang/rust/issues/89122


Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
 2022-03-10 23:38:47 +00:00
Dario Nieuwenhuis
9bad9365dc Update rust nightly, embedded-hal 1.0, embedded-hal-async. 2022-03-11 00:38:07 +01:00