Dario Nieuwenhuis
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0272deb158
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stm32/rcc: add shared code for hsi48 with crs support.
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2023-11-05 23:52:54 +01:00 |
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Dario Nieuwenhuis
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8911a4d855
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stm32/rcc: switch to modern api for l0, l1.
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2023-11-05 03:06:13 +01:00 |
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shakencodes
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bc07539133
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Fix missed field in cfg'd code
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2023-11-01 13:30:04 -07:00 |
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shakencodes
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b4a82b7ed4
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Correct adc_clock_source for all µprocs in l4l5.rs
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2023-11-01 13:22:50 -07:00 |
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shakencodes
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e2688dda22
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Eliminates redefinition of AdcClockSource
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2023-11-01 12:06:19 -07:00 |
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shakencodes
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d0d8585e4c
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Reinstate rcc::Config adc_clock_source field
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2023-11-01 11:46:17 -07:00 |
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Dario Nieuwenhuis
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a39ae12edc
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stm32/rcc: misc cleanups.
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2023-10-23 17:36:21 +02:00 |
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Dario Nieuwenhuis
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0ef1cb29f7
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stm32/rcc: merge wb into l4/l5.
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2023-10-23 17:36:21 +02:00 |
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Dario Nieuwenhuis
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b9e13cb5d1
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stm32/rcc: merge wl into l4/l5.
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2023-10-23 00:31:36 +02:00 |
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Dario Nieuwenhuis
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412bcad2d1
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stm32: rename HSI16 -> HSI
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2023-10-22 22:39:55 +02:00 |
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xoviat
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0fb677aad7
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stm32: update metapac
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2023-10-20 20:21:53 -05:00 |
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Dario Nieuwenhuis
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361fde35cf
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stm32/rcc: wait for mux switch.
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2023-10-18 04:32:18 +02:00 |
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xoviat
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bbd12c9372
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stm32: update metapac
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2023-10-17 20:31:44 -05:00 |
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xoviat
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a3574e519a
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stm32: update metapac
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2023-10-16 20:04:10 -05:00 |
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Dario Nieuwenhuis
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aff77d2b65
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stm32/rng: add test.
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2023-10-16 05:35:29 +02:00 |
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Dario Nieuwenhuis
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18e96898ea
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stm32/rcc: unify L4 and L5.
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2023-10-16 04:00:51 +02:00 |
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