Commit Graph

281 Commits

Author SHA1 Message Date
pennae
fdd6e08ed6 rp: hook up softfloat rom intrinsics
rp-hal has done this very well already, so we'll just copy their entire
impl again. only div.rs needed some massaging because our sio access
works a little differently, everything else worked as is.
2023-04-19 23:04:47 +02:00
bors[bot]
38c5b97df0
Merge #1378
1378: Add ability to invert UART pins, take 2 r=Dirbaio a=jakewins

Same PR as before, except this now works :) 

There was a minor hiccup in the UartRx code where the rx pin got passed as the tx argument, so the invert settings didn't get applied. With this fix, my local setup at least is happily reading inverted uart data.

Co-authored-by: Jacob Davis-Hansson <jake@davis-hansson.com>
2023-04-18 15:48:47 +00:00
Jacob Davis-Hansson
21ea98810a Pass rx pin to right init arg 2023-04-18 17:44:19 +02:00
bors[bot]
99dcbf00c4
Merge #1372
1372: rp: add division intrinsics r=Dirbaio a=pennae

rp2040-hal adds division intrinsics using the hardware divider unit in the SIO, as does the pico-sdk itself. using the hardware is faster than the compiler_rt implementations, and more compact too.

since embassy does not expose the hardware divider in any way (yet?) we could go even further an remove the state-saving code rp2040-hal needs, but that doesn't seem to be worth it.

Co-authored-by: pennae <github@quasiparticle.net>
2023-04-16 23:23:47 +00:00
Dario Nieuwenhuis
a258e15c23 rp: switch to released rp-pac v1.0 2023-04-16 23:59:26 +02:00
pennae
7a682ec02a rp: add division intrinsics
rp2040-hal adds division intrinsics using the hardware divider unit in
the SIO, as does the pico-sdk itself. using the hardware is faster than
the compiler_rt implementations, and more compact too.
2023-04-16 19:45:18 +02:00
Jacob Davis-Hansson
81f10e136a outover instead of inover 2023-04-15 15:13:44 +02:00
Dario Nieuwenhuis
f681b9d4e5 Remove the _todo_embedded_hal_serial impls. EH will probably not have these serial traits. 2023-04-15 00:58:58 +02:00
Jacob Davis-Hansson
b9fc2a6b33 Add ability to invert UART pins
This is useful in some cases where the surrounding circuit
for some reason inverts the UART signal, for instance if you're talking
to a device via an optocoupler.
2023-04-14 21:08:24 +02:00
Dario Nieuwenhuis
577f060d24 Release embassy-sync v0.2.0 2023-04-13 23:40:49 +02:00
Brooks J Rady
1fbb8f0b32 feat(rp): add Wait impl to OutputOpenDrain
A while ago `OutputOpenDrain` was made to implement `InputPin`,
something that allowed drivers for various one-wire protocols to be
written, but it's been lacking a `Wait` implementation — something
that's needed to write async versions of these drivers.

This commit also adds `get_level()` to `OutputOpenDrain`, since
`is_high()` and `is_low()` were already implemented, but `get_level()`
itself was missing.
2023-04-09 09:15:57 +01:00
Dario Nieuwenhuis
be37eee13d Update embedded-hal crates. 2023-04-06 22:41:50 +02:00
bors[bot]
08f911d25e
Merge #1318
1318: rp: Allow zero len reads for buffered uart r=Dirbaio a=timokroeger

Prevents the read methods from getting stuck forever.

cc `@MathiasKoch` can you test if this fixes the problem you described in the chat?

Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
2023-04-02 18:33:36 +00:00
Timo Kröger
7ef6a3cfb2 rp: Allow zero len writes for buffered uart
Prevents the write methods from getting stuck forever.
2023-04-02 14:36:32 +02:00
Timo Kröger
f78aa4f936 rp: Allow zero len reads for buffered uart
Prevents the read methods from getting stuck forever.
2023-04-01 14:31:24 +02:00
Thierry Fleury
0e13fe9925 Fix set_baudrate on RP-PICO 2023-04-01 11:44:49 +02:00
bors[bot]
9c7b9b7848
Merge #1288
1288: fix(rp): spi transfer r=elpiel a=elpiel

Fixes #1181 

Co-authored-by: Lachezar Lechev <elpiel93@gmail.com>
2023-03-26 15:55:58 +00:00
Lachezar Lechev
7be63b3468
fix: spi transfer bug and additions to test
Signed-off-by: Lachezar Lechev <elpiel93@gmail.com>
2023-03-26 18:14:17 +03:00
Lachezar Lechev
9939d43800
fix: PR comment
Signed-off-by: Lachezar Lechev <elpiel93@gmail.com>
2023-03-24 12:14:23 +02:00
Mathias
88483b5abe Fix return type for EH-nb traits 2023-03-23 14:26:37 +01:00
Mathias
04f90e3a9d Add embedded-io blocking Read + Write for BufferedUart 2023-03-23 14:18:19 +01:00
Lachezar Lechev
7a4db1da26
fix(rp): spi transfer
Signed-off-by: Lachezar Lechev <elpiel93@gmail.com>
2023-03-20 16:34:30 +02:00
Mathias
89a371d10c Add HIL test for into_buffered uart on embassy-rp 2023-03-14 12:46:58 +01:00
Mathias
bce1ce7dcb Allow upgrading a blocking uart to a BufferedUart, and implement blocking serial traits for BufferedUart 2023-03-14 10:36:30 +01:00
Caleb Jamison
7bdb3abad7 Swap debug! for trace! in rp gpio
When using gpio pin changes for things like peripheral interrupts these
debug! calls flood defmt, making it difficult to find what you're
actually looking for.
2023-03-02 13:59:52 -05:00
Lachezar Lechev
5cb0c8cc01
fix: rp - disable Pull-down/up resistors for ADC read
Signed-off-by: Lachezar Lechev <elpiel93@gmail.com>
2023-02-28 09:22:38 +02:00
Andres Hurtado Lopez
2331d58aa6 RP-PICO UART adding set_baudrate: missing to run rust-fmt 2023-02-26 21:23:51 -05:00
Andres Hurtado Lopez
482ba835c4 RP-PICO UART adding set_baudrate: Changing static call from specific type to a Self (requires adding lifetime specifier) 2023-02-26 19:20:08 -05:00
Andres Hurtado Lopez
7172dfd083 RP-PICO UART adding set_baudrate: refactoring of methods 2023-02-26 19:14:25 -05:00
Andres Hurtado Lopez
8fb380b180 RP-PICO UART adding set_baudrate 2023-02-26 18:40:23 -05:00
Grant Miller
7be4337de9 Add #[must_use] to all futures 2023-02-24 13:01:41 -06:00
sekoia
e641db1f75 Fix a typo in "PioPeripheral" 2023-02-15 14:10:07 +01:00
Slushee
dfc58ad3a2
Add copy to Level enum in embassy-rp gpio module 2023-02-13 17:29:35 +00:00
Slushee
1626a4a74b
Add clone to embassy_rp::gpio::Level 2023-02-13 17:12:50 +00:00
Dario Nieuwenhuis
ca10fe7135 usb: docs 2023-01-31 22:27:19 +01:00
nitroxis
1e60c60afd rp: allow isochronous USB endpoints to be up to 1023 in size 2023-01-27 07:24:49 +01:00
Matt Johnston
83af513424 rp gpio: make pin_bank() inline
This allows set_high() etc to be inlined, toggling pins
should be much faster.
2023-01-19 13:36:40 +08:00
bors[bot]
b6c8505697
Merge #1142
1142: More rp2040 BufferedUart fixes r=Dirbaio a=timokroeger

* Refactor init code
* Make it possible to drop RX without breaking TX (or vice versa)
* Correctly handle RX buffer full scenario

Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
2023-01-14 00:07:02 +00:00
chemicstry
ce842fe28c Refactor embassy-usb address handling to allow reordering of status resoponse 2023-01-11 17:47:12 +01:00
Timo Kröger
539f97da53 rp: Fix formatting string to please CI 2023-01-05 22:00:44 +01:00
Timo Kröger
1096a9746c rp: Improve BufferedUart interrupt handling
* Only clear interrupt flags that have fired (so that we do not lose any error flags)
* Enable RX interrupt when a read is requested, disable it when the RX buffer is full
* Rework TX interrupt handling: its "edge" triggered by a FIFO threshold
2023-01-05 18:45:58 +01:00
Pedro Ferreira
6d4c6e0481 rp2040: add {tx,rx}-only constructors to UART 2023-01-04 21:11:19 +01:00
Timo Kröger
840a75674b rp: Disable RX interrupts when ring buffer is full
When data is in the RX fifo the RX timeout interrupt goes high again even after clearing it.
The result is a deadlock because execution is stuck in the interrupt handler. No other code
can run to clear the receive buffer.
Enable and disable RX interrupts based on the buffer fill level.
Use the same approach for the TX code path.
2023-01-04 16:53:43 +01:00
Timo Kröger
a24037edf9 rp: Fix BufferedUart drop code
Only unregister the interrupt handler when both parts are inactive
2023-01-04 15:59:03 +01:00
Timo Kröger
68c186309f rp: Common init function for BufferedUart
BufferedUart, BufferedUartRx and BufferedUartTX can all use the same init code.
2023-01-04 15:58:26 +01:00
Timo Kröger
e4f457646f rp: Fill and empty FIFOs in buffered uart interrupt
Fixes an issue where only the first byte was transmitted.
Should improve throughput aswell.
2022-12-27 11:28:52 +01:00
Dario Nieuwenhuis
41d6316984 rp: switch to released 0.2.1 pio crate. 2022-12-26 22:30:22 +01:00
bors[bot]
c29657f95a
Merge #1128
1128: Add missing SPI pins r=Dirbaio a=pferreir

The SPI definitions lack the pins which are not accessible on the pico (but are so e.g. on the stamp).

Co-authored-by: Pedro Ferreira <pedro@dete.st>
2022-12-25 23:52:33 +00:00
Pedro Ferreira
f2fb9a2ca6 Add missing SPI pins 2022-12-25 23:49:04 +00:00
kalkyl
e090ab1915 Remove lifetime, use pac fields 2022-12-24 03:22:51 +01:00