Commit Graph

4452 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
14e0090cb1 stm32/dma: remove separate process_tcif. 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
45843034ec Actually clear idle flag 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
7757405908 Remove unused import 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
fc268df6f5 Support overflow detection for more than one ring-period 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
4ea6662e55 Do not disable dma request when idle line is detected 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
49455792cb Ring-buffered uart rx with one-period overrun detection 2023-05-01 22:42:36 +02:00
bors[bot]
855c0d1423
Merge #1376
1376: rtc: cleanup and consolidate r=Dirbaio a=xoviat

This removes an extra file that I left in, adds an example, and consolidates the files into one 'v2' file.

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-01 19:32:06 +00:00
bors[bot]
05c36e05f9
Merge #1414
1414: rp: report errors from buffered and dma uart receives r=Dirbaio a=pennae

neither of these reported errors so far, which is not ideal. add error reporting to both of them that matches the blocking error reporting as closely as is feasible, even allowing partial receives from buffered uarts before errors are reported where they would have been by the blocking code. dma transfers don't do this, if an errors applies to any byte in a transfer the entire transfer is nuked (though we probably could report how many bytes have been transferred).

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-01 15:35:39 +00:00
pennae
b58b9ff390 rp/uart: report errors from dma receive 2023-05-01 15:36:53 +02:00
pennae
1d5adb8974 rp/uart: extract fifo draining from blocking_read
this will also be needed for dma operations.
2023-05-01 15:32:58 +02:00
pennae
be66e0f7ce rp/uart: make dma multicore-safe
running rx and tx on different cores could lead to hangs if the dmacr
register modifys run concurrently. this is bad.
2023-05-01 15:32:58 +02:00
pennae
861f49cfd4 rp/uart: report errors from buffered uart
this reports errors at the same location the blocking uart would, which
works out to being mostly exact (except in the case of overruns, where
one extra character is dropped). this is actually easier than going
nuclear in the case of errors and nuking both the buffer contents and
the rx fifo, both of which are things we'd have to do in addition to
what's added here, and neither are needed for correctness.
2023-05-01 15:32:58 +02:00
pennae
7ab9fe0522 rp/uart: extract common code from async and blocking buffered reads
once we add error propagation the common code will become even larger,
so it makes sense to move it out.
2023-05-01 15:24:03 +02:00
pennae
1c8492bab2 tests/rp: test error conditions for uart 2023-05-01 15:22:56 +02:00
pennae
19588a9e6f rp/uart: rename state to buffered_state
we'll add a dma state soon as well.
2023-05-01 15:22:39 +02:00
pennae
1d2f6667df rp/uart: add set-break functions
sending break conditions is necessary to implement some protocols, and
the hardware supports this natively. we do have to make sure that we
don't assert a break condition while the uart is busy though, otherwise
the break may be inserted before the last character in the tx fifo.
2023-05-01 15:16:30 +02:00
bors[bot]
ac0ea406f9
Merge #1395
1395: rp/pio: bit of a rework r=Dirbaio a=pennae

the pio module is currently in a Bit of a State. this is far from all that's needed to make it more useful, but it's a start.

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-01 11:00:48 +00:00
pennae
7336b8cd88 rp/uart: add UartRx::new_blocking 2023-05-01 13:00:40 +02:00
pennae
bcbe3040a1 tests/rp: fix buffered uart test
the rp uart receive fifo is 32 entries deep, so the 31 byte test data
fits into it without needing any buffering. extend to 48 bytes to fill
the entire fifo and the 16 byte test buffer.
2023-05-01 13:00:40 +02:00
pennae
f4ade6af8b rp/pio: write instr memory only from common
instruction memory is a shared resource. writing it only from PioCommon
clarifies this, and perhaps makes it more obvious that multiple state
machines can share the same instructions.

this also allows *freeing* of instruction memory to reprogram the
system, although this interface is not entirely safe yet. it's safe in
the sense rusts understands things, but state machines may misbehave if
their instruction memory is freed and rewritten while they are running.
fixing this is out of scope for now since it requires some larger
changes to how state machines are handled. the interface provided
currently is already unsafe in that it lets people execute instruction
memory that has never been written, so this isn't much of a drawback for now.
2023-05-01 12:58:57 +02:00
pennae
fa1ec29ae6 rp/pio: remove a bunch of unnecessary let _ = self 2023-05-01 12:58:57 +02:00
pennae
58e727d3b9 rp/pio: move non-sm-specific methods to PioCommon
pin and irq operations affect the entire pio block. with pins this is
not very problematic since pins themselves are resources, but irqs are
not treated like that and can thus interfere across state machines. the
ability to wait for an irq on a state machine is kept to make
synchronization with user code easier, and since we can't inspect loaded
programs at build time we wouldn't gain much from disallowing waits from
state machines anyway.
2023-05-01 12:58:57 +02:00
pennae
4cd5ed81aa rp/pio: remove top-level PIOS array
this mainly removes the need for explicit indexing to get the pac
object. runtime effect is zero, but arguably things are a bit easier to
read with less indexing.
2023-05-01 12:58:57 +02:00
pennae
4618b79b22 rp/pio: seal PioInstance, SmInstance
seems prudent to hide access to the internals.
2023-05-01 12:58:57 +02:00
pennae
db16b6ff3f rp/pio: don't call dma::init so much
this is already done during platform init. it wasn't even sound in the
original implementation because futures would meddle with the nvic in
critical sections, while another (interrupt) executor could meddle with
the nvic without critical sections here. it is only accidentally sound
now and only if irq1 of both pios isn't used by user code. luckily the
worst we can expect to happen is interrupt priorities being set wrong,
but wrong is wrong is wrong.
2023-05-01 12:58:57 +02:00
pennae
a9074fd09b rp/pio: enable pio interrupts only once
since we never actually *disable* these interrupts for any length of
time we can simply enable them globally. we also initialize all pio
interrupt flags to not cause system interrupts since state machine
irqa are not necessarily meant to cause a system interrupt when set. the
fifo interrupts are sticky and can likewise only be cleared inside the
handler by disabling them.
2023-05-01 12:58:57 +02:00
pennae
f2469776f4 rp/pio: use atomic accesses, not critical sections
atomic accesses are not only faster but also can't conflict with other
critical sections.
2023-05-01 12:53:32 +02:00
pennae
a10850a6da rp/pio: handle all pio irqs in one handler
dma does this too, also with 12 bits to check. this decreases code size
significantly (increasing speed when the cache is cold), frees up an
interrupt handler, and avoids read-modify-write cycles (which makes each
processed flag cheaper). due to more iterations per handler invocation
the actual runtime of the handler body remains roughly the
same (slightly faster at O2, slightly slower at Oz).

notably wakers are now kept in one large array indexed by the irq
register bit number instead of three different arrays, this allows for
machine code-level optimizations of waker lookups.
2023-05-01 12:53:32 +02:00
bors[bot]
ce04b732d1
Merge #1407
1407: Remove legacy LoRa drivers r=Dirbaio a=ceekdee

Remove legacy LoRa drivers and associated configuration.

Co-authored-by: ceekdee <taigatensor@gmail.com>
Co-authored-by: Chuck Davis <taigatensor@gmail.com>
2023-04-30 19:36:36 +00:00
Chuck Davis
ff6748a0d8
Merge branch 'embassy-rs:master' into master 2023-04-30 11:09:43 -05:00
bors[bot]
7646f18836
Merge #1405
1405: add IPCC peripheral for stm32wb r=xoviat a=OueslatiGhaith

Hello again,

This pull request is related to #1397 and #1401, inspired by #24, and was tested on an stm32wb55rg.

This pull request aims to add the IPCC peripheral for stm32wb microcontrollers.
I am debating whether this should be included in the public API, since the IPCC peripheral would be typically managed by the TL Mailbox, not by the app directly.

Co-authored-by: OueslatiGhaith <ghaith.oueslati@enis.tn>
2023-04-30 15:23:55 +00:00
bors[bot]
41fe718ea8
Merge #1412
1412: stm32/uart: abort on error r=Dirbaio a=xoviat

This PR aborts the DMA transfer in the event of a UART error. Otherwise, the transfer will never complete, and an error will not be returned.

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-04-30 14:58:36 +00:00
bors[bot]
94c6727b3f
Merge #1410
1410: Add `Transactional` trait to rp's i2c impl r=Dirbaio a=DasLixou

Fixes #1409 

Co-authored-by: Lixou <82600264+DasLixou@users.noreply.github.com>
Co-authored-by: xoviat <49173759+xoviat@users.noreply.github.com>
2023-04-30 07:52:49 +00:00
xoviat
b77794c9a7 stm32/uart: abort on error 2023-04-28 21:43:03 -05:00
xoviat
ba886b45b8
rustfmt 2023-04-28 16:46:32 -05:00
Lixou
2119b8e1ca
Add Transactional trait to rp's i2c impl 2023-04-28 21:23:32 +02:00
Chuck Davis
49bed094a3
Merge branch 'embassy-rs:master' into master 2023-04-28 13:35:22 -05:00
ceekdee
49ecd8d7c5 Remove external-lora-phy feature. 2023-04-28 13:33:20 -05:00
OueslatiGhaith
29cc661dca removed constrain method 2023-04-28 10:17:01 +01:00
bors[bot]
3e730aa8b0
Merge #1403
1403: Bump versions preparing for -macros and -executor release r=lulf a=lulf

I'd like to propose a new release of embassy-macros and embassy-executor, as there is a challenge with some of the features changing since 0.1.1 when using libraries that depend on 0.1.1 with applications that patch to use git versions.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2023-04-27 18:20:10 +00:00
Ulf Lilleengen
28a3454846 add changelog 2023-04-27 20:19:07 +02:00
OueslatiGhaith
91cddd50f6 reversed changes in Cargo.toml 2023-04-27 18:26:19 +01:00
ceekdee
9d610c6866 Remove legacy LoRa drivers. 2023-04-27 11:05:33 -05:00
bors[bot]
03d6363d5a
Merge #1406
1406: rp: DMA behaviour during flash operations r=Dirbaio a=kalkyl

This PR changes the old behaviour during flash operations where all DMA transfers were paused during the flash operation.
The new approach is to wait for any DMA operating in flash region to finish and let RAM transfers continue.

Co-authored-by: kalkyl <henrik.alser@me.com>
2023-04-27 15:28:11 +00:00
OueslatiGhaith
d960bf344a fixed missing imports 2023-04-27 16:22:41 +01:00
kalkyl
31b54e0fbd rustfmt 2023-04-27 17:09:16 +02:00
OueslatiGhaith
3ba73b5ff4 fixed mistake with casting channel to a usize 2023-04-27 16:08:57 +01:00
OueslatiGhaith
8c733c29cc add IPCC peripheral for stm32wb 2023-04-27 16:03:22 +01:00
kalkyl
278818395e rp: DMA behaviour during FLASH operations 2023-04-27 16:48:25 +02:00
Ulf Lilleengen
42a8f1671d Bump versions preparing for -macros and -executor release 2023-04-27 11:54:22 +02:00