rp/pio: don't call dma::init so much
this is already done during platform init. it wasn't even sound in the original implementation because futures would meddle with the nvic in critical sections, while another (interrupt) executor could meddle with the nvic without critical sections here. it is only accidentally sound now and only if irq1 of both pios isn't used by user code. luckily the worst we can expect to happen is interrupt priorities being set wrong, but wrong is wrong is wrong.
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@ -8,7 +8,7 @@ use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
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use embassy_hal_common::PeripheralRef;
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use embassy_sync::waitqueue::AtomicWaker;
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use crate::dma::{self, Channel, Transfer};
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use crate::dma::{Channel, Transfer};
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use crate::gpio::sealed::Pin as SealedPin;
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use crate::gpio::{Drive, Pin, Pull, SlewRate};
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use crate::pac::dma::vals::{DataSize, TreqSel};
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@ -949,7 +949,6 @@ pub trait PioStateMachine: Sized + Unpin {
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fn dma_push<'a, C: Channel>(&'a self, ch: PeripheralRef<'a, C>, data: &'a [u32]) -> Transfer<'a, C> {
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unsafe {
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dma::init();
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let pio_no = Self::Pio::PIO_NO;
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let sm_no = Self::Sm::SM_NO;
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let p = ch.regs();
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@ -973,7 +972,6 @@ pub trait PioStateMachine: Sized + Unpin {
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fn dma_pull<'a, C: Channel>(&'a self, ch: PeripheralRef<'a, C>, data: &'a mut [u32]) -> Transfer<'a, C> {
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unsafe {
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dma::init();
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let pio_no = Self::Pio::PIO_NO;
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let sm_no = Self::Sm::SM_NO;
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let p = ch.regs();
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