Scott Mabin
6770d8e8a6
Allow the RTC clock source to be configured with the new RTC mechanism
2023-09-06 00:04:09 +01:00
xoviat
48085939e7
stm32/rcc: rename common to bus
2023-08-27 08:35:13 -05:00
Sebastian Goll
df6952648e
Make sure to check RCC settings for compatibility before applying
2023-08-16 14:11:09 +02:00
Dario Nieuwenhuis
3aef5999d5
Merge pull request #1716 from xoviat/rcc-p
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stm32/rcc: extract and combine ahb/apb prescalers
2023-07-30 20:43:54 +00:00
xoviat
2f18770e27
stm32/rcc: extract and combine ahb/apb prescalers
2023-07-30 09:52:30 -05:00
Scott Mabin
e0ce7fcde7
stm32f2 pll overflow with crystal
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With a large enough HSE input frequency, the vco clock calculation will
overflow a u32. Therefore, in this specific case we have to use the
inner value and cast to u64 to ensure the mul isn't clipped before
applying the divider.
2023-07-30 01:00:53 +01:00
Dario Nieuwenhuis
e892014b65
Update stm32-metapac, includes chiptool changes to use real Rust enums now.
2023-06-29 02:01:33 +02:00
Sebastian Goll
f3699e67b9
Fix typo in derivation of PLLP divisor
2023-04-12 02:07:31 +02:00
chemicstry
3bf1e1d4aa
Fix f2, wl compilation
2022-07-10 21:46:14 +03:00
chemicstry
1fd5022e72
Refactor IWDG to use LSI frequency from RCC
2022-07-10 20:59:36 +03:00
Dario Nieuwenhuis
a8703b7598
Run rustfmt.
2022-06-12 22:22:31 +02:00
Joonas Javanainen
e88559c5ca
Use defmt-friendly error handling
2022-04-30 11:41:17 +03:00
Joonas Javanainen
07ad52162b
Add PLL config support for F2
2022-04-29 18:21:40 +03:00
Joonas Javanainen
0cfe1dc9df
Move HSE config out of main clock mux
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This makes the configuration more flexible and closer to the underlying
configuration register structure. For example, we could use HSI for the
system clock, but use HSE to output a clock with MCO.
2022-04-29 17:51:18 +03:00
Joonas Javanainen
a608d0deaf
Add minimal STM32F2 RCC
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No support for PLL or other clocks than SYSCLK/AHB/APB1/APB2
2022-03-27 18:40:49 +03:00
