Fix typo in derivation of PLLP divisor

2023-04-12 02:07:31 +02:00 · 2023-04-12 02:07:31 +02:00 · f3699e67b9
commit f3699e67b9
parent 201a038134
1 changed files with 1 additions and 1 deletions
--- a/embassy-stm32/src/rcc/f2.rs
+++ b/embassy-stm32/src/rcc/f2.rs
@ -148,7 +148,7 @@ impl Into<Pllp> for PLLMainDiv {
        match self {
            PLLMainDiv::Div2 => Pllp::DIV2,
            PLLMainDiv::Div4 => Pllp::DIV4,
-            PLLMainDiv::Div6 => Pllp::DIV8,
+            PLLMainDiv::Div6 => Pllp::DIV6,
            PLLMainDiv::Div8 => Pllp::DIV8,
        }
    }