WindowWatchdog configures a timer channel to capture both edges of an
input and compare the time between edges to a duration range. In other
words, it expects a ~50% duty cycle square wave on its input.
One possible use for this is to monitor whether another device is
functional.
If VALID_THRESHOLD (currently 2) edge intervals are within range, ok()
returns true, otherwise, if an edge is outside of the valid range ok()
returns false.
state_change() runs the calling task whenever the ok() state changes.
1255: common: allow atomic ringbuf to fill up to N instead of just N-1. r=Dirbaio a=Dirbaio
Extracted out of #1208. Since I don't think that'll end up using the ringbuf in the end, I've separated it.
This allows the ringbuf to be filled up to `N` instead of just `N-1`, using some fun tricks on the indices.
The advantage is better performance: Before, the first write would fill N-1 bytes, The second would write just the 1 byte left before wrapping, then N-2. Then 2, then N-3, and so on. This would result in more smaller chunks, so worse perf. This problem is gone now.
bors r+
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
This allows the ringbuf to be filled up to `N` instead of just `N-1`, using some fun tricks on the indices.
The advantage is better performance: Before, the first write would fill N-1 bytes, The second would write just the 1 byte left before wrapping, then N-2. Then 2, then N-3, and so on. This would result in more smaller chunks, so worse perf. This problem is gone now.
1247: `PacketQueue::init()` r=davidedellagiustina a=davidedellagiustina
`PacketQueue` is pretty big, so I added a method to initialize it without requiring an allocation on the stack (which could in fact overflow). Before this PR, the only solution would be to declare a `PacketQueue` instance as a `static mut`, while now one could for example have a `Box<MaybeUninit<PacketQueue<...>>>` and then use `init()` on it.
Ideally, the same work would need to be done for all those structures that own big arrays which could overflow the stack.
Co-authored-by: Davide Della Giustina <davide@dellagiustina.com>
1248: embassy-time: add async tick() method to Ticker r=Dirbaio a=kbleeke
Small QOL change so you don't have to add a direct dependency on futures-util to use the Ticker
Co-authored-by: kbleeke <pluth@0t.re>
1238: embassy-net: DNS resolver detects when name is just an IP address r=lulf a=kbleeke
fixes#1237
I am not sure, if this is the right place to put this code. Alternatively, It could be in dns::DnsSocket or reqwless (and all other libraries that need to maybe resolve hostnames).
Are there other DNS query-types where it would make sense to try to parse an IP address?
Co-authored-by: kbleeke <pluth@0t.re>
1236: Add `#[must_use]` to all futures r=Dirbaio a=GrantM11235
I think that's all of them, I just grep'd for `impl.* Future for`
Co-authored-by: Grant Miller <GrantM11235@gmail.com>
1231: embassy-time: Implement conversions to/from core::time::Duration for embassy-time::Duration r=Dirbaio a=kbleeke
I chose microseconds for the conversion as the lowest resolution that embassy provides. A new Error-type did not seem that useful but I can add one, if necessary.
Co-authored-by: kbleeke <pluth@0t.re>
1228: stm32/sdmmc: Implement proper clock configuration r=chemicstry a=chemicstry
This implements proper clock configuration for sdmmc based on chip family, because `RccPeripheral::frequency()` is almost always incorrect. This can't be fixed in PAC, because sdmmc uses two clock domains, one for memory bus and one for sd card. `RccPeripheral::frequency()` usually returns the memory bus clock, but SDIO clock calculations need sd card domain clock. Moreover, chips have multiple clock source selection bits, which makes this even more complicated. I'm not sure if it's worth implementing all this logic in `RccPeripheral::frequency()` instead of cfg's in sdmmc.
Some chips (Lx, U5, H7) require RCC updates to expose required clocks. I didn't want to mash everything in a single PR so left a TODO comment. I also left a `T::frequency()` fallback, which seemed to work in H7 case even though the clock is most certainly incorrect.
In addition, added support for clock divider bypass for sdmmc_v1, which allows reaching a maximum clock of 48 MHz. The peripheral theoretically supports up to 50 MHz, but for that ST recommends setting pll48 frequency to 50 MHz 🤔
Co-authored-by: chemicstry <chemicstry@gmail.com>
1227: stm32/dma: fix spurious transfer complete interrupts r=Dirbaio a=pattop
DMA interrupts must be acknowledged by writing to the DMA_{L,H}IFCR
register.
Writing to the CR register is unnecessary as the channel (EN bit) is
disabled by hardware on completion of the transfer.
Co-authored-by: Patrick Oppenlander <patrick.oppenlander@gmail.com>
DMA interrupts must be acknowledged by writing to the DMA_{L,H}IFCR
register.
Writing to the CR register is unnecessary as the channel (EN bit) is
disabled by hardware on completion of the transfer.
1225: nrf: rename UARTETWISPIn -> SERIALn r=Dirbaio a=Dirbaio
The UARTETWISPIn naming is quite horrible. With the nRF53, Nordic realized this and renamed the interrupts to SERIALn. Let's copy that for our peripheral names, in nrf53 and nrf91.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
1226: embassy-net: Implement flush for TcpSocket r=Dirbaio a=kbleeke
Implements flush for TcpSocket by checking the send queue.
Flushing is implemented by checking if smoltcp's send_queue/tx_buffer is empty. The flush is completed when all outstanding octets are acknowledged. Smoltcp wakes the send waker [here](https://docs.rs/smoltcp/latest/src/smoltcp/socket/tcp.rs.html#1712) when ACKs are processed and data is removed from the send buffer. So we can re-check in our flush implementation, if the buffer is now empty.
fixes#1223
Co-authored-by: kbleeke <pluth@0t.re>
The UARTETWISPIn naming is quite horrible. With the nRF53, Nordic realized this
and renamed the interrupts to SERIALn. Let's copy that for our peripheral names, in nrf53 and nrf91.
1170: nrf: add support for UICR configuration. r=Dirbaio a=Dirbaio
- APPROTECT enable/disable. Notably this fixes issues with nrf52-rev3 and nrf53 from locking itself at reset.
- Use NFC pins as GPIO.
- Use RESET pin as GPIO.
NFC and RESET pins singletons are made available only when usable as GPIO, for compile-time checking.
TODO: test
- [x] nrf52 rev1
- [x] nrf52 rev3
- [x] nrf53
- [x] nrf91
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
If the user requests some configuration, but UICR is already programmed
to something else, detect this and warn the user.
We don't do it for the debug port settings, because if they are wrong
then the user will simply not be able to read debug logs.
- APPROTECT enable/disable. Notably this fixes issues with nrf52-rev3 and nrf53 from locking itself at reset.
- Use NFC pins as GPIO.
- Use RESET pin as GPIO.
NFC and RESET pins singletons are made available only when usable as GPIO,
for compile-time checking.
1221: examples/stm32wb: do not reserve words at start of RAM. r=Dirbaio a=Dirbaio
They're used to communicate from the app to ST's OTA bootloader. See AN5247.
This bootloader is optional, must be flashed by the user, and requires changing the FLASH start address as well, so the current memory regions still require modifications to use it. Therefore there's no point in reserving these words.
Thanks `@adamgreig` for investigating the purpose.
bors r+
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
They're used to communicate from the app to ST's OTA bootloader. See AN5247.
This bootloader is optional, must be flashed by the user, and requires changing the FLASH start address as well, so the current memory regions still require modifications to use it. Therefore there's no point in reserving these words.
Thanks @adamgreig for investigating the purpose.
1218: Lora: sx126x: Change timing window to match values found experimentally. r=Dirbaio a=CBJamo
As mentioned in #1188.
1219: stm32/sdmmc: Fix SDIOv1 writes r=Dirbaio a=chemicstry
This fixes writes on sdmmc v1 (SDIO). I'm pretty sure I tested writes in #669, but maybe I was just lucky or I just forgot.
There were two problems:
- Writes require DMA FIFO mode, otherwise SDIO FIFO is under/overrun depending on sdio/pclk2 clock ratio.
- Hardware flow control is broken for sdmmc v1 (I checked F1 and F4 erratas). This causes clock glitches above 12 MHz and results in write CRC errors.
Co-authored-by: Caleb Jamison <caleb@cbjamo.com>
Co-authored-by: chemicstry <chemicstry@gmail.com>
1217: Fix a typo in "PioPeripheral" r=Dirbaio a=SekoiaTree
Renames "PioPeripherial" to "PioPeripheral" (without the second i).
Co-authored-by: sekoia <sequoia.1009@gmail.com>
