max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
2,693 Commits 67 Branches 32 Tags 16 MiB
5044361ddd
Commit Graph

139 Commits

Author SHA1 Message Date
Ulf Lilleengen
383beb37b3 Rename from wl55 to wl5x and enable debug wfe 2021-06-16 16:07:21 +02:00
Ulf Lilleengen
b6a8703698 Add support for generating PAC for dual cores 
* Chips that have multiple cores will be exposed as chipname_corename,
  i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
  and pick the first and only core from the list
* Add support for stm32wl55 chip family
 2021-06-16 15:12:07 +02:00
Ulf Lilleengen
8ae4f47d3d Fix compile 2021-06-15 16:44:00 +02:00
Ulf Lilleengen
49fad2de8a Use correct frequencies for timers 2021-06-15 16:07:23 +02:00
Ulf Lilleengen
4b406dd107 Remove default rcc impl 2021-06-14 20:24:51 +02:00
Ulf Lilleengen
5e1b0a5398 Add wb55 clocks 2021-06-14 11:41:02 +02:00
Ulf Lilleengen
ee9f67fa01 Add common types 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a2da2a6db2 Remove unused l0 code 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
95532726b2 Add minimal RCC impls for L4 and F4 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a13e07625f Add ... c1? 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
0b52731897 Add clocks for h7 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
2c63393c9e Add Clock type per RCC family 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
952f525af5 Provide a way for a peripheral to query its clock frequency 
Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
1bb7123156 Add examples for STM32L0 2021-06-09 23:09:48 +02:00
Ulf Lilleengen
ed29d82071 Use critical_section 2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ee3b82b743 Auto generate SPI v2 clock enable 
Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral.

Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.
 2021-06-08 17:20:29 +02:00
Ulf Lilleengen
a63388874a Update after name fix 2021-06-07 14:06:54 +02:00
Ulf Lilleengen
1cd2c55b7c Fix stm32l0 build 2021-06-07 12:19:09 +02:00
Ulf Lilleengen
f5e2fb9a5a Update to new api 2021-06-07 12:03:31 +02:00
Dario Nieuwenhuis
e7dc5c0939 fmt: make all macros macro_rules so scoping is consistent. 2021-06-07 00:16:39 +02:00
Ulf Lilleengen
c3a521066d Add utility to enable debug 2021-06-02 15:23:10 +02:00
Ulf Lilleengen
4863d5e01e Add a way to enable more features of the STM32L0 RCC 
Add ability to enable the hsi48 clock. Code modified from the STM32L0XX
hal
 2021-06-02 14:28:33 +02:00
Dario Nieuwenhuis
d24b67512f More fixes 2021-05-31 03:21:44 +02:00
Dario Nieuwenhuis
d8e4421fc6 Add stm32-metapac crate, with codegen in rust 2021-05-31 02:40:58 +02:00
Ulf Lilleengen
3669eba561 Use builder 2021-05-27 10:01:40 +02:00
Ulf Lilleengen
a41a812345 Move clocks to rcc mod 2021-05-27 09:50:11 +02:00
Ulf Lilleengen
6eaf224fec No more systemclock 2021-05-26 21:46:57 +02:00
Ulf Lilleengen
bfa999a2e0 Assume tim2 in macro and remove clock setup in chip specific rcc init 
Add temporary start_tim2() fn to Clock to assist macro in starting
embassy clock
 2021-05-26 21:42:07 +02:00
Ulf Lilleengen
f960f5b105 Rework 2021-05-26 13:55:25 +02:00
Ulf Lilleengen
9743c59ad4 Simplify 2021-05-26 13:29:11 +02:00
Ulf Lilleengen
ea67940743 Refactor 2021-05-26 13:08:14 +02:00
Ulf Lilleengen
c501b162fc Enable clock by default for stm32l0 
Modify init function to return a Clock instance defined by a per-chip
SystemClock type and use this in macro setup

A proof of concept implementation for STM32 L0 chips.

This allows using embassy::main macros for STM32 devices that have the
clock setup logic.
 2021-05-26 12:33:07 +02:00
Ulf Lilleengen
ef254647f7 Add stm32l0 2021-05-25 13:32:10 +02:00
Ulf Lilleengen
1c10e746b6 Re-adds embassy macros for stm32 
* Hook RCC config into chip config and use chip-specific RCC init
  function
* RTC/clock setup is ignored for now
 2021-05-25 13:30:42 +02:00
Thales Fragoso
2605dabca3 H7 RCC: Fix off by one error 2021-05-21 20:20:17 -03:00
Thales Fragoso
1689ab2f8b H7 RCC: Setup DBGMCU to enable debugging during wfi/wfe 2021-05-21 20:20:17 -03:00
Thales Fragoso
7f65f491e5 Finish initial H7 RCC support 2021-05-21 20:16:25 -03:00
Thales Fragoso
2ea12d96ee More work on H7 RCC 2021-05-21 20:13:39 -03:00
Thales Fragoso
054f0d51dc H7: Add initial PLL configuration 2021-05-21 20:13:37 -03:00