Sebastian Goll
f3699e67b9
Fix typo in derivation of PLLP divisor
2023-04-12 02:07:31 +02:00
chemicstry
3bf1e1d4aa
Fix f2, wl compilation
2022-07-10 21:46:14 +03:00
chemicstry
1fd5022e72
Refactor IWDG to use LSI frequency from RCC
2022-07-10 20:59:36 +03:00
Dario Nieuwenhuis
a8703b7598
Run rustfmt.
2022-06-12 22:22:31 +02:00
Joonas Javanainen
e88559c5ca
Use defmt-friendly error handling
2022-04-30 11:41:17 +03:00
Joonas Javanainen
07ad52162b
Add PLL config support for F2
2022-04-29 18:21:40 +03:00
Joonas Javanainen
0cfe1dc9df
Move HSE config out of main clock mux
...
This makes the configuration more flexible and closer to the underlying
configuration register structure. For example, we could use HSI for the
system clock, but use HSE to output a clock with MCO.
2022-04-29 17:51:18 +03:00
Joonas Javanainen
a608d0deaf
Add minimal STM32F2 RCC
...
No support for PLL or other clocks than SYSCLK/AHB/APB1/APB2
2022-03-27 18:40:49 +03:00
