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1279 Commits

Author SHA1 Message Date
Mathias
d372df7ddb L4: Switch to MSI to prevent problems with PLL configuration, and enable power to AHB bus clock to allow RTC to run 2023-07-01 12:16:23 +02:00
Dario Nieuwenhuis
6eb46c419c Merge pull request #1565 from JuliDi/main 
Implement DMA for DAC on STM32
 2023-06-29 08:54:28 +00:00
Julian
96f1525ffe Revert changes to dma.rs 2023-06-29 09:20:25 +02:00
Dario Nieuwenhuis
e892014b65 Update stm32-metapac, includes chiptool changes to use real Rust enums now. 2023-06-29 02:01:33 +02:00
Kevin Lannen
5666c56903 STM32G4: Add CRS support to RCC 
Create working CRS USB Example
 2023-06-28 16:53:16 -06:00
JuliDi
daedfbbd87 add dma is_running change doc 2023-06-28 15:39:36 +02:00
JuliDi
91c31d5e43 Update DAC examples, add DAC + DMA example 2023-06-28 11:58:25 +02:00
Dario Nieuwenhuis
ed493be869 stm32: update metapac, includes fix for OTG with 9 endpoints (H7) 2023-06-27 23:58:32 +02:00
JuliDi
9c81d63155 fix warnings 2023-06-27 22:33:17 +02:00
JuliDi
60c54107ce fix sdmmc bdma transferconfig fields 2023-06-27 21:58:56 +02:00
JuliDi
56dd22f0ac feature-gate set_channel_mode, undo dma.rs changes 2023-06-27 21:23:47 +02:00
JuliDi
afec1b439b feature-gate dma write, make trigger not return a result 2023-06-27 18:17:51 +02:00
Dario Nieuwenhuis
219ef5b37a stm32/otg: add VBUS detection. 
Fixes #1442.
 2023-06-27 12:52:37 +02:00
Dario Nieuwenhuis
5e6e18b310 stm32/usb: add TODO: implement VBUS detection. 2023-06-27 04:29:01 +02:00
Dario Nieuwenhuis
80407aa930 stm32/otg: set tx fifo num in IN endpoints on configure. 2023-06-27 02:12:33 +02:00
Dario Nieuwenhuis
a575e40a35 stm32/otg: clear NAK bit on endpoint enable. 2023-06-27 02:12:06 +02:00
Dario Nieuwenhuis
28fb492c40 stm32/otg: flush fifos on reconfigure and on ep disable. 2023-06-27 00:42:24 +02:00
JuliDi
e7bc84dda8 fix issues when DAC2 present, add additional options to DMA (NOT YET WORKING with STM32H7A3ZI) 2023-06-26 09:42:25 +02:00
JuliDi
8cafaa1f3c add docs, cleanup 2023-06-25 11:54:25 +02:00
JuliDi
df944edeef fix minor issues with splitting channels etc 2023-06-25 10:53:35 +02:00
JuliDi
388d3e273d first attempt at fixing the 2nd channel problem 2023-06-24 13:10:59 +02:00
JuliDi
915f79c974 allow independent use of ch1 and ch2 on dac 2023-06-23 12:14:40 +02:00
JuliDi
ea04a0277b change dma complete transfer IR default to true 2023-06-23 12:14:26 +02:00
schphil
71afa40a69 Merge branch 'embassy-rs:main' into can-split 2023-06-23 10:19:30 +02:00
Philipp Scheff
89fbb02979 add as_mut 2023-06-22 17:49:33 +02:00
Philipp Scheff
5ecf9ec7bc split can 2023-06-22 17:17:51 +02:00
JuliDi
78736328a0 update docs and update to new dma interface 2023-06-22 10:44:08 +02:00
JuliDi
8d0095c618 add option to enable/disable complete transfer interrupt 2023-06-22 10:43:45 +02:00
xoviat
1f2be2dac5 Merge pull request #1569 from xoviat/tl-mbox-2 
wpan: misc. cleanup and add mac
 2023-06-21 21:50:12 +00:00
JuliDi
fdb3c3d6ff Merge remote-tracking branch 'upstream/main' 2023-06-21 11:52:53 +02:00
Dario Nieuwenhuis
2e625138ff Merge pull request #1501 from xoviat/can 
async can
 2023-06-20 22:57:31 +00:00
xoviat
ca21027eea Merge pull request #3 from schphil/can 
fix extended can id
 2023-06-20 17:45:28 -05:00
xoviat
0a551eb7c6 stm32/can: fix time 2023-06-20 17:39:00 -05:00
xoviat
0d67ef795e Merge branch 'main' of https://github.com/embassy-rs/embassy into tl-mbox-2 2023-06-19 21:18:46 -05:00
xoviat
0998221478 stm32/can: update interrupts 2023-06-19 16:05:59 -05:00
Dario Nieuwenhuis
428a4ba3f9 stm32/gpdma: clear all interrupts after reset. 
Reset doesn't clear them, this causes subsequent transfers to instantly
complete because the TC flag was set from before.
 2023-06-19 23:03:31 +02:00
xoviat
aaad906815 Merge branch 'main' of https://github.com/embassy-rs/embassy into can 2023-06-19 15:52:33 -05:00
JuliDi
56ab6d9f14 remove write_X variants 2023-06-19 13:54:22 +02:00
JuliDi
88052480b1 fix typo, minor cleanup 2023-06-19 13:50:17 +02:00
JuliDi
218b102b28 remove Alignment and make Value and Value array look the same 2023-06-19 13:46:17 +02:00
JuliDi
fe7b72948a add ValueArray type and respective write functions 2023-06-19 13:42:25 +02:00
Dario Nieuwenhuis
3c70f799a2 Merge pull request #1572 from whitequark/bdma-blocking_wait-stop 
BDMA: request stop after busy loop in blocking_wait()
 2023-06-19 09:55:07 +00:00
JuliDi
e0747e937f remove unsafe for circular dma reg access 2023-06-19 11:15:09 +02:00
JuliDi
320e2cf35b Merge branch 'main' of github.com:embassy-rs/embassy 2023-06-19 11:14:48 +02:00
Catherine
bbc81146ec BDMA: request stop after busy loop in blocking_wait(). 
Otherwise the channel cannot be used again, since CR.EN remains set
and the DMA channel registers are read-only while it is set.
 2023-06-19 09:06:41 +00:00
Dario Nieuwenhuis
558918651e stm32: update stm32-metapac. 2023-06-19 03:22:12 +02:00
JuliDi
f8ee33abb9 add half transfer interrupt and circular dma 2023-06-18 18:51:36 +02:00
xoviat
748d1ea89d stm32/ipcc: minor cleanup 2023-06-18 10:10:05 -05:00
Dario Nieuwenhuis
adaed307b4 Merge pull request #1561 from petegibson/stm32-buffereduart-int-flags-fix 
Ensure idle & ove flags are cleared in BufferedUart ISR on STM32
 2023-06-18 10:40:22 +00:00
Peter Gibson
b4f96e192c Don't read data register to clear flags on usart v3 ^& v4 2023-06-18 08:45:58 +10:00