pbert
ecdd7c0e2f
enable clock first
2023-10-12 11:04:44 +02:00
pbert
f65a96c541
STM32: combine RccPeripherals reset() and enable() to reset_and_enable()
2023-10-12 11:04:19 +02:00
xoviat
57ccc1051a
stm32: add initial rcc mux for h5
2023-10-11 20:59:47 -05:00
Dario Nieuwenhuis
70a91945fc
stm32: remove atomic-polyfill.
2023-10-12 02:07:26 +02:00
Dario Nieuwenhuis
4a43cd3982
stm32/rcc: LSE xtal is 32768hz, not 32000hz.
...
Fixes #2043
2023-10-11 13:39:04 +02:00
Dario Nieuwenhuis
b91d1eaca0
stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.
2023-10-11 04:12:38 +02:00
Dario Nieuwenhuis
21915a9a3f
stm32/rcc: unify L0 and L1.
2023-10-11 01:22:27 +02:00
Dario Nieuwenhuis
d0d0ceec6a
stm32/rcc: rename HSE32 to HSE
2023-10-11 01:06:44 +02:00
Dario Nieuwenhuis
0cfa8d1bb5
stm32/rcc: use more PLL etc enums from PAC.
2023-10-11 00:12:33 +02:00
Dario Nieuwenhuis
6186fe0807
stm32/rcc: use PLL enums from PAC.
2023-10-09 02:48:22 +02:00
Dario Nieuwenhuis
3bf8e4de5f
Merge pull request #2015 from willglynn/stm32u5_faster_clocks
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stm32: u5: implement >55 MHz clock speeds
2023-10-06 23:38:15 +00:00
Dario Nieuwenhuis
3a8e0d4a27
stm32: implement MCO for all chips.
2023-10-07 01:15:24 +02:00
shakencodes
68c4820dde
Add MCO support for stm32wl family
2023-10-06 14:37:36 -07:00
Matt Ickstadt
f01609036f
h7: implement RTC and LSE clock configuration
2023-10-06 13:28:30 -05:00
Will Glynn
38e7709a24
stm32: u5: implement >55 MHz clock speeds
...
This commit allows STM32U5 devices to operate at 160 MHz.
On STM32U5, MSIS can run at 48 MHz and HSE can reach 50 MHz. Faster
clocks require using PLL1's R output, though PLL1 can serve other
functions besides using the R output for the system clock. This commit
extracts a public `PllConfig` struct, primarily to place associated
constructors on that type, but also with an eye towards enabling the P
and Q outputs in a later commit.
STM32U5 PLLs have various frequency requirements on each stage: after
the `m` prescaler, after the `n` multiplier, and after the `r` divider.
This commit implements the associated checks as assertions.
This commit fixes clock calculation and PLL register configuration
errors in PLL initialization.
STM32U5 has a PWR peripheral which can be configured to push Vcore into
different voltage ranges. System clocks exceeding 55 MHz require range
2, and system clocks exceeding 110 MHz require range 1. This commit
adds `voltage_range` to `Config` and configures PWR as directed.
The voltage range implies different performance limits on various clock
signals, including inside a PLL. This commit implements voltage range
<-> frequency range checks as assertions, and extracts the
otherwise-repeated MSIS, HSI16, and HSE initialization into private
methods on `Config`.
STM32U5 frequencies above 55 MHz require using the PWR EPOD booster.
The EPOD booster requires configuring a second `m` term for PLL1,
`mboost`, such that it falls in a particular range. (Recall that >50
MHz cannot be reached without PLL1, so there is no scenario where EPOD
is needed but PLL1 is not.) This commit configures and enables the EPOD
booster automatically as required.
2023-10-05 22:13:27 -05:00
xoviat
bb8a1b7f1f
wpan: re-enable HIL tests
2023-10-03 15:53:22 -05:00
xoviat
bc203ebe4b
Merge branch 'main' of github.com:embassy-rs/embassy into fix-stop
2023-10-02 18:30:41 -05:00
xoviat
e042b3056d
stm32: fix stop
2023-10-02 18:11:03 -05:00
Dario Nieuwenhuis
b856d760f4
stm32/rcc: reset backup domain before enabling LSE.
2023-10-02 22:12:50 +02:00
Dario Nieuwenhuis
2af97e7595
rcc/f4: fix build on stm32f446
...
fixes #1989
2023-10-01 23:01:58 +02:00
Tyler Gilbert
1be5f193c3
#Issue 1974 more whitespace fixes
2023-09-29 21:53:01 -05:00
Tyler Gilbert
4a632e08b7
#Issue 1974 fix extra whitespace
2023-09-29 21:46:19 -05:00
Tyler Gilbert
6cdee93934
#Issue 1974 fix more warnings treated as errors
2023-09-29 21:27:15 -05:00
Tyler Gilbert
5c8c1b2146
#Issue 1974 fix warnings
2023-09-29 21:16:20 -05:00
Tyler
2f9b59c5cf
Merge branch 'main' into issue-1974-add-sai-driver
2023-09-29 20:02:24 -06:00
Tyler Gilbert
ce91fb2bfc
Issue #1974 add SAI driver
2023-09-29 20:57:59 -05:00
Mateusz Butkiewicz
e1951f3ddf
feat(stm32f7): restore rtc configuration for stm32f7 series
2023-09-27 16:08:05 +02:00
Dario Nieuwenhuis
a57e48459e
stm32/rcc: remove bad limits on l5.
2023-09-26 05:15:09 +02:00
Dario Nieuwenhuis
c604d8a8f1
stm32/rcc: add voltage_scale, flash waitstates.
2023-09-26 05:15:09 +02:00
xoviat
04b09a2acb
stm32/rtc: use rccperi enable
2023-09-25 16:26:29 -05:00
xoviat
2543bcafaf
Merge pull request #1945 from xoviat/bd-2
...
stm32: fix bd lsi
2023-09-24 23:41:04 +00:00
xoviat
9f2fc04caa
stm32: fix bd lsi
2023-09-24 18:37:09 -05:00
Dario Nieuwenhuis
e03239e88d
stm32: centralize enabling pwr, syscfg, flash.
2023-09-25 01:07:55 +02:00
Dario Nieuwenhuis
83b4c01273
stm32/rcc: unify h5 and h7.
2023-09-21 23:47:56 +02:00
Christian Enderle
ad64d7b20b
fix low-power: APB1 needed for LSE
2023-09-21 17:17:58 +02:00
Dario Nieuwenhuis
00b9f9acef
stm32/h7: fix bad PWR reg versions.
2023-09-21 00:23:56 +02:00
Sebastian Goll
561696dfad
Fix typo in F2 RCC voltage ranges
2023-09-19 10:20:25 +02:00
Dario Nieuwenhuis
4bfbcd6c72
stm32: use PAC enums for VOS.
2023-09-18 03:15:15 +02:00
xoviat
a6ef314be1
stm32: update configure_ls as agreed
2023-09-17 18:41:45 -05:00
Dario Nieuwenhuis
bbe1d96045
stm32/rcc: use AHBPrescaler div impls in stm32wba
2023-09-17 02:30:50 +02:00
xoviat
de2773afdd
stm32/rcc: convert bus prescalers to pac enums
2023-09-16 17:41:11 -05:00
xoviat
ad0a306ea5
stm32: fix wpan_ble test
2023-09-16 10:19:09 -05:00
Dario Nieuwenhuis
8315cf064e
stm32: add stm32wba support.
2023-09-16 04:04:45 +02:00
xoviat
c28a6bdd0b
stm32: generate adc_common
2023-09-15 17:35:53 -05:00
xoviat
9fb14379c3
stm32: add lp to l0
2023-09-14 18:53:27 -05:00
xoviat
08415e001e
stm32/f3: add high res for hrtim and misc.
2023-09-10 13:33:17 -05:00
xoviat
11a78fb1e4
rcc: more cleanup
2023-09-08 18:20:58 -05:00
xoviat
4550452f43
rustfmt
2023-09-06 17:53:02 -05:00
xoviat
08410432b5
stm32: fix rcc merge
2023-09-06 17:51:40 -05:00
xoviat
3cf3caa3ab
Merge branch 'main' into rcc-bd
2023-09-06 17:49:29 -05:00
xoviat
c21ad04c2e
stm32: extract lse/lsi into bd mod
2023-09-06 17:48:12 -05:00
xoviat
d097c99719
stm32/rcc: add lsi and lse bd abstraction
2023-09-06 17:33:56 -05:00
Olle Sandberg
0d3ff34d80
adc: enable ADC and clock selection for STM32WLx
2023-09-06 06:57:30 +02:00
xoviat
a05afc5426
Merge pull request #1867 from xoviat/adc-g4
...
Adc g4
2023-09-05 23:31:03 +00:00
Scott Mabin
6770d8e8a6
Allow the RTC clock source to be configured with the new RTC mechanism
2023-09-06 00:04:09 +01:00
xoviat
7622d2eb61
stm32: fix merge issues
2023-09-05 17:10:15 -05:00
xoviat
7573160077
Merge branch 'main' of https://github.com/embassy-rs/embassy into adc-g4
2023-09-05 17:02:28 -05:00
xoviat
f502271940
stm32: add initial adc f3 impl
2023-09-05 16:46:57 -05:00
Daehyeok Mun
49ba9c3da2
initial support for STM32G4 ADC
2023-09-04 23:36:41 -07:00
xoviat
27dfced285
stm32: fix rcc wb
2023-08-29 19:51:21 -05:00
xoviat
989c98f316
stm32/rtc: autocompute prescalers
2023-08-29 19:41:03 -05:00
xoviat
6b8b145266
stm32: revert changes to rcc f4
2023-08-28 16:17:42 -05:00
xoviat
70a5221b2e
stm32/bd: consolidate enable_rtc
2023-08-28 15:34:08 -05:00
xoviat
e981cd4968
stm32: fix rtc wakeup timing and add dbg
2023-08-27 21:15:57 -05:00
xoviat
cbc92dce05
stm32/bd: fix errors
2023-08-27 15:18:34 -05:00
xoviat
531f51d0eb
rcc/bd: consolidate mod
2023-08-27 15:01:09 -05:00
xoviat
f28ab18d7b
stm32: fix l4 re-export
2023-08-27 09:50:02 -05:00
xoviat
3bf6081eb5
stm32: fix wl re-export
2023-08-27 09:41:31 -05:00
xoviat
fb942e6675
stm32: re-export rtcclocksource
2023-08-27 09:25:14 -05:00
xoviat
10ea068027
stm32/bd: allow dead code
2023-08-27 09:12:04 -05:00
xoviat
4caa8497fc
stm32: extract backupdomain into mod
2023-08-27 09:07:34 -05:00
xoviat
48085939e7
stm32/rcc: rename common to bus
2023-08-27 08:35:13 -05:00
xoviat
cda4047310
stm32: flesh out lp executor
2023-08-24 19:29:11 -05:00
xoviat
83f224e140
stm32/lp: add refcount
2023-08-23 20:18:34 -05:00
xoviat
7bff2ebab3
Merge pull request #1766 from xoviat/rtc-w
...
stm32/rtc: add start/stop wakeup
2023-08-22 21:50:53 +00:00
xoviat
5bfddfc9b6
stm32/rcc: add rtc to f410
2023-08-21 18:10:10 -05:00
xoviat
8c12453544
stm32/rcc: set rtc clock on f4
2023-08-21 17:50:18 -05:00
Dario Nieuwenhuis
cc400aa178
stm32: fix f37x build.
...
originally broke in https://github.com/embassy-rs/embassy/pull/1762
2023-08-19 01:15:32 +02:00
Dominik Sliwa
5bc0175be9
configure flash latency after axi clock and handle different flash in STM32H7A/B devices
2023-08-18 23:44:56 +02:00
Dario Nieuwenhuis
94fa95c699
Merge pull request #1793 from ARizzo35/stm32l4-rtc-pwren
...
stm32l4: set pwren in rcc regardless of clock source
2023-08-18 10:19:54 +00:00
Adam Rizkalla
62e66cdda3
stm32l4: set pwren in rcc regardless of clock source
2023-08-17 19:16:03 -05:00
Olle Sandberg
c80c323634
stm32-wl: set RTC clock source on RCC init
2023-08-16 14:41:00 +02:00
Sebastian Goll
df6952648e
Make sure to check RCC settings for compatibility before applying
2023-08-16 14:11:09 +02:00
xoviat
32fdd4c787
tests/stm32: fix rtc test
2023-08-08 20:33:24 -05:00
xoviat
6a73ab1afa
stm32/l4: set rtc clock source in rcc
2023-08-08 19:58:03 -05:00
xoviat
6fc5c608f8
stm32/rtc: remove generics and segregate clock sel
2023-08-08 19:47:01 -05:00
xoviat
28618d12a1
stm32/rtc: restructure
2023-08-06 11:58:28 -05:00
xoviat
66c1712118
stm32/rtc: enable in rcc mod
2023-08-06 11:11:53 -05:00
Bartek
5fcebd28f4
Fix unlocking the backup domain when enabling LSE
...
Set PWREN bit to enable the power interface clock before enabling access to the backup domain.
2023-08-01 13:46:34 +09:30
Dario Nieuwenhuis
3aef5999d5
Merge pull request #1716 from xoviat/rcc-p
...
stm32/rcc: extract and combine ahb/apb prescalers
2023-07-30 20:43:54 +00:00
xoviat
a8a491212b
stm32/rcc: cleanup merge
2023-07-30 10:18:54 -05:00
xoviat
2f18770e27
stm32/rcc: extract and combine ahb/apb prescalers
2023-07-30 09:52:30 -05:00
Scott Mabin
e0ce7fcde7
stm32f2 pll overflow with crystal
...
With a large enough HSE input frequency, the vco clock calculation will
overflow a u32. Therefore, in this specific case we have to use the
inner value and cast to u64 to ensure the mul isn't clipped before
applying the divider.
2023-07-30 01:00:53 +01:00
xoviat
c7c701b3e3
Merge branch 'main' of https://github.com/embassy-rs/embassy into hrtim
2023-07-28 17:18:22 -05:00
Dario Nieuwenhuis
036e6ae30c
Rename embassy-hal-common to embassy-hal-internal, document it's for internal use only. ( #1700 )
2023-07-28 13:23:22 +02:00
xoviat
270d1d59a0
stm32/rcc: use wpan default only for wpan
2023-07-24 18:25:15 -05:00
xoviat
1425dda0a7
stm32/rcc: fix minor issues
2023-07-24 17:19:45 -05:00
xoviat
bd60f003e0
stm32/rcc: move rcc logic from ipcc
2023-07-23 17:01:34 -05:00
xoviat
d42dff45de
Merge branch 'main' of https://github.com/embassy-rs/embassy into hrtim
2023-07-22 14:49:31 -05:00
Phil Markgraf
3bae533066
Enable RTC on STM32WL chips ( #1645 )
...
* Add clippy allow to not report if same then branch
* Support enabling RTC clock on STM32WL
* Add clippy allow to not report if same then branch
* Support enabling RTC clock on STM32WL
* Add rtc example for stm32wl
* Address code review feedback
2023-07-15 13:40:23 +02:00
