Commit Graph

761 Commits

Author SHA1 Message Date
Henrik Alsér
880b71a1e8 impl SetConfig for stm32 i2c and SPI 2022-07-09 02:28:05 +02:00
Vincent Stakenburg
d1d07cd9e3 fix case when chip has multiple iwdg 2022-06-28 13:22:43 +02:00
Vincent Stakenburg
f2ad9c2d9d rebase and fix unborrow 2022-06-28 12:51:08 +02:00
Vincent Stakenburg
74bbf5aa02 address review 2022-06-28 12:46:17 +02:00
Vincent Stakenburg
5cf3fbece4 initial independent watchdog implementation 2022-06-28 12:46:17 +02:00
Dario Nieuwenhuis
42bc510eff Remove STM32L485 "ghost chips" 2022-06-27 02:47:15 +02:00
Dario Nieuwenhuis
a855889f70 Update stm32-data 2022-06-27 02:10:01 +02:00
Dario Nieuwenhuis
948bb93dc2 docs: Add $COMMIT to git srclinks. 2022-06-26 23:55:38 +02:00
Dario Nieuwenhuis
397722c328 stm32: fix f100 build. 2022-06-26 23:52:38 +02:00
bors[bot]
84628d36cf
Merge #826
826: Bump bxcan version r=chemicstry a=chemicstry



Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-06-22 23:48:45 +00:00
chemicstry
3cdd8c1aeb Fix PWM for advanced timers 2022-06-23 02:27:39 +03:00
chemicstry
31177d994f Fix example 2022-06-23 02:01:23 +03:00
chemicstry
2d2f9e39b9 Bump bxcan version 2022-06-23 01:42:21 +03:00
Dario Nieuwenhuis
1f746e0939 Remove the authors field from Cargo.tomls
It currently contains whoever was first to write some code for the crate,
even if many more people have contributed to it later.

The field is "sort of" deprecated, it was made optional recently:
https://rust-lang.github.io/rfcs/3052-optional-authors-field.html

Due the the reasons listed there I believe removing it is better than
setting it to generic fluff like "The Embassy contributors".
2022-06-18 02:16:40 +02:00
Dario Nieuwenhuis
88e36a70bd
Update to 2021 edition. (#820) 2022-06-18 02:15:48 +02:00
Daniel Bevenius
9031b8f80a Fix doc comments for BpskPacketParams 2022-06-16 07:34:59 +02:00
Daniel Bevenius
d0edd171f8 Fix typo in LoRaPacketParams::new doc 2022-06-16 06:22:03 +02:00
Ulf Lilleengen
faa59efbf6 Cargo fmt 2022-06-15 09:01:22 +02:00
Ulf Lilleengen
3696226fe8 Sync subghz peripheral support with stm32wlxx-hal 2022-06-14 16:27:42 +02:00
Dario Nieuwenhuis
a8703b7598 Run rustfmt. 2022-06-12 22:22:31 +02:00
Dario Nieuwenhuis
5085100df2 Add embassy-cortex-m crate.
- Move Interrupt and InterruptExecutor from `embassy` to `embassy-cortex-m`.
- Move Unborrow from `embassy` to `embassy-hal-common` (nothing in `embassy` requires it anymore)
- Move PeripheralMutex from `embassy-hal-common` to `embassy-cortex-m`.
2022-06-12 21:45:38 +02:00
Dario Nieuwenhuis
db344c2bda
common/PeripheralMutex: remove unsafe API. (#802)
Following the project's decision that "leak unsafe" APIs are not marked as "unsafe",
update PeripheralMutex to accept non-'static state without unsafe.

Fixes #801
2022-06-09 21:28:13 +02:00
Ulf Lilleengen
7d64f5cda7 Use correct index and bank 2022-06-07 15:59:22 +02:00
Dario Nieuwenhuis
3e4bead321 stm32: add USB driver. 2022-06-07 03:29:00 +02:00
Dario Nieuwenhuis
0aa73f58e2 Update stm32-metapac. 2022-06-07 00:28:26 +02:00
chemicstry
b0ffd9a1cc Fix AF pullup configuration for GPIOv1 2022-06-06 17:12:52 +03:00
Will Glynn
34a8a64bf5 stm32: make tick rate configurable
The stm32 time drivers support arbitrary tick rates but the associated
Cargo features do not. Enabling any time driver presently enables
`embassy/time-tick-32768hz`; instead, enable only `embassy/time`.

This is a breaking change: users must now choose a tick rate. The
previous behavior is available by enabling the
`embassy/time-tick-32768hz` feature, but now users may also choose
`embassy/time-tick-1000hz` or `embassy/time-tick-1mhz` instead.
2022-05-30 20:13:25 -05:00
bors[bot]
70e4418df9
Merge #781 #785
781:  embassy-net v2 r=Dirbaio a=Dirbaio

- No more `dyn`
- It's no longer a global singleton, you can create muliple net stacks at once.
  - You can't tear them down though, the Device it still has to be `'static` due to restrictions with smoltcp's "fake GAT" in the Device trait. :(
- Removed `_embassy_rand` hack, random seed is passed on creation.



785: stm32: g0: add PLL clock source r=Dirbaio a=willglynn

STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at 16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach 64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q` to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main reason the user will configure the PLL, so `r` is mandatory and the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the MCO and MCO2 peripherals, so `q` is optional and the output is conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()` calls `PllConfig::init()` which initializes the PLL per [RM0454]. It disables the PLL, waits for it to stop, enables the source oscillator, configures the PLL, waits for it to lock, and then enables the appropriate outputs. `rcc::init()` then switches the clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This was likely a blocker for anyone using HSE >= 24 MHz, with or without the PLL.) Flash accesses are now automatically slowed down as needed before changing the clock source, and sped up as permitted after changing the clock source. The number of flash wait states also determines if flash prefetching will be profitable, so that is now handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Co-authored-by: Will Glynn <will@willglynn.com>
2022-05-31 00:25:21 +00:00
Dario Nieuwenhuis
6320e30adf Update embedded-hal-async to 0.1.0-alpha.1 2022-05-29 22:34:08 +02:00
Will Glynn
1c2b27dcad embassy-stm32: g0: add PLL clock source
STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at
16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach
64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks
its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q`
to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main
    reason the user will configure the PLL, so `r` is mandatory and
	the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S
    peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the
    MCO and MCO2 peripherals, so `q` is optional and the output is
	conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()`
calls `PllConfig::init()` which initializes the PLL per [RM0454]. It
disables the PLL, waits for it to stop, enables the source
oscillator, configures the PLL, waits for it to lock, and then
enables the appropriate outputs. `rcc::init()` then switches the
clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash
wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz
requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This
was likely a blocker for anyone using HSE >= 24 MHz, with or without
the PLL.) Flash accesses are now automatically slowed down as needed
before changing the clock source, and sped up as permitted after
changing the clock source. The number of flash wait states also
determines if flash prefetching will be profitable, so that is now
handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
2022-05-27 23:56:42 -05:00
chemicstry
1d951a54be Reimplement BufRead for BufferedUart 2022-05-26 14:02:55 +03:00
Dario Nieuwenhuis
a5aea995a8 WIP embassy-net v2 2022-05-25 19:56:22 +02:00
Dario Nieuwenhuis
d0fe9af458
Merge pull request #771 from embassy-rs/net-split
net: add split() to tcpsocket
2022-05-19 07:13:24 +02:00
Dario Nieuwenhuis
e3b8e35498 Make embassy-net nightly-only.
It's useless without async traits, so juggling the `nightly` feature
around is not worth the pain.
2022-05-19 06:15:01 +02:00
bors[bot]
7743b8e1ae
Merge #776
776: Automatically set ADC clock prescaler on v2 ADC to respect max frequency r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-05-19 04:00:23 +00:00
Dario Nieuwenhuis
47ceee47d5 Update embedded-io to 0.3 2022-05-19 00:36:18 +02:00
Matous Hybl
53f65d8b09 Automatically set ADC clock prescaler on v2 ADC to respect max frequency 2022-05-18 18:34:36 +02:00
Ralf
c90968bb70 stm32/rcc: Modify only relevant CFGR bits and keep the settings previously done.
PLL settings remained intact because these bits are not writable when PLL is enabled,
but prescaler settings were overwritten by selecting PLL as sysclk (CFGR.SW[1:0]).
2022-05-12 09:09:39 +02:00
Ralf
1a216958ac stm32/rcc: Set flash prefetch buffer and half cycle access according to AHB clock prescaler 2022-05-12 09:09:39 +02:00
Ralf
f4677469f9 stm32/usart: Data length is including parity. To get e.g. 8E1 you need to choose 9 data bits 2022-05-12 09:09:30 +02:00
Matous Hybl
01fb447e9d Allow maximal clock for F7 HCLK 2022-05-08 23:07:28 +02:00
bors[bot]
e9ab960ebf
Merge #760
760: stm32/gpio: Add support for `set_speed` for gpio v1 r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-05-08 19:53:31 +00:00
Grant Miller
acc1761637 Remove unnecessary cfg 2022-05-08 14:50:15 -05:00
Grant Miller
b230ac9c1a stm32/gpio: Add support for set_speed for gpio v1 2022-05-08 14:43:37 -05:00
Dario Nieuwenhuis
96d0eb9476 stm32: Fix stm32f107 build. 2022-05-08 21:37:37 +02:00
bors[bot]
a4bf190f2f
Merge #752
752: Replace embassy::io with embedded_io. r=Dirbaio a=Dirbaio

TODO:

- [x] Release embedded-io on crates.io
- [x] Remove git dep

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-05-06 23:54:07 +00:00
Dario Nieuwenhuis
931a137f8c Replace embassy::io with embedded_io. 2022-05-07 01:45:54 +02:00
Matous Hybl
118532278c Add H7 flash and bootloader support 2022-05-06 21:57:15 +02:00
Matous Hybl
6d56f772e1 Add F7 flash and bootloader support 2022-05-06 21:57:15 +02:00
Matous Hybl
f3700b4e42 Refactor flash handling to different modules for different families 2022-05-06 21:57:15 +02:00