652: Use new stm32-data registers and fix AHB clock calculation r=Dirbaio a=msamsonoff
This is the follow-on to my PR against stm32-data that added new register enums for the G0. I have updated the G0 RCC module to use those new enums.
I have also fixed an issue with the calculation of the AHB clock rate. 32 is not available as an AHB prescaler. The sequence jumps from 16 to 64. The original bit shifting math did not account for this gap. I have replaced it with a `match` instead.
653: Fixes for rustdoc building. r=Dirbaio a=Dirbaio
Co-authored-by: Matthew W. Samsonoff <matt.samsonoff@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
The original code for calculating the AHB clock did not account for the gap in
prescaler values (32 is not an available value.) The bit shifting and math has
been replaced by a `match`.
The source files are unreadable because they're not fmt'd, and
they take up a LOT of space when generating docs for all 1200 chips
because they don't deduplicate.
These files end up containing chip-specific info, so they deduplicate
really badly when building docs for all 1200 chips.
The doc generator removes files starting with `_`.
636: stm32: Add support for using TIM12 and TIM15 as time driver r=Dirbaio a=matoushybl
I am not sure what the effect of reducing the number of alarms will be, but these are the only timers I have available on my board.
Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
646: Debloat stm32-metapac r=Dirbaio a=Dirbaio
- Remove usage of `peripheral_counts!` macrotables.
- Remove `dbgmcu!` macrotable.
- Move the remaining macrotables to embassy-stm32 build.rs. This brings metapac decompressed size from ~250mb to ~100mb
- Deduplicate files with identical metadata. This brings decompressed size from ~100mb to ~70mb, compressed from ~10mb to ~4mb, which is finally small enough to publish on crates.io!
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
645: stm32 usart: Fix RX interrupt flag handling r=lulf a=timokroeger
* On v1 interrupts cannot be cleared individually.
Instead they are cleared implicitly by reading or writing DR (which we do now).
* Multiple error flags can be set at the same time:
Handle them all in one go intstead of re-entering the ISR for each one so that
we do not lose any error flags on v1 hardware.
* Wake when the RX buffer becomes full: This allows fast running chips to pull data
from the buffer before receiving the next byte.
Tested on v1 hardware, lets see if v2 still succeeds on CI.
Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
* On v1 interrupts cannot be cleared individually.
Instead they are cleared implicitly by reading or writing DR (which we do now).
* Multiple error flags can be set at the same time:
Handle them all in one go intstead of re-entering the ISR for each one so that
we do not lose any error flags on v1 hardware.
* Wake when the RX buffer becomes full: This allows fast running chips to pull data
from the buffer before receiving the next byte.
639: stm32: move pin trait impls from macrotables to build.rs r=Dirbaio a=Dirbaio
Continuation of work from #601#638
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
638: stm32: move dma trait impls from macrotables to build.rs r=Dirbaio a=Dirbaio
Continuation of work from #601
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
