4cffa200bd
eth: Add lan8742a PHY
2021-06-16 16:48:35 +02:00
46e1bae9e3
eth-v2: Start Ethernet peripheral implementation
2021-06-16 16:48:35 +02:00
6386c34079
Merge pull request #250 from lulf/dual-core
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Add support for generating PAC for dual cores
2021-06-16 16:46:01 +02:00
a4ea08f89f
Update submodule
2021-06-16 16:31:12 +02:00
56c5218292
Prescaler 1 means divide by 3 on WL55
2021-06-16 16:21:16 +02:00
383beb37b3
Rename from wl55 to wl5x and enable debug wfe
2021-06-16 16:07:21 +02:00
b6a8703698
Add support for generating PAC for dual cores
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* Chips that have multiple cores will be exposed as chipname_corename,
i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
and pick the first and only core from the list
* Add support for stm32wl55 chip family
2021-06-16 15:12:07 +02:00
927be50109
Merge pull request #249 from embassy-rs/nrf-pacs
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nrf: use released nrf52805-pac, nrf52820-pac
2021-06-15 23:12:55 +02:00
76ae9e0e7c
nrf: use released nrf52805-pac, nrf52820-pac
2021-06-15 22:25:37 +02:00
c9bf039cae
Merge pull request #248 from lulf/add-timer-frequencies
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Add separate fields for timer frequencies
2021-06-15 17:29:48 +02:00
8ae4f47d3d
Fix compile
2021-06-15 16:44:00 +02:00
49fad2de8a
Use correct frequencies for timers
2021-06-15 16:07:23 +02:00
ceb5d92da3
Merge pull request #246 from lulf/remove-default-rcc
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Remove default rcc impl
2021-06-14 20:30:02 +02:00
4b406dd107
Remove default rcc impl
2021-06-14 20:24:51 +02:00
fd24677f84
Merge pull request #245 from bobmcwhirter/adc_v3
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ADCv3 and example.
2021-06-14 19:26:42 +02:00
d58fb11b2e
ADCv3 and example.
2021-06-14 13:20:42 -04:00
0dafd8f763
Merge pull request #241 from lulf/get-clock-frequencies
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Provide a way for a peripheral to query its clock frequency
2021-06-14 16:22:14 +02:00
531093f281
Derive SPI v1 and v3 clocks automatically
2021-06-14 11:58:16 +02:00
5e1b0a5398
Add wb55 clocks
2021-06-14 11:41:02 +02:00
ee9f67fa01
Add common types
2021-06-14 11:33:11 +02:00
a2da2a6db2
Remove unused l0 code
2021-06-14 11:33:11 +02:00
95532726b2
Add minimal RCC impls for L4 and F4
2021-06-14 11:33:11 +02:00
a13e07625f
Add ... c1?
2021-06-14 11:33:11 +02:00
0b52731897
Add clocks for h7
2021-06-14 11:33:11 +02:00
2c63393c9e
Add Clock type per RCC family
2021-06-14 11:33:11 +02:00
952f525af5
Provide a way for a peripheral to query its clock frequency
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Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
2021-06-14 11:33:11 +02:00
85f172dd93
Merge pull request #244 from Tiwalun/fix-gen-macos
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Make gen.py work without CSafeLoader
2021-06-12 20:20:09 +02:00
9edb6e41ce
Make gen.py work without CSafeLoader
2021-06-12 18:28:21 +02:00
97e2f10665
Merge pull request #242 from Tiwalun/stm32wb55-metapac
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Initial support and example for STM32WB55
2021-06-12 16:33:40 +02:00
b82e2627aa
Add STM32WB55 examples to CI, fix example crate name
2021-06-12 07:06:42 +02:00
0eab96f573
Initial support and example for STM32WB55
2021-06-12 07:06:36 +02:00
3353f59a43
Merge pull request #243 from embassy-rs/update-smoltcp
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UPdate smoltcp
2021-06-12 00:56:24 +02:00
890e93f367
UPdate smoltcp
2021-06-12 00:50:36 +02:00
def8870cbb
Merge pull request #240 from lulf/enable-timer-clock
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Enable timer clock in RCC on timer start
2021-06-11 16:30:54 +02:00
6c7fd3e3c4
Refactor
2021-06-11 16:21:51 +02:00
8dd3ddd228
Special handling for timers instead
2021-06-10 09:52:57 +02:00
0a9022d59f
Enable timer clock in RCC on timer start
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* Moves the tim2-specific code into macro which always uses TIM2
* For peripherals without clock specified, attempt to locate enable and
reset registers in the RCC block matching the peripheral name. This
could be useful for peripherals where deducing the clock name might
not be feasible, but it remains to be tested with more chip families
to see if it is sufficiently accurate.
2021-06-10 09:37:30 +02:00
37fbc5fcc4
Merge pull request #239 from lulf/add-h7ab-missing
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Update reference to missing H7AB
2021-06-10 09:04:22 +02:00
2493fde536
Update reference to missing H7AB
2021-06-10 08:58:18 +02:00
bd7425a571
Merge pull request #228 from embassy-rs/metapac2
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stm32-metapac: add new codegen, allows pregenerating the entire pac
2021-06-10 03:49:41 +02:00
c5a418a9a6
Run metapac full gen in Ci
2021-06-10 03:05:44 +02:00
189ab7b00e
Update stm32-data to fix rcc_h7ab issues.
2021-06-10 03:03:44 +02:00
5b8ac447f2
stm32-metapac: add new codegen, allows pregenerating the entire pac
2021-06-10 02:33:38 +02:00
08bd140c6d
Merge pull request #238 from lulf/add-stm32l0-examples
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Add stm32l0 examples
2021-06-09 23:12:44 +02:00
1a51fd0453
Add all examples to workspace template
2021-06-09 23:12:25 +02:00
1bb7123156
Add examples for STM32L0
2021-06-09 23:09:48 +02:00
3d16e922d5
Merge pull request #237 from lulf/enable-clock-for-peris
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Infer enable and reset registers based on RCC registry file
2021-06-09 23:09:00 +02:00
9a2adec584
Make RCC lookup optional
2021-06-09 19:33:29 +02:00
f3d1ac6623
Enable clock for RNG
2021-06-09 13:54:53 +02:00
a92d6a372b
Cleanup and fix l4s
2021-06-09 13:50:04 +02:00
