Commit Graph

723 Commits

Author SHA1 Message Date
c6a11db39e Merge #854
854: Implement IWDG timeout calculation r=Dirbaio a=chemicstry

Allow specifying `IndependentWatchdog` timeout as `Duration` instead of prescaler value.

Since IWDG is clocked from LSI, which differs between families, I standardized HSI/LSI definitions in RCC and used that.

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-07-10 21:45:34 +00:00
5a208d28d0 Fix g0 rcc build 2022-07-11 00:37:00 +03:00
93e7d53e39 Merge #851
851: Gpio dynamic flex r=Dirbaio a=AntoineMugnier

Add Flex GPIO type for embassy-stm32 as it is the case for  embassy-nrf.


Co-authored-by: amugniere@gmail.com <antoine.mugnier@depixus.com>
2022-07-10 21:22:46 +00:00
d7d1e46a5f Use u32 instead of Duration for IWDG 2022-07-11 00:00:33 +03:00
323b0d1a5c Have removed ANOTHER redondant ErrorType trait impl 2022-07-10 22:01:48 +02:00
1eca026ebd Have removed redondant ErrorType trait impl 2022-07-10 21:36:04 +02:00
e4a36e1d98 rustfmt on previously edited files 2022-07-10 21:08:12 +02:00
53388d4576 have adapted access to pin() and port() methods of Sealed::Pin in exti.rs according to previous changes on Input struct 2022-07-10 20:55:04 +02:00
3bf1e1d4aa Fix f2, wl compilation 2022-07-10 21:46:14 +03:00
f43545f36e Fix warnings 2022-07-10 21:16:54 +03:00
85054a7233 Fix typo 2022-07-10 21:15:38 +03:00
1fd5022e72 Refactor IWDG to use LSI frequency from RCC 2022-07-10 20:59:36 +03:00
bd01e90bfa Implement IWDG timeout calculation 2022-07-10 20:38:30 +03:00
5f43c1d37e Merge #850
850: Shared buses with SetConfig r=Dirbaio a=kalkyl

Addresses issue #830 

Co-authored-by: Henrik Alsér <henrik@mindbite.se>
2022-07-10 00:03:44 +00:00
fa3e1ab68a correction of the access to flex pin attribute in gpio_v2 2022-07-09 14:06:47 +02:00
880b71a1e8 impl SetConfig for stm32 i2c and SPI 2022-07-09 02:28:05 +02:00
39702d7624 set_as_input_output() and set_as_output() : Have added comments and made functions public 2022-07-08 21:46:16 +02:00
43aec9083c Cleanup 2022-07-08 08:03:38 +02:00
01ef03f446 stm32/i2c: impl ErrorType for all. 2022-07-07 15:46:30 +02:00
399e7a4791 NoDma 2022-07-07 15:46:30 +02:00
be731b222e Cleanup 2022-07-07 15:46:30 +02:00
0fe818f4f8 v1 fix 2022-07-07 15:46:30 +02:00
1ed5b387f9 v2 fix 2022-07-07 15:46:30 +02:00
02812754ec rustfmt 2022-07-07 15:46:30 +02:00
2460d21fa4 Add EH 1.0 impls for stm32 i2c 2022-07-07 15:46:30 +02:00
4e54d09ab1 Have added OutputOpenDrain with Flex 2022-07-04 22:38:05 +02:00
13b259d7cd Have added Flex to eh01 and eh2 2022-07-04 22:19:02 +02:00
359fc4d124 Flex GPIO implementation : Output 2022-06-30 23:03:15 +02:00
f05082b9a3 have reverted changed in mod eh1 from previous commit 2022-06-30 22:55:57 +02:00
9b3c5af92a Flex GPIO implementation : Input 2022-06-30 22:50:53 +02:00
d1d07cd9e3 fix case when chip has multiple iwdg 2022-06-28 13:22:43 +02:00
f2ad9c2d9d rebase and fix unborrow 2022-06-28 12:51:08 +02:00
74bbf5aa02 address review 2022-06-28 12:46:17 +02:00
5cf3fbece4 initial independent watchdog implementation 2022-06-28 12:46:17 +02:00
a855889f70 Update stm32-data 2022-06-27 02:10:01 +02:00
397722c328 stm32: fix f100 build. 2022-06-26 23:52:38 +02:00
3cdd8c1aeb Fix PWM for advanced timers 2022-06-23 02:27:39 +03:00
88e36a70bd Update to 2021 edition. (#820) 2022-06-18 02:15:48 +02:00
9031b8f80a Fix doc comments for BpskPacketParams 2022-06-16 07:34:59 +02:00
d0edd171f8 Fix typo in LoRaPacketParams::new doc 2022-06-16 06:22:03 +02:00
faa59efbf6 Cargo fmt 2022-06-15 09:01:22 +02:00
3696226fe8 Sync subghz peripheral support with stm32wlxx-hal 2022-06-14 16:27:42 +02:00
a8703b7598 Run rustfmt. 2022-06-12 22:22:31 +02:00
5085100df2 Add embassy-cortex-m crate.
- Move Interrupt and InterruptExecutor from `embassy` to `embassy-cortex-m`.
- Move Unborrow from `embassy` to `embassy-hal-common` (nothing in `embassy` requires it anymore)
- Move PeripheralMutex from `embassy-hal-common` to `embassy-cortex-m`.
2022-06-12 21:45:38 +02:00
db344c2bda common/PeripheralMutex: remove unsafe API. (#802)
Following the project's decision that "leak unsafe" APIs are not marked as "unsafe",
update PeripheralMutex to accept non-'static state without unsafe.

Fixes #801
2022-06-09 21:28:13 +02:00
7d64f5cda7 Use correct index and bank 2022-06-07 15:59:22 +02:00
3e4bead321 stm32: add USB driver. 2022-06-07 03:29:00 +02:00
0aa73f58e2 Update stm32-metapac. 2022-06-07 00:28:26 +02:00
b0ffd9a1cc Fix AF pullup configuration for GPIOv1 2022-06-06 17:12:52 +03:00
70e4418df9 Merge #781 #785
781:  embassy-net v2 r=Dirbaio a=Dirbaio

- No more `dyn`
- It's no longer a global singleton, you can create muliple net stacks at once.
  - You can't tear them down though, the Device it still has to be `'static` due to restrictions with smoltcp's "fake GAT" in the Device trait. :(
- Removed `_embassy_rand` hack, random seed is passed on creation.



785: stm32: g0: add PLL clock source r=Dirbaio a=willglynn

STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at 16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach 64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q` to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main reason the user will configure the PLL, so `r` is mandatory and the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the MCO and MCO2 peripherals, so `q` is optional and the output is conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()` calls `PllConfig::init()` which initializes the PLL per [RM0454]. It disables the PLL, waits for it to stop, enables the source oscillator, configures the PLL, waits for it to lock, and then enables the appropriate outputs. `rcc::init()` then switches the clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This was likely a blocker for anyone using HSE >= 24 MHz, with or without the PLL.) Flash accesses are now automatically slowed down as needed before changing the clock source, and sped up as permitted after changing the clock source. The number of flash wait states also determines if flash prefetching will be profitable, so that is now handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Co-authored-by: Will Glynn <will@willglynn.com>
2022-05-31 00:25:21 +00:00