Fix g0 rcc build

2022-07-11 00:37:00 +03:00 · 2022-07-11 00:37:00 +03:00 · 5a208d28d0
commit 5a208d28d0
parent 5044361ddd
1 changed files with 1 additions and 1 deletions
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@ -361,7 +361,7 @@ pub(crate) unsafe fn init(config: Config) {
            // Enable LSI
            RCC.csr().write(|w| w.set_lsion(true));
            while !RCC.csr().read().lsirdy() {}
-            (LSI_FREQ, Sw::LSI)
+            (LSI_FREQ.0, Sw::LSI)
        }
    };