b24520579a
rcc: ahb/apb -> hclk/pclk
2023-10-15 19:51:35 -05:00
1fc35c753b
rcc: update pll clock naming
2023-10-15 15:10:42 -05:00
b91d1eaca0
stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.
2023-10-11 04:12:38 +02:00
0cfa8d1bb5
stm32/rcc: use more PLL etc enums from PAC.
2023-10-11 00:12:33 +02:00
6186fe0807
stm32/rcc: use PLL enums from PAC.
2023-10-09 02:48:22 +02:00
e03239e88d
stm32: centralize enabling pwr, syscfg, flash.
2023-09-25 01:07:55 +02:00
561696dfad
Fix typo in F2 RCC voltage ranges
2023-09-19 10:20:25 +02:00
4bfbcd6c72
stm32: use PAC enums for VOS.
2023-09-18 03:15:15 +02:00
a6ef314be1
stm32: update configure_ls as agreed
2023-09-17 18:41:45 -05:00
de2773afdd
stm32/rcc: convert bus prescalers to pac enums
2023-09-16 17:41:11 -05:00
11a78fb1e4
rcc: more cleanup
2023-09-08 18:20:58 -05:00
6770d8e8a6
Allow the RTC clock source to be configured with the new RTC mechanism
2023-09-06 00:04:09 +01:00
48085939e7
stm32/rcc: rename common to bus
2023-08-27 08:35:13 -05:00
df6952648e
Make sure to check RCC settings for compatibility before applying
2023-08-16 14:11:09 +02:00
3aef5999d5
Merge pull request #1716 from xoviat/rcc-p
...
stm32/rcc: extract and combine ahb/apb prescalers
2023-07-30 20:43:54 +00:00
2f18770e27
stm32/rcc: extract and combine ahb/apb prescalers
2023-07-30 09:52:30 -05:00
e0ce7fcde7
stm32f2 pll overflow with crystal
...
With a large enough HSE input frequency, the vco clock calculation will
overflow a u32. Therefore, in this specific case we have to use the
inner value and cast to u64 to ensure the mul isn't clipped before
applying the divider.
2023-07-30 01:00:53 +01:00
e892014b65
Update stm32-metapac, includes chiptool changes to use real Rust enums now.
2023-06-29 02:01:33 +02:00
f3699e67b9
Fix typo in derivation of PLLP divisor
2023-04-12 02:07:31 +02:00
3bf1e1d4aa
Fix f2, wl compilation
2022-07-10 21:46:14 +03:00
1fd5022e72
Refactor IWDG to use LSI frequency from RCC
2022-07-10 20:59:36 +03:00
a8703b7598
Run rustfmt.
2022-06-12 22:22:31 +02:00
e88559c5ca
Use defmt-friendly error handling
2022-04-30 11:41:17 +03:00
07ad52162b
Add PLL config support for F2
2022-04-29 18:21:40 +03:00
0cfe1dc9df
Move HSE config out of main clock mux
...
This makes the configuration more flexible and closer to the underlying
configuration register structure. For example, we could use HSI for the
system clock, but use HSE to output a clock with MCO.
2022-04-29 17:51:18 +03:00
a608d0deaf
Add minimal STM32F2 RCC
...
No support for PLL or other clocks than SYSCLK/AHB/APB1/APB2
2022-03-27 18:40:49 +03:00
