Commit Graph

1733 Commits

Author SHA1 Message Date
Grant Miller
d426caefbf Move NoPin impls from v1 to mod 2021-12-06 14:02:21 -06:00
bors[bot]
8b4a247af2
Merge #517
517: Fix embassy-net documentation of running examples. r=lulf a=matoushybl

and fix weird indentation.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-12-06 14:39:53 +00:00
Matous Hybl
a802fd83aa Fix embassy-net documentation of running examples. 2021-12-06 14:59:15 +01:00
bors[bot]
7c155c3aba
Merge #514
514: Refactor sx127x driver to use async SPI r=lulf a=lulf

It also contains a fix to SPI DMA transfer/read_write operations to ensure MISO doesn't contain any old data.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2021-12-06 08:35:11 +00:00
Ulf Lilleengen
81ec4c82fd Flush MISO before transfer operation 2021-12-03 09:53:28 +01:00
Ulf Lilleengen
9a730ef692 Refactor sx127x radio to use async SPI with DMA 2021-12-03 09:53:28 +01:00
Ulf Lilleengen
b9693c0b91 Update rust-lorawan to version supporting defmt 0.3 2021-12-02 19:10:29 +01:00
bors[bot]
6d6e6f55b8
Merge #513
513: Update stm32data ref r=lulf a=lulf

Not including the changes to stm32-data main which seems to break the build.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2021-12-02 17:55:07 +00:00
Ulf Lilleengen
5d057eb12c Update stm32data ref 2021-12-02 18:46:53 +01:00
bors[bot]
df9a41c3eb
Merge #515
515: Downcast timer to GP16 for time drivers. r=lulf a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-12-02 17:13:55 +00:00
Matous Hybl
6e0eb33ea8 Downcast timer to GP16 for time drivers. 2021-12-02 18:07:05 +01:00
bors[bot]
51c26a7d05
Merge #512
512: nrf9160: fix gpiote r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-12-02 03:03:52 +00:00
Dario Nieuwenhuis
edbe242ccc ci: add gpiote+time-driver to embassy-nrf to catch more failures. 2021-12-02 04:01:39 +01:00
Dario Nieuwenhuis
6dd55265cd nrf/gpiote: fix build for nrf9160 2021-12-02 04:01:03 +01:00
bors[bot]
2d620df9d6
Merge #511
511: Fix wrong pin configuration in STM32's SPI v3. r=matoushybl a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-12-01 21:29:04 +00:00
Matous Hybl
f0cb77443c Fix wrong pin configuration in STM32's SPI v3. 2021-12-01 22:18:14 +01:00
bors[bot]
9500c8c17b
Merge #509
509: Remove unsafe from nRF uarte and improve doco with rationale r=Dirbaio a=huntc

The constructors themselves are not strictly unsafe. Interactions with DMA can be generally unsafe if a future is dropped, but that's a separate issue. It is important that we use the `unsafe` keyword diligently as it can lead to confusion otherwise.

I've also provided some rationale re. the usage of [Uarte] vs [BufferedUarte].

Co-authored-by: huntc <huntchr@gmail.com>
2021-11-30 22:39:18 +00:00
huntc
496ad4ed43 Rationale for uarte usage 2021-12-01 09:37:09 +11:00
huntc
469852c667 Removed unsafe from uarte
The constructors themselves are not strictly unsafe. Interactions with DMA can be generally unsafe if a future is dropped, but that's a separate issue. It is important that we use the `unsafe` keyword diligently as it can lead to confusion otherwise.
2021-12-01 09:14:24 +11:00
bors[bot]
e36e36dab6
Merge #507
507: Stm32 data upate 4 r=Dirbaio a=Dirbaio

Main imrpvement is RCC regs info comes from yamls now.

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-29 01:28:24 +00:00
Dario Nieuwenhuis
b0fabfab5d Update stm32-data: rcc regs info comes from yamls now. 2021-11-29 02:28:02 +01:00
Dario Nieuwenhuis
3332c40705 examples: remove unused deps. 2021-11-29 02:07:48 +01:00
bors[bot]
2a2911221d
Merge #506
506: Clock cleaning r=Dirbaio a=lulf

Different STM32 RCC peripherals have different capabilities and register values. Define types for each RCC types inside each module to ensure full range of capabilities for each family can be used

Co-authored-by: Ulf Lilleengen <ulf.lilleengen@gmail.com>
2021-11-28 19:41:16 +00:00
Ulf Lilleengen
25b49a8a2a Remove common clock types
Different STM32 RCC peripherals have different capabilities and register
values. Define types for each RCC types inside each module to ensure
full range of capabilities for each family can be used
2021-11-28 16:46:08 +01:00
Ulf Lilleengen
1b24b3bd68 Make ci script run on Mac OS X 2021-11-28 14:07:21 +01:00
bors[bot]
543cc65e56
Merge #449
449: STM32: Add PWM support r=Dirbaio a=bgamari

Here is a first-cut at implementing PWM support for STM32 targets via the TIM peripherals. Currently this only contains pin configuration for the STM32G0 but it would be straightforward to extend to other platforms.

Co-authored-by: Ben Gamari <ben@smart-cactus.org>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-27 02:07:43 +00:00
Dario Nieuwenhuis
006e567716 stm32/pwm: allow using the advanced timer instances too. 2021-11-27 03:06:53 +01:00
Dario Nieuwenhuis
e40555e245 examples/stm32g4: add pwm example 2021-11-27 03:06:46 +01:00
Dario Nieuwenhuis
d7d1258411 stm32/pwm: small cleanups 2021-11-27 03:05:10 +01:00
Dario Nieuwenhuis
22fad1e7bc stm32/pwm: impl instance/pin for all chips 2021-11-27 03:04:50 +01:00
Ben Gamari
8211d58ee2 stm32/pwm: initial commit 2021-11-27 02:50:30 +01:00
bors[bot]
793f4b1f7d
Merge #505
505: stm32: add stm32g4 support. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-27 01:44:23 +00:00
Dario Nieuwenhuis
88d4b0c00d stm32: add stm32g4 support. 2021-11-27 02:34:23 +01:00
bors[bot]
c7d9729028
Merge #486
486: Pwm ppi events r=Dirbaio a=jacobrosenthal

More PWM yak shaving. I was going to do some safe pwm ppi events stuff but I just dont think it fits this api design.. ppi is just very low level, im not sure how safe it will be in general

* first we should probably have borrows of handlers for ppi with lifetime of the peripheral?  hal does eb4ba6ae42/nrf-hal-common/src/pwm.rs (L714-L716)
* in general having access to tasks can put the state in some configuration the api doesnt understand anymore. for `SequencePwm` ideally id hand you back either only seq_start0 or seq_start1 because youd only use one based on if your `Times` is even or odd.. but again we only know that with this api AFTER start has been called. I dont think were ready for typestates

SO I figured why not add the pwm ppi events but make them unsafe and commit this example since I started it.

Somewhat related drop IS removing the last duty cycle from the pin correctly, but stop DOES NOT..the only thing that sets the pin back is pin.conf() as far as I can tell, so I tried to document that better and got rid of stop for the `SimplePwm` again since that doesnt need it then. However its ackward we dont have a way to unset the pwm without setting a new sequence of 0s, or dropping the peripheral


Co-authored-by: Jacob Rosenthal <jacobrosenthal@gmail.com>
2021-11-26 23:08:24 +00:00
Dario Nieuwenhuis
524eed5db5 Update smoltcp, fix build issues with no ethernet. 2021-11-26 21:09:44 +01:00
bors[bot]
6aa27d1a8e
Merge #504
504: net: update smoltcp r=Dirbaio a=Dirbaio

What it says on the tin

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-26 03:15:54 +00:00
Dario Nieuwenhuis
c257893da9 net: update smoltcp 2021-11-26 04:12:14 +01:00
bors[bot]
539c007b44
Merge #502
502: Ensure SPI DMA write is completed r=lulf a=lulf

Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2021-11-24 20:02:49 +00:00
bors[bot]
32d52c89a9
Merge #503
503: net: don't depend directly on smoltcp outside embassy-net r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-24 19:22:04 +00:00
Dario Nieuwenhuis
e4de15e4de net: don't depend directly on smoltcp outside embassy-net 2021-11-24 17:48:48 +01:00
Ulf Lilleengen
cd9a1d547c Ensure SPI DMA write is completed
Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.
2021-11-24 14:59:18 +01:00
bors[bot]
8fea6c94f6
Merge #501
501: stm32-metapac cleanups r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-24 01:00:22 +00:00
Dario Nieuwenhuis
f9934fb56b ci: do main build with fully generated stm32-metapac. 2021-11-24 01:43:53 +01:00
Dario Nieuwenhuis
e187f50f4b stm32: remove unused deps 2021-11-24 01:41:51 +01:00
Dario Nieuwenhuis
78d109f5d5 stm32-metapac: add pac feature to allow building only the macrotables. 2021-11-24 01:04:23 +01:00
Dario Nieuwenhuis
d06cb0a264 stm32-metapac-gen: use actually common common.rs instead of emitting it at every single chip file. 2021-11-24 00:42:14 +01:00
bors[bot]
e725d22fd4
Merge #489
489: Faster CI with cargo-batch r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-23 23:24:27 +00:00
Dario Nieuwenhuis
dfb6d407a1 stm32: rename core features from _cmX to -cmX, cleanup gen. 2021-11-23 23:49:06 +01:00
bors[bot]
b0da114395
Merge #491
491: Fix interrupt_take macro by specifying path to panic macro. r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-11-23 14:34:15 +00:00
Matous Hybl
0ca6060bfd Fix interrupt_take macro by specifying path to panic macro. 2021-11-23 11:00:37 +01:00