Commit Graph

884 Commits

Author SHA1 Message Date
kalkyl
ab63f3832f rp: Read flash unique id and jedec id 2023-05-16 11:21:17 +02:00
bors[bot]
1a87f7477a
Merge #1458
1458: rp: remove take!, add bind_interrupts! r=Dirbaio a=pennae

both of the uart interrupts now check a flag that only the dma rx path ever sets (and now unsets again on drop) to return early if it's not as they expect. this is ... not our preferred solution, but if bind_interrupts *must* allow mutiple handlers to be specified then this is the only way we can think of that doesn't break uarts.

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-15 15:59:30 +00:00
pennae
14a5d03af2 rp: remove take!, add bind_interrupts! 2023-05-15 15:24:56 +02:00
Dario Nieuwenhuis
62857bdb2d net: reexport UDP PacketMetadata under the udp module. 2023-05-15 00:55:34 +02:00
Dario Nieuwenhuis
26d7610554 net: do not use smoltcp Instant/Duration in public API. 2023-05-15 00:53:30 +02:00
Dario Nieuwenhuis
2fcdfc4876 rp: don't use SetConfig trait in PWM and PIO.
It was intended to allow changing baudrate on shared spi/i2c. There's no
advantage in using it for PWM or PIO, and makes it less usable because you have to
have `embassy-embedded-hal` as a dep to use it.
2023-05-13 02:13:26 +02:00
bors[bot]
7f96359804
Merge #1424
1424: add TL maibox for stm32wb r=xoviat a=OueslatiGhaith

Hello,

This pull request is related to #1397 and #1401, inspired by #24, build upon the work done in #1405, and was tested on an stm32wb55rg.

This pull request aims to add the transport layer mailbox for stm32wb microcontrollers. For now it's only capable of initializing it and getting the firmware information

Co-authored-by: goueslati <ghaith.oueslati@habemus.com>
Co-authored-by: Ghaith Oueslati <73850124+OueslatiGhaith@users.noreply.github.com>
Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-11 22:48:55 +00:00
xoviat
bf45b1d83d fix memory.x 2023-05-11 17:23:18 -05:00
xoviat
d7262f9849 rustfmt 2023-05-11 16:53:55 -05:00
xoviat
8a620fd59c stm32/ble: fix tests and add instructions to run example 2023-05-11 16:45:42 -05:00
Caleb Jamison
9d971e5b15
Merge branch 'master' into master 2023-05-09 17:55:27 -04:00
Caleb Jamison
5cfe1a1fb4 Dirbaio comments round 2 2023-05-09 17:45:24 -04:00
Caleb Jamison
6bea078487 Remove patches, bump rp-pac version 2023-05-09 12:20:23 -04:00
Caleb Jamison
5015c845c5 Improve gpout example, clk_gpout_freq 2023-05-09 12:10:24 -04:00
Dirk Stolle
0584312ef0 Fix some typos 2023-05-08 23:25:01 +02:00
bors[bot]
d0703f83db
Merge #1435
1435: Added example for multi priority executors rp2040 r=Dirbaio a=fakusb

I added an example for multiple priorities of tasks on rp2040 by adjusting [examples/nrf52840/src/bin/multiprio.rs](https://github.com/embassy-rs/embassy/blob/master/examples/nrf52840/src/bin/multiprio.rs) .

This needs https://github.com/embassy-rs/rp-pac/pull/2 , and this commit also adds the 6 new interrupt handlers for software interrupts to embassy-rs.

We might need to change the git path for rp-pac in [embassy-rp/Cargo.toml](https://github.com/embassy-rs/embassy/compare/master...fakusb:rp2040-multiprio-executor?expand=1#diff-47463ea358745927ecdb686f52feab816fde5d402a9628a136c116f34a802ab0)

Closes #1413

Co-authored-by: Fabian Kunze <fkunze@fkunze.de>
2023-05-08 16:59:07 +00:00
Caleb Jamison
59132514cf Add missing functions, Cleanup, Gpout example 2023-05-08 09:45:54 -04:00
Fabian Kunze
87795cbca8 added example multi priority executors rp2040 2023-05-07 01:00:13 +02:00
pennae
b38d496d51 rp/pio: allow wrap-around program loading
execution wraps around after the end of instruction memory and wrapping
works with this, so we may as well allow program loading across this
boundary. could be useful for reusing chunks of instruction memory.
2023-05-06 21:08:20 +02:00
pennae
8e4d65e163 rp/pio: configure state machines with Config struct
the many individual sets aren't very efficient, and almost no checks
were done to ensure that the configuration written to the hardware was
actually valid. this adresses both of these.
2023-05-06 17:23:41 +02:00
pennae
37b460637d rp/pio: add set-pin-{values,dirs} convenience functions
these are needed a lot during state machine setup, it makes sense to
provide convenience functions for them.
2023-05-06 11:52:25 +02:00
pennae
41ec4170a5 rp/pio: add load_program, use_program
programs contain information we could pull from them directly and use to
validate other configuration of the state machine instead of asking the
user to pull them out and hand them to us bit by bit. unfortunately
programs do not specify how many in or out bits they use, so we can only
handle side-set and wrapping jumps like this. it's still something though.
2023-05-06 11:44:04 +02:00
pennae
8ebe6e5f20 rp/pio: drop Pio prefix from almost all names
it's only any good for PioPin because there it follows a pattern of gpio
pin alternate functions being named like that, everything else can just
as well be referred to as `pio::Thing`
2023-05-05 19:08:16 +02:00
bors[bot]
067f1382e4
Merge #1429
1429: rp pio, √9 r=Dirbaio a=pennae

another mix of refactoring and soundness issues. most notably pio pins are now checked for being actually accessible to the pio blocks, are constructible from not just the owned peripherals but refs as well, and have their registrations to the pio block reverted once all state machines and the common block has been dropped.

state machines are now also stopped when dropped, and concurrent rx+tx using dma can finally be done in a sound manner. previously it was possible to do, but allowed users to start two concurrent transfers to the same fifo using different dma channels, which obviously would not have the expected results on average.

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-04 20:04:11 +00:00
ceekdee
91612b7446 Simplify SUBGHZSPI configuration. 2023-05-04 09:45:18 -05:00
goueslati
007f452927 removed hardcoded addresses in memory.x 2023-05-04 11:02:17 +01:00
Chuck Davis
91d1fff4ed
Merge branch 'embassy-rs:master' into master 2023-05-03 21:07:28 -05:00
ceekdee
629e0ea595 Handle SUBGHZSPI as async. 2023-05-03 21:05:47 -05:00
xoviat
7750ea65ba rustfmt 2023-05-03 18:14:42 -05:00
xoviat
a0b1299890 stm32/tests: add hil test for ble 2023-05-03 17:36:31 -05:00
pennae
c44c108db5 rp/pio: wrap sm rx, tx in structs and allow splitting
this *finally* allows sound implementions of bidirectional transfers
without blocking. the futures previously allowed only a single direction
to be active at any given time, and the dma transfers didn't take a
mutable reference and were thus unsound.
2023-05-03 13:00:52 +02:00
pennae
909a5fe2e5 rp/pio: split irqs from state machines
we can only have one active waiter for any given irq at any given time.
allowing waits for irqs on state machines bypasses this limitation and
causes lost events for all but the latest waiter for a given irq.
splitting this out also allows us to signal from state machines to other
parts of the application without monopolizing state machine access for
the irq wait, as would be necessary to make irq waiting sound.
2023-05-03 12:57:21 +02:00
pennae
486fe9e59d rp/pio: remove PioStateMachineInstance
move all methods into PioStateMachine instead. the huge trait wasn't
object-safe and thus didn't have any benefits whatsoever except for
making it *slightly* easier to write bounds for passing around state
machines. that would be much better solved with generics-less instances.
2023-05-03 11:25:58 +02:00
pennae
906d2b2db7 rp/pio: PioStateMachine{Instance, => ,Instance}
next step: get rid of the insance trait entirely
2023-05-03 11:25:58 +02:00
pennae
4ccb2bc95a rp/pio: add PioPin trait
pio can only access pins in bank 0, so it doesn't make sense to even
allow wrapping of other banks' pins.
2023-05-03 11:25:43 +02:00
bors[bot]
2afa08c923
Merge #1425
1425: rp pio, round 2 r=Dirbaio a=pennae

another round of bugfixes for pio, and some refactoring. in the end we'd like to make pio look like all the other modules and not expose traits that provide all the methods of a type, but put them onto the type itself. traits only make much sense, even if we added an AnyPio and merged the types for the member state machines (at the cost of at least a u8 per member of Pio).

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-02 18:03:00 +00:00
pennae
7a36072a15 rp/pio: drop SmInstance{,Base}
these are just overly convoluted ways of writing down numbers.
2023-05-02 18:01:18 +02:00
pennae
a167c77d39 rp/pio: make PioCommon a struct
the PioCommon trait does not serve much of a purpose; there can be only
two implementations and they only differ in a few associated constants.
2023-05-02 18:01:18 +02:00
pennae
8839f3f62a rp/pio: PioInstance::split -> Pio::new
not requiring a PioInstance for splitting lets us split from a
PeripheralRef or borrowed PIO as well, mirroring every other peripheral
in embassy_rp. pio pins still have to be constructed from owned pin
instances for now.
2023-05-02 15:52:50 +02:00
pennae
3229b5e809 rp/pio: remove PioPeripheral
merge into PioInstance instead. PioPeripheral was mostly a wrapper
around PioInstance anyway, and the way the wrapping was done required
PioInstanceBase<N> types where PIO{N} could've been used instead.
2023-05-02 15:46:21 +02:00
pennae
8e22d57447 rp/pio: add hd44780 example
add an hd44780 example for pio. hd44780 with busy polling is a pretty
complicated protocol if the busy polling is to be done by the
peripheral, and this example exercises many pio features that we don't
have good examples for yet.
2023-05-02 13:44:24 +02:00
goueslati
bab30a7e87 added TL Mailbox initialization for STM32WB 2023-05-02 12:16:48 +01:00
bors[bot]
855c0d1423
Merge #1376
1376: rtc: cleanup and consolidate r=Dirbaio a=xoviat

This removes an extra file that I left in, adds an example, and consolidates the files into one 'v2' file.

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-01 19:32:06 +00:00
bors[bot]
05c36e05f9
Merge #1414
1414: rp: report errors from buffered and dma uart receives r=Dirbaio a=pennae

neither of these reported errors so far, which is not ideal. add error reporting to both of them that matches the blocking error reporting as closely as is feasible, even allowing partial receives from buffered uarts before errors are reported where they would have been by the blocking code. dma transfers don't do this, if an errors applies to any byte in a transfer the entire transfer is nuked (though we probably could report how many bytes have been transferred).

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-01 15:35:39 +00:00
pennae
b58b9ff390 rp/uart: report errors from dma receive 2023-05-01 15:36:53 +02:00
pennae
f4ade6af8b rp/pio: write instr memory only from common
instruction memory is a shared resource. writing it only from PioCommon
clarifies this, and perhaps makes it more obvious that multiple state
machines can share the same instructions.

this also allows *freeing* of instruction memory to reprogram the
system, although this interface is not entirely safe yet. it's safe in
the sense rusts understands things, but state machines may misbehave if
their instruction memory is freed and rewritten while they are running.
fixing this is out of scope for now since it requires some larger
changes to how state machines are handled. the interface provided
currently is already unsafe in that it lets people execute instruction
memory that has never been written, so this isn't much of a drawback for now.
2023-05-01 12:58:57 +02:00
pennae
58e727d3b9 rp/pio: move non-sm-specific methods to PioCommon
pin and irq operations affect the entire pio block. with pins this is
not very problematic since pins themselves are resources, but irqs are
not treated like that and can thus interfere across state machines. the
ability to wait for an irq on a state machine is kept to make
synchronization with user code easier, and since we can't inspect loaded
programs at build time we wouldn't gain much from disallowing waits from
state machines anyway.
2023-05-01 12:58:57 +02:00
Chuck Davis
49bed094a3
Merge branch 'embassy-rs:master' into master 2023-04-28 13:35:22 -05:00
ceekdee
49ecd8d7c5 Remove external-lora-phy feature. 2023-04-28 13:33:20 -05:00
ceekdee
9d610c6866 Remove legacy LoRa drivers. 2023-04-27 11:05:33 -05:00