Mateusz Butkiewicz
e1951f3ddf
feat(stm32f7): restore rtc configuration for stm32f7 series
2023-09-27 16:08:05 +02:00
Dario Nieuwenhuis
a57e48459e
stm32/rcc: remove bad limits on l5.
2023-09-26 05:15:09 +02:00
Dario Nieuwenhuis
c604d8a8f1
stm32/rcc: add voltage_scale, flash waitstates.
2023-09-26 05:15:09 +02:00
xoviat
04b09a2acb
stm32/rtc: use rccperi enable
2023-09-25 16:26:29 -05:00
xoviat
2543bcafaf
Merge pull request #1945 from xoviat/bd-2
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stm32: fix bd lsi
2023-09-24 23:41:04 +00:00
xoviat
9f2fc04caa
stm32: fix bd lsi
2023-09-24 18:37:09 -05:00
Dario Nieuwenhuis
e03239e88d
stm32: centralize enabling pwr, syscfg, flash.
2023-09-25 01:07:55 +02:00
Dario Nieuwenhuis
83b4c01273
stm32/rcc: unify h5 and h7.
2023-09-21 23:47:56 +02:00
Christian Enderle
ad64d7b20b
fix low-power: APB1 needed for LSE
2023-09-21 17:17:58 +02:00
Dario Nieuwenhuis
00b9f9acef
stm32/h7: fix bad PWR reg versions.
2023-09-21 00:23:56 +02:00
Sebastian Goll
561696dfad
Fix typo in F2 RCC voltage ranges
2023-09-19 10:20:25 +02:00
Dario Nieuwenhuis
4bfbcd6c72
stm32: use PAC enums for VOS.
2023-09-18 03:15:15 +02:00
xoviat
a6ef314be1
stm32: update configure_ls as agreed
2023-09-17 18:41:45 -05:00
Dario Nieuwenhuis
bbe1d96045
stm32/rcc: use AHBPrescaler div impls in stm32wba
2023-09-17 02:30:50 +02:00
xoviat
de2773afdd
stm32/rcc: convert bus prescalers to pac enums
2023-09-16 17:41:11 -05:00
xoviat
ad0a306ea5
stm32: fix wpan_ble test
2023-09-16 10:19:09 -05:00
Dario Nieuwenhuis
8315cf064e
stm32: add stm32wba support.
2023-09-16 04:04:45 +02:00
xoviat
c28a6bdd0b
stm32: generate adc_common
2023-09-15 17:35:53 -05:00
xoviat
9fb14379c3
stm32: add lp to l0
2023-09-14 18:53:27 -05:00
xoviat
08415e001e
stm32/f3: add high res for hrtim and misc.
2023-09-10 13:33:17 -05:00
xoviat
11a78fb1e4
rcc: more cleanup
2023-09-08 18:20:58 -05:00
xoviat
4550452f43
rustfmt
2023-09-06 17:53:02 -05:00
xoviat
08410432b5
stm32: fix rcc merge
2023-09-06 17:51:40 -05:00
xoviat
3cf3caa3ab
Merge branch 'main' into rcc-bd
2023-09-06 17:49:29 -05:00
xoviat
c21ad04c2e
stm32: extract lse/lsi into bd mod
2023-09-06 17:48:12 -05:00
xoviat
d097c99719
stm32/rcc: add lsi and lse bd abstraction
2023-09-06 17:33:56 -05:00
Olle Sandberg
0d3ff34d80
adc: enable ADC and clock selection for STM32WLx
2023-09-06 06:57:30 +02:00
xoviat
a05afc5426
Merge pull request #1867 from xoviat/adc-g4
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Adc g4
2023-09-05 23:31:03 +00:00
Scott Mabin
6770d8e8a6
Allow the RTC clock source to be configured with the new RTC mechanism
2023-09-06 00:04:09 +01:00
xoviat
7622d2eb61
stm32: fix merge issues
2023-09-05 17:10:15 -05:00
xoviat
7573160077
Merge branch 'main' of https://github.com/embassy-rs/embassy into adc-g4
2023-09-05 17:02:28 -05:00
xoviat
f502271940
stm32: add initial adc f3 impl
2023-09-05 16:46:57 -05:00
Daehyeok Mun
49ba9c3da2
initial support for STM32G4 ADC
2023-09-04 23:36:41 -07:00
xoviat
27dfced285
stm32: fix rcc wb
2023-08-29 19:51:21 -05:00
xoviat
989c98f316
stm32/rtc: autocompute prescalers
2023-08-29 19:41:03 -05:00
xoviat
6b8b145266
stm32: revert changes to rcc f4
2023-08-28 16:17:42 -05:00
xoviat
70a5221b2e
stm32/bd: consolidate enable_rtc
2023-08-28 15:34:08 -05:00
xoviat
e981cd4968
stm32: fix rtc wakeup timing and add dbg
2023-08-27 21:15:57 -05:00
xoviat
cbc92dce05
stm32/bd: fix errors
2023-08-27 15:18:34 -05:00
xoviat
531f51d0eb
rcc/bd: consolidate mod
2023-08-27 15:01:09 -05:00
xoviat
f28ab18d7b
stm32: fix l4 re-export
2023-08-27 09:50:02 -05:00
xoviat
3bf6081eb5
stm32: fix wl re-export
2023-08-27 09:41:31 -05:00
xoviat
fb942e6675
stm32: re-export rtcclocksource
2023-08-27 09:25:14 -05:00
xoviat
10ea068027
stm32/bd: allow dead code
2023-08-27 09:12:04 -05:00
xoviat
4caa8497fc
stm32: extract backupdomain into mod
2023-08-27 09:07:34 -05:00
xoviat
48085939e7
stm32/rcc: rename common to bus
2023-08-27 08:35:13 -05:00
xoviat
cda4047310
stm32: flesh out lp executor
2023-08-24 19:29:11 -05:00
xoviat
83f224e140
stm32/lp: add refcount
2023-08-23 20:18:34 -05:00
xoviat
7bff2ebab3
Merge pull request #1766 from xoviat/rtc-w
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stm32/rtc: add start/stop wakeup
2023-08-22 21:50:53 +00:00
xoviat
5bfddfc9b6
stm32/rcc: add rtc to f410
2023-08-21 18:10:10 -05:00
xoviat
8c12453544
stm32/rcc: set rtc clock on f4
2023-08-21 17:50:18 -05:00
Dario Nieuwenhuis
cc400aa178
stm32: fix f37x build.
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originally broke in https://github.com/embassy-rs/embassy/pull/1762
2023-08-19 01:15:32 +02:00
Dominik Sliwa
5bc0175be9
configure flash latency after axi clock and handle different flash in STM32H7A/B devices
2023-08-18 23:44:56 +02:00
Dario Nieuwenhuis
94fa95c699
Merge pull request #1793 from ARizzo35/stm32l4-rtc-pwren
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stm32l4: set pwren in rcc regardless of clock source
2023-08-18 10:19:54 +00:00
Adam Rizkalla
62e66cdda3
stm32l4: set pwren in rcc regardless of clock source
2023-08-17 19:16:03 -05:00
Olle Sandberg
c80c323634
stm32-wl: set RTC clock source on RCC init
2023-08-16 14:41:00 +02:00
Sebastian Goll
df6952648e
Make sure to check RCC settings for compatibility before applying
2023-08-16 14:11:09 +02:00
xoviat
32fdd4c787
tests/stm32: fix rtc test
2023-08-08 20:33:24 -05:00
xoviat
6a73ab1afa
stm32/l4: set rtc clock source in rcc
2023-08-08 19:58:03 -05:00
xoviat
6fc5c608f8
stm32/rtc: remove generics and segregate clock sel
2023-08-08 19:47:01 -05:00
xoviat
28618d12a1
stm32/rtc: restructure
2023-08-06 11:58:28 -05:00
xoviat
66c1712118
stm32/rtc: enable in rcc mod
2023-08-06 11:11:53 -05:00
Bartek
5fcebd28f4
Fix unlocking the backup domain when enabling LSE
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Set PWREN bit to enable the power interface clock before enabling access to the backup domain.
2023-08-01 13:46:34 +09:30
Dario Nieuwenhuis
3aef5999d5
Merge pull request #1716 from xoviat/rcc-p
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stm32/rcc: extract and combine ahb/apb prescalers
2023-07-30 20:43:54 +00:00
xoviat
a8a491212b
stm32/rcc: cleanup merge
2023-07-30 10:18:54 -05:00
xoviat
2f18770e27
stm32/rcc: extract and combine ahb/apb prescalers
2023-07-30 09:52:30 -05:00
Scott Mabin
e0ce7fcde7
stm32f2 pll overflow with crystal
...
With a large enough HSE input frequency, the vco clock calculation will
overflow a u32. Therefore, in this specific case we have to use the
inner value and cast to u64 to ensure the mul isn't clipped before
applying the divider.
2023-07-30 01:00:53 +01:00
xoviat
c7c701b3e3
Merge branch 'main' of https://github.com/embassy-rs/embassy into hrtim
2023-07-28 17:18:22 -05:00
Dario Nieuwenhuis
036e6ae30c
Rename embassy-hal-common to embassy-hal-internal, document it's for internal use only. ( #1700 )
2023-07-28 13:23:22 +02:00
xoviat
270d1d59a0
stm32/rcc: use wpan default only for wpan
2023-07-24 18:25:15 -05:00
xoviat
1425dda0a7
stm32/rcc: fix minor issues
2023-07-24 17:19:45 -05:00
xoviat
bd60f003e0
stm32/rcc: move rcc logic from ipcc
2023-07-23 17:01:34 -05:00
xoviat
d42dff45de
Merge branch 'main' of https://github.com/embassy-rs/embassy into hrtim
2023-07-22 14:49:31 -05:00
Phil Markgraf
3bae533066
Enable RTC on STM32WL chips ( #1645 )
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* Add clippy allow to not report if same then branch
* Support enabling RTC clock on STM32WL
* Add clippy allow to not report if same then branch
* Support enabling RTC clock on STM32WL
* Add rtc example for stm32wl
* Address code review feedback
2023-07-15 13:40:23 +02:00
David Purser
69b4e898b3
Correctly calculate target VCO frequency from multipliers
2023-07-07 20:52:44 -05:00
Mathias
1255d8a8ce
Merge branch 'main' of https://github.com/embassy-rs/embassy into embassy-stm32/rcc-rtc-l4
2023-07-05 12:36:42 +02:00
Dario Nieuwenhuis
eb57bb298f
Merge pull request #1617 from xoviat/const-rcc
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stm32/rcc: allow const-propagation
2023-07-04 22:31:55 +00:00
xoviat
953c745ed8
stm32/rcc: allow const-propagation
2023-07-04 16:29:46 -05:00
Dario Nieuwenhuis
9c4df46c46
rustfmt.
2023-07-04 21:34:55 +02:00
Mathias
60b2f075dc
Merge branch 'main' of https://github.com/embassy-rs/embassy into embassy-stm32/rcc-rtc-l4
2023-07-03 19:33:26 +02:00
xoviat
8141d53d94
Merge branch 'main' of https://github.com/embassy-rs/embassy into hrtim
2023-07-01 17:32:25 -05:00
Mathias
d372df7ddb
L4: Switch to MSI to prevent problems with PLL configuration, and enable power to AHB bus clock to allow RTC to run
2023-07-01 12:16:23 +02:00
xoviat
6e13f5b387
rustfmt
2023-06-30 18:33:22 -05:00
Dario Nieuwenhuis
e892014b65
Update stm32-metapac, includes chiptool changes to use real Rust enums now.
2023-06-29 02:01:33 +02:00
Kevin Lannen
5666c56903
STM32G4: Add CRS support to RCC
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Create working CRS USB Example
2023-06-28 16:53:16 -06:00
Dario Nieuwenhuis
ed493be869
stm32: update metapac, includes fix for OTG with 9 endpoints (H7)
2023-06-27 23:58:32 +02:00
Dario Nieuwenhuis
558918651e
stm32: update stm32-metapac.
2023-06-19 03:22:12 +02:00
Kevin Lannen
c94ba84892
stm32g4: PLL: Add support for configuring PLL_P and PLL_Q
2023-06-14 10:44:51 -06:00
Carl St-Laurent
8ddeaddc67
Rename to follow ref manual and CubeIDE
2023-06-08 20:46:48 -04:00
Carl St-Laurent
4185c10bf8
Cleanup
2023-06-04 12:09:03 -04:00
Carl St-Laurent
ade46489f1
Added Vcore boost mode and Flash wait state
2023-06-04 11:57:42 -04:00
Carl St-Laurent
6fe853a7d3
Better comments
2023-06-04 10:58:44 -04:00
Carl St-Laurent
2f269f3256
stm32/rcc: Implement basic PLL support for STM32G4 series
2023-06-03 22:05:24 -04:00
bors[bot]
d28dc08f09
Merge #1486
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1486: feature(embassy-stm32): add RTC MUX selection to embassy-stm32 L4 family r=Dirbaio a=MathiasKoch
To select and setup LSE and/or LSI
Co-authored-by: Mathias <mk@blackbird.online>
2023-05-25 20:13:27 +00:00
Mathias
181c4c5311
Add RTC MUX selection to embassy-stm32 L4 family, to select and setup LSE and/or LSI
2023-05-25 21:28:32 +02:00
Rasmus Melchior Jacobsen
963f3e3059
Align with updated stm32 metapac
2023-05-25 16:06:02 +02:00
Marco Pastrello
db2bc8783e
Improve readability
2023-05-05 19:04:58 +02:00
Marco Pastrello
c37f86ff1c
removes unecessary braces
2023-05-05 00:12:32 +02:00
Marco Pastrello
2dcbe75cca
beautify
2023-05-04 23:51:42 +02:00
Marco Pastrello
5158014f3f
PPLXTPRE is a bool.
...
This flag for example permits the following clock tree
configuration on stm32f103r8
let mut config = Config::default();
config.rcc.hse = Some(Hertz(16_000_000));
config.rcc.sys_ck = Some(Hertz(72_000_000));
config.rcc.pclk1 = Some(Hertz(36_000_000));
config.rcc.pclk2 = Some(Hertz(72_000_000));
config.rcc.pllxtpre = true;
Init fails if pllxtpre is false.
2023-05-04 22:59:52 +02:00
