Commit Graph

310 Commits

Author SHA1 Message Date
df4aa0fe25 stm32: fix low-power test 2023-10-23 16:26:34 -05:00
62e1e1637c Merge pull request #2097 from embassy-rs/rcc-no-spaghetti
stm32/tests: add stm32h753zi, stm32h7a3zi.
2023-10-21 02:49:12 +00:00
3d03c18d4f stm32/tests: add stm32h753zi, stm32h7a3zi. 2023-10-21 04:46:45 +02:00
0fb677aad7 stm32: update metapac 2023-10-20 20:21:53 -05:00
241488ef1c bypass ODEN if chip doesn't have it 2023-10-18 19:42:31 +08:00
f20f170b1f stm32/rcc: refactor and unify f4 into f7. 2023-10-18 05:11:31 +02:00
67010d123c stm32/rcc: refactor f7. 2023-10-18 05:01:11 +02:00
361fde35cf stm32/rcc: wait for mux switch. 2023-10-18 04:32:18 +02:00
7ce3b19389 stm32/rcc: remove unused enum. 2023-10-18 04:32:18 +02:00
bbd12c9372 stm32: update metapac 2023-10-17 20:31:44 -05:00
683d5c3066 Merge pull request #2077 from xoviat/rcc
stm32: update metapac
2023-10-17 01:05:18 +00:00
a3574e519a stm32: update metapac 2023-10-16 20:04:10 -05:00
e7aeb9b29f stm32f1: Keep flash prefetch enabled 2023-10-16 19:23:01 -05:00
aff77d2b65 stm32/rng: add test. 2023-10-16 05:35:29 +02:00
18e96898ea stm32/rcc: unify L4 and L5. 2023-10-16 04:00:51 +02:00
5c5e681819 stm32/rcc: add better support for L4/L4+ differences. 2023-10-16 03:23:43 +02:00
b24520579a rcc: ahb/apb -> hclk/pclk 2023-10-15 19:51:35 -05:00
1fc35c753b rcc: update pll clock naming 2023-10-15 15:10:42 -05:00
4a156df7a1 stm32: expand rcc mux to g4 and h7 2023-10-14 23:33:57 -05:00
8a10948ce9 stm32/rcc: port L4 to the "flattened" API like h5/h7. 2023-10-15 03:08:49 +02:00
3bfbf2697f stm32/rcc: remove unused lse/lsi fields in h7 2023-10-15 01:48:27 +02:00
824556c9c8 rcc: remove mux_prefix from clocks 2023-10-14 12:51:45 -05:00
3264941c1b rcc mux: update metapac 2023-10-13 23:06:32 -05:00
97ca0e77bf stm32: avoid creating many tiny critical sections in init.
Saves 292 bytes on stm32f0 bilnky with max optimizations (from 3132 to 2840).
2023-10-12 16:20:34 +02:00
ecdd7c0e2f enable clock first 2023-10-12 11:04:44 +02:00
f65a96c541 STM32: combine RccPeripherals reset() and enable() to reset_and_enable() 2023-10-12 11:04:19 +02:00
57ccc1051a stm32: add initial rcc mux for h5 2023-10-11 20:59:47 -05:00
70a91945fc stm32: remove atomic-polyfill. 2023-10-12 02:07:26 +02:00
4a43cd3982 stm32/rcc: LSE xtal is 32768hz, not 32000hz.
Fixes #2043
2023-10-11 13:39:04 +02:00
b91d1eaca0 stm32/rcc: add LSE/LSI to all chips, add RTC to more chips. 2023-10-11 04:12:38 +02:00
21915a9a3f stm32/rcc: unify L0 and L1. 2023-10-11 01:22:27 +02:00
d0d0ceec6a stm32/rcc: rename HSE32 to HSE 2023-10-11 01:06:44 +02:00
0cfa8d1bb5 stm32/rcc: use more PLL etc enums from PAC. 2023-10-11 00:12:33 +02:00
6186fe0807 stm32/rcc: use PLL enums from PAC. 2023-10-09 02:48:22 +02:00
3bf8e4de5f Merge pull request #2015 from willglynn/stm32u5_faster_clocks
stm32: u5: implement >55 MHz clock speeds
2023-10-06 23:38:15 +00:00
3a8e0d4a27 stm32: implement MCO for all chips. 2023-10-07 01:15:24 +02:00
68c4820dde Add MCO support for stm32wl family 2023-10-06 14:37:36 -07:00
f01609036f h7: implement RTC and LSE clock configuration 2023-10-06 13:28:30 -05:00
38e7709a24 stm32: u5: implement >55 MHz clock speeds
This commit allows STM32U5 devices to operate at 160 MHz.

On STM32U5, MSIS can run at 48 MHz and HSE can reach 50 MHz. Faster
clocks require using PLL1's R output, though PLL1 can serve other
functions besides using the R output for the system clock. This commit
extracts a public `PllConfig` struct, primarily to place associated
constructors on that type, but also with an eye towards enabling the P
and Q outputs in a later commit.

STM32U5 PLLs have various frequency requirements on each stage: after
the `m` prescaler, after the `n` multiplier, and after the `r` divider.
This commit implements the associated checks as assertions.

This commit fixes clock calculation and PLL register configuration
errors in PLL initialization.

STM32U5 has a PWR peripheral which can be configured to push Vcore into
different voltage ranges. System clocks exceeding 55 MHz require range
2, and system clocks exceeding 110 MHz require range 1. This commit
adds `voltage_range` to `Config` and configures PWR as directed.

The voltage range implies different performance limits on various clock
signals, including inside a PLL. This commit implements voltage range
<-> frequency range checks as assertions, and extracts the
otherwise-repeated MSIS, HSI16, and HSE initialization into private
methods on `Config`.

STM32U5 frequencies above 55 MHz require using the PWR EPOD booster.
The EPOD booster requires configuring a second `m` term for PLL1,
`mboost`, such that it falls in a particular range. (Recall that >50
MHz cannot be reached without PLL1, so there is no scenario where EPOD
is needed but PLL1 is not.) This commit configures and enables the EPOD
booster automatically as required.
2023-10-05 22:13:27 -05:00
bb8a1b7f1f wpan: re-enable HIL tests 2023-10-03 15:53:22 -05:00
bc203ebe4b Merge branch 'main' of github.com:embassy-rs/embassy into fix-stop 2023-10-02 18:30:41 -05:00
e042b3056d stm32: fix stop 2023-10-02 18:11:03 -05:00
b856d760f4 stm32/rcc: reset backup domain before enabling LSE. 2023-10-02 22:12:50 +02:00
2af97e7595 rcc/f4: fix build on stm32f446
fixes #1989
2023-10-01 23:01:58 +02:00
1be5f193c3 #Issue 1974 more whitespace fixes 2023-09-29 21:53:01 -05:00
4a632e08b7 #Issue 1974 fix extra whitespace 2023-09-29 21:46:19 -05:00
6cdee93934 #Issue 1974 fix more warnings treated as errors 2023-09-29 21:27:15 -05:00
5c8c1b2146 #Issue 1974 fix warnings 2023-09-29 21:16:20 -05:00
2f9b59c5cf Merge branch 'main' into issue-1974-add-sai-driver 2023-09-29 20:02:24 -06:00
ce91fb2bfc Issue #1974 add SAI driver 2023-09-29 20:57:59 -05:00