640: Skip EasyDMA slice location check for empty slices and copy data if necessary r=Dirbaio a=TilBlechschmidt
As discussed, this PR makes the following changes:
- Ignore pointer location of zero-length slices (fixes#631)
- Change default functions so they copy the tx buffer if it does not reside in RAM
- Introduce new variants for `write`, `transfer`, and their blocking versions which fails instead of copying
- Add documentation about the motivation behind all these variants
<img width="984" alt="image" src="https://user-images.githubusercontent.com/5037967/155415788-c2cd1055-9289-4004-959d-be3b1934a439.png">
Remaining TODOs:
- [x] Change copying behaviour for other peripherals
- [x] TWI
- [x] UART
- [x] Add module-level documentation regarding EasyDMA and `_from_ram` method variants
`@Dirbaio` it probably makes sense for you to review it now before I "copy" over the changes to the other two peripherals.
Co-authored-by: Til Blechschmidt <til@blechschmidt.de>
648: Fix nRF Saadc continuous sampling r=Dirbaio a=huntc
Starting the sampling task prior to starting the SAADC peripheral can lead to unexpected buffer behaviour with multiple channels. We now provide an init callback at the point where the SAADC has started for the first time. This callback can be used to kick off sampling via PPI.
We also need to trigger the SAADC to start sampling the next buffer when the previous one is ended so that we do not drop samples - the major benefit of double buffering.
Given these additional tasks, we now simplify the API by passing in the TIMER and two PPI channels.
As a bonus, we provide an async `calibrate` method as it is recommended to use before starting up the sampling.
The example has been updated to illustrate these new features along with the simplified API.
The changes here have been tested on my nRF52840-DK.
656: stm32: Refactor DMA interrupts r=Dirbaio a=GrantM11235
Previously, every dma interrupt handler called the same `on_irq`
function which had to check the state of every dma channel.
Now, each dma interrupt handler only calls an `on_irq` method for its
corresponding channel or channels.
Co-authored-by: huntc <huntchr@gmail.com>
Co-authored-by: Grant Miller <GrantM11235@gmail.com>
Previously, every dma interrupt handler called the same `on_irq`
function which had to check the state of every dma channel.
Now, each dma interrupt handler only calls an `on_irq` method for its
corresponding channel or channels.
Starting the sampling task prior to starting the SAADC peripheral can lead to unexpected buffer behaviour with multiple channels. We now provide an init callback at the point where the SAADC has started for the first time. This callback can be used to kick off sampling via PPI.
We also need to trigger the SAADC to start sampling the next buffer when the previous one is ended so that we do not drop samples - the major benefit of double buffering.
As a bonus we provide a calibrate method as it is recommended to use before starting up the sampling.
The example has been updated to illustrate these new features.
655: common/serial/usb: fix hang when write buffer gets full and then the bus resets. r=Dirbaio a=Dirbaio
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
650: `bxcan` improvements r=Dirbaio a=timokroeger
* Do not use wildcard reexport for `bxcan`
* `cfgs` to fix `bxcan` implementation for devices with "CAN1" but no "CAN2" peripheral
Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
Approach is similar to USB OTG.
STM32L49x and STML4Ax have CAN1 and CAN2.
All others STM32L4xx do only have CAN1.
STM32F72x and STM32F73x are the only F7 devices with only CAN1.
652: Use new stm32-data registers and fix AHB clock calculation r=Dirbaio a=msamsonoff
This is the follow-on to my PR against stm32-data that added new register enums for the G0. I have updated the G0 RCC module to use those new enums.
I have also fixed an issue with the calculation of the AHB clock rate. 32 is not available as an AHB prescaler. The sequence jumps from 16 to 64. The original bit shifting math did not account for this gap. I have replaced it with a `match` instead.
653: Fixes for rustdoc building. r=Dirbaio a=Dirbaio
Co-authored-by: Matthew W. Samsonoff <matt.samsonoff@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
The original code for calculating the AHB clock did not account for the gap in
prescaler values (32 is not an available value.) The bit shifting and math has
been replaced by a `match`.
The source files are unreadable because they're not fmt'd, and
they take up a LOT of space when generating docs for all 1200 chips
because they don't deduplicate.
These files end up containing chip-specific info, so they deduplicate
really badly when building docs for all 1200 chips.
The doc generator removes files starting with `_`.
636: stm32: Add support for using TIM12 and TIM15 as time driver r=Dirbaio a=matoushybl
I am not sure what the effect of reducing the number of alarms will be, but these are the only timers I have available on my board.
Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
646: Debloat stm32-metapac r=Dirbaio a=Dirbaio
- Remove usage of `peripheral_counts!` macrotables.
- Remove `dbgmcu!` macrotable.
- Move the remaining macrotables to embassy-stm32 build.rs. This brings metapac decompressed size from ~250mb to ~100mb
- Deduplicate files with identical metadata. This brings decompressed size from ~100mb to ~70mb, compressed from ~10mb to ~4mb, which is finally small enough to publish on crates.io!
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
645: stm32 usart: Fix RX interrupt flag handling r=lulf a=timokroeger
* On v1 interrupts cannot be cleared individually.
Instead they are cleared implicitly by reading or writing DR (which we do now).
* Multiple error flags can be set at the same time:
Handle them all in one go intstead of re-entering the ISR for each one so that
we do not lose any error flags on v1 hardware.
* Wake when the RX buffer becomes full: This allows fast running chips to pull data
from the buffer before receiving the next byte.
Tested on v1 hardware, lets see if v2 still succeeds on CI.
Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
* On v1 interrupts cannot be cleared individually.
Instead they are cleared implicitly by reading or writing DR (which we do now).
* Multiple error flags can be set at the same time:
Handle them all in one go intstead of re-entering the ISR for each one so that
we do not lose any error flags on v1 hardware.
* Wake when the RX buffer becomes full: This allows fast running chips to pull data
from the buffer before receiving the next byte.
