Commit Graph

4203 Commits

Author SHA1 Message Date
pennae
ed843b519b rp/pio: tighten variance of particle structs
all of these exist in 1:1 correspondence to their parent hal objects, so
let's make all of their lifetimes invariant.
2023-05-05 19:08:16 +02:00
pennae
09f078a1cc rp/pio: remove critical section in IrqFuture::poll
there's nothing this critical section protects against. both read and
write-to-clear are atomic and don't interfere with other irq futures,
only potentially with setting/clearing an irq flag from an arm core.
neither have ever been synchronized, and both have the same observable
effects under atomic writes and critical sections. (for both setting and
clearing an irq flag observable differences could only happen if the
set/clear happened after the poll read, but before the write. if it's a
clear we observe the same effects as sequencing the clear entirely after
the poll, and if it's a set we observe the same effects as sequencing
the set entirely before the poll)
2023-05-05 19:08:16 +02:00
pennae
8ebe6e5f20 rp/pio: drop Pio prefix from almost all names
it's only any good for PioPin because there it follows a pattern of gpio
pin alternate functions being named like that, everything else can just
as well be referred to as `pio::Thing`
2023-05-05 19:08:16 +02:00
Dario Nieuwenhuis
4439031d43 lora: fix docs build. 2023-05-04 22:39:37 +02:00
bors[bot]
067f1382e4
Merge #1429
1429: rp pio, √9 r=Dirbaio a=pennae

another mix of refactoring and soundness issues. most notably pio pins are now checked for being actually accessible to the pio blocks, are constructible from not just the owned peripherals but refs as well, and have their registrations to the pio block reverted once all state machines and the common block has been dropped.

state machines are now also stopped when dropped, and concurrent rx+tx using dma can finally be done in a sound manner. previously it was possible to do, but allowed users to start two concurrent transfers to the same fifo using different dma channels, which obviously would not have the expected results on average.

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-04 20:04:11 +00:00
bors[bot]
72e36d8997
Merge #1431
1431: Simplify SUBGHZSPI configuration r=Dirbaio a=ceekdee

Determine SUBGHZSPI PCLK3 within new_subghz(), controlled by the stm32wl feature.

Co-authored-by: ceekdee <taigatensor@gmail.com>
2023-05-04 14:57:00 +00:00
ceekdee
91612b7446 Simplify SUBGHZSPI configuration. 2023-05-04 09:45:18 -05:00
bors[bot]
b1ef856242
Merge #1430
1430: Handle SUBGHZSPI as async r=lulf a=ceekdee

For STM32WL, simplify configuration for the use of SUBGHZSPI to perform LoRa operations.  Use Rx/Tx DMA on SPI to enable async functionality.

Co-authored-by: ceekdee <taigatensor@gmail.com>
Co-authored-by: Chuck Davis <taigatensor@gmail.com>
2023-05-04 07:19:20 +00:00
Chuck Davis
91d1fff4ed
Merge branch 'embassy-rs:master' into master 2023-05-03 21:07:28 -05:00
ceekdee
629e0ea595 Handle SUBGHZSPI as async. 2023-05-03 21:05:47 -05:00
pennae
c44c108db5 rp/pio: wrap sm rx, tx in structs and allow splitting
this *finally* allows sound implementions of bidirectional transfers
without blocking. the futures previously allowed only a single direction
to be active at any given time, and the dma transfers didn't take a
mutable reference and were thus unsound.
2023-05-03 13:00:52 +02:00
pennae
77f7830da3 rp/pio: move irq flag handling to own struct
this way we can share irq handling between state machines and common
without having to duplicate the methods. it also lets us give irq flag
access to places without having to dedicate a state machine or the
common instance to those places, which can be very useful to eg trigger
an event and wait for a confirmation using an irq wait object.
2023-05-03 13:00:08 +02:00
pennae
909a5fe2e5 rp/pio: split irqs from state machines
we can only have one active waiter for any given irq at any given time.
allowing waits for irqs on state machines bypasses this limitation and
causes lost events for all but the latest waiter for a given irq.
splitting this out also allows us to signal from state machines to other
parts of the application without monopolizing state machine access for
the irq wait, as would be necessary to make irq waiting sound.
2023-05-03 12:57:21 +02:00
pennae
486fe9e59d rp/pio: remove PioStateMachineInstance
move all methods into PioStateMachine instead. the huge trait wasn't
object-safe and thus didn't have any benefits whatsoever except for
making it *slightly* easier to write bounds for passing around state
machines. that would be much better solved with generics-less instances.
2023-05-03 11:25:58 +02:00
pennae
906d2b2db7 rp/pio: PioStateMachine{Instance, => ,Instance}
next step: get rid of the insance trait entirely
2023-05-03 11:25:58 +02:00
pennae
79985f0036 rp/pio: hide pio/sm numbers
nothing should care which number pio it is running on, and the state
machine index could always be extracted from type information.
2023-05-03 11:25:58 +02:00
pennae
6ad58f428a rp/pio: wrap PioPins from ref, like everything else
also store peripheral refs instead of a raw pin/bank number, like
everything else.
2023-05-03 11:25:53 +02:00
pennae
4ccb2bc95a rp/pio: add PioPin trait
pio can only access pins in bank 0, so it doesn't make sense to even
allow wrapping of other banks' pins.
2023-05-03 11:25:43 +02:00
pennae
17e78175a6 rp/pio: disable state machines on drop 2023-05-03 11:25:32 +02:00
pennae
62841dd5b9 rp/pio: revert pio pin funcsel to null on pio+sms drop
once all sharing owners of pio pins have been dropped we should reset
the pin for use by other hal objects. unfortunately this needs an atomic
state per pio block because PioCommon and all of the state machines
really do share ownership of any wrapped pins. only PioCommon can create
them, but all state machines can keep them alive. since state machines
can be moved to core1 we can't do reference counting in relaxed mode,
but we *can* do relaxed pin accounting (since only common and the final
drop can modify this).
2023-05-03 11:25:28 +02:00
pennae
1e8da91def rp/pio: make free_instr unsafe
we can't prove that some instruction memory is not used as long as state
machines are alive, and we can pass instance memory handles between
instances as well. mark free_instr unsafe, with documentation for this caveat.
2023-05-03 08:53:34 +02:00
bors[bot]
374c92a4f0
Merge #1420
1420: stm32/usart: add OVER8 and PRESC, add baudrate test. r=Dirbaio a=Dirbaio

Fixes #1183 
Fixes #1418 

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-05-02 20:14:12 +00:00
Dario Nieuwenhuis
433422b9f2 stm32/test: remove adsfa 2023-05-02 22:13:38 +02:00
Dario Nieuwenhuis
a85b34c1fe stm32/test: F1 no longer fits in RAM. 2023-05-02 22:13:38 +02:00
Dario Nieuwenhuis
1078f6f4e7 stm32/test: workaround #1426 2023-05-02 22:13:38 +02:00
Dario Nieuwenhuis
2bb6e93e86 stm32/usart: add baudrate calc test. 2023-05-02 20:10:09 +02:00
bors[bot]
2afa08c923
Merge #1425
1425: rp pio, round 2 r=Dirbaio a=pennae

another round of bugfixes for pio, and some refactoring. in the end we'd like to make pio look like all the other modules and not expose traits that provide all the methods of a type, but put them onto the type itself. traits only make much sense, even if we added an AnyPio and merged the types for the member state machines (at the cost of at least a u8 per member of Pio).

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-02 18:03:00 +00:00
Dario Nieuwenhuis
a61701b756 stm32/usart: add OVER8 and PRESC support, update PAC 2023-05-02 19:36:00 +02:00
pennae
7a36072a15 rp/pio: drop SmInstance{,Base}
these are just overly convoluted ways of writing down numbers.
2023-05-02 18:01:18 +02:00
pennae
a167c77d39 rp/pio: make PioCommon a struct
the PioCommon trait does not serve much of a purpose; there can be only
two implementations and they only differ in a few associated constants.
2023-05-02 18:01:18 +02:00
pennae
8839f3f62a rp/pio: PioInstance::split -> Pio::new
not requiring a PioInstance for splitting lets us split from a
PeripheralRef or borrowed PIO as well, mirroring every other peripheral
in embassy_rp. pio pins still have to be constructed from owned pin
instances for now.
2023-05-02 15:52:50 +02:00
pennae
ac111f40d8 rp/pio: fix PioPin::set_pull, set_schmitt comment 2023-05-02 15:46:22 +02:00
pennae
3229b5e809 rp/pio: remove PioPeripheral
merge into PioInstance instead. PioPeripheral was mostly a wrapper
around PioInstance anyway, and the way the wrapping was done required
PioInstanceBase<N> types where PIO{N} could've been used instead.
2023-05-02 15:46:21 +02:00
bors[bot]
b2047c4351
Merge #1423
1423: rp: fix gpio InputFuture and inefficiencies r=pennae a=pennae

InputFuture could not wait for edges without breaking due to a broken From impl, but even if the impl had been correct it would not have worked correctly because raw edge interrupts are sticky and must be cleared from software. also replace critical sections with atomic accesses, and do nvic setup only once.

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-02 12:56:51 +00:00
pennae
849011b826 rp/gpio: set up gpio interrupts only once
doing this setup work repeatedly, on every wait, is unnecessary. with
nothing ever disabling the interrupt it is sufficient to enable it once
during device init and never touch it again.
2023-05-02 14:28:27 +02:00
pennae
6cec6fa09b rp/pio: don't use modify on shared registers
pio control registers are notionally shared between state machines as
well. state machine operations that change these registers must use
atomic accesses (or critical sections, which would be overkill).

notably PioPin::set_input_sync_bypass was even wrong, enabling the
bypass on a pin requires the corresponding bit to be set (not cleared).
the PioCommon function got it right.
2023-05-02 13:44:24 +02:00
pennae
0d224a00e1 rp/pio: avoid sm(SM_NO) indexing
accessing the current state machine is an extremely common operation
that shouldn't have its specifics repeated myriad times.
2023-05-02 13:44:24 +02:00
pennae
47ae9b7981 rp/pio: add funcsel values to PioInstance
makes code setting funcsels easier to read and should make it easier to
hook up more pio blocks, should they ever appear
2023-05-02 13:44:24 +02:00
pennae
8e22d57447 rp/pio: add hd44780 example
add an hd44780 example for pio. hd44780 with busy polling is a pretty
complicated protocol if the busy polling is to be done by the
peripheral, and this example exercises many pio features that we don't
have good examples for yet.
2023-05-02 13:44:24 +02:00
bors[bot]
5f99ccf54c
Merge #1422
1422: rp: remove leftovers from #1414 r=Dirbaio a=pennae

forgot to remove these when they were no longer necessary or useful. oops.

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-02 10:07:32 +00:00
pennae
54e695b1b2 rp/pio: fix dma
fixing the dma word size to 32 makes it impossible to implement any
peripheral that takes its data in smaller chunks, eg uart, spi, i2c,
ws2812, the list goes on.

compiler barriers were also not set correctly; we need a SeqCst barrier
before starting a transfer as well to avoid reordering of accesses into
a buffer after dma has started.
2023-05-02 10:56:37 +02:00
pennae
8fc92fdf62 rp/gpio: drop critical_section use
we don't need critical sections if we just use atomic access aliases.
2023-05-02 08:43:04 +02:00
pennae
c6424fdc11 gp/gpio: fix InputFuture edge waits
InputFuture did not use and check edge interrupts correctly.
InterruptTrigger should've checked for not 1,2,3,4 but 1,2,4,8 since the
inte fields are bitmasks, and not clearing INTR would have repeatedly
triggered edge interrupts early.
2023-05-02 08:43:04 +02:00
pennae
3c31236c10 rp: remove leftovers from #1414
forgot to remove these when they were no longer necessary or useful. oops.
2023-05-02 07:40:12 +02:00
bors[bot]
6096f0cf4b
Merge #1404
1404: feat(stm32): Add DMA based, ring-buffer based rx uart, v3 r=Dirbaio a=rmja

This PR replaces #1150. Comparing to that PR, this one has the following changes:

* The implementation now aligns with the new stm32 dma module, thanks `@Dirbaio!`
* Calls to `read()` now returns on either 1) idle line, or 2) ring buffer is at most half full. This is different from the previous pr, which would return a lot of 1 byte reads. Thank you `@chemicstry` for making me realize that it was actually not what I wanted. This is accomplished using half-transfer completed and full-transfer completed interrupts. Both seems to be supported on both dma and bdma.

The implementation still have the issue mentioned here: https://github.com/embassy-rs/embassy/pull/1150#discussion_r1094627035

Regarding the todos here: https://github.com/embassy-rs/embassy/pull/1150#issuecomment-1513905925. I have removed the exposure of ndtr from `dma::RingBuffer` to the uart so that the uart now simply calls `ringbuf::reload_position()` to align the position within the ring buffer to that of the actual running dma controller. BDMA and GPDMA is not implemented. I do not have any chips with those dma controllers, so maybe someone else should to this so that it can be tested.

The `saturate_serial` test utility inside `tests/utils` has an `--idles` switch which can be used to saturate the uart from a pc, but with random idles.

Because embassy-stm32 now can have tests, we should probably run them in ci. I do this locally to test the DmaRingBuffer:  `cargo test --no-default-features --features stm32f429ig`.

cc `@chemicstry` `@Dirbaio` 


Co-authored-by: Rasmus Melchior Jacobsen <rmja@laesoe.org>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-05-01 21:36:10 +00:00
Dario Nieuwenhuis
a1d45303c3 stm32/test: fix race condition in uart_dma. 2023-05-01 23:20:51 +02:00
Dario Nieuwenhuis
7601779693 stm32/test: cleanup ringbuffer test, exit on success (transferring 100kb) 2023-05-01 23:20:51 +02:00
Dario Nieuwenhuis
1806422763 stm32/test: add real defmt timestamp 2023-05-01 23:20:51 +02:00
Dario Nieuwenhuis
00cde67abe stm32/dma: solve overlapping impl on DmaCtrl on stm32h7 2023-05-01 23:20:51 +02:00
Dario Nieuwenhuis
96e8a7ddb9 stm32/uart: feature-gate ringbuffer out when using gpdma, not supported yet. 2023-05-01 22:43:23 +02:00