Prepare executor and macros for release (#1825)

* Set release date, bump macros version

* Add pool_size change to changelog

.github/ci/doc.sh

@@ -15,7 +15,6 @@ export BUILDER_COMPRESS=true
 # which makes rustup very sad
 rustc --version > /dev/null
 
-docserver-builder -i ./embassy-stm32 -o webroot/crates/embassy-stm32/git.zup
 docserver-builder -i ./embassy-boot/boot -o webroot/crates/embassy-boot/git.zup
 docserver-builder -i ./embassy-boot/nrf -o webroot/crates/embassy-boot-nrf/git.zup
 docserver-builder -i ./embassy-boot/rp -o webroot/crates/embassy-boot-rp/git.zup
@@ -36,11 +35,21 @@ docserver-builder -i ./embassy-usb-driver -o webroot/crates/embassy-usb-driver/g
 docserver-builder -i ./embassy-usb-logger -o webroot/crates/embassy-usb-logger/git.zup
 docserver-builder -i ./cyw43 -o webroot/crates/cyw43/git.zup
 docserver-builder -i ./cyw43-pio -o webroot/crates/cyw43-pio/git.zup
-docserver-builder -i ./embassy-net-w5500 -o webroot/crates/embassy-net-w5500/git.zup
+docserver-builder -i ./embassy-net-wiznet -o webroot/crates/embassy-net-wiznet/git.zup
+docserver-builder -i ./embassy-net-enc28j60 -o webroot/crates/embassy-net-enc28j60/git.zup
 docserver-builder -i ./embassy-net-esp-hosted -o webroot/crates/embassy-net-esp-hosted/git.zup
 docserver-builder -i ./embassy-stm32-wpan -o webroot/crates/embassy-stm32-wpan/git.zup --output-static webroot/static
+docserver-builder -i ./embassy-net-adin1110 -o webroot/crates/embassy-net-adin1110/git.zup
 
 export KUBECONFIG=/ci/secrets/kubeconfig.yml
 POD=$(kubectl -n embassy get po -l app=docserver -o jsonpath={.items[0].metadata.name})
 kubectl cp webroot/crates $POD:/data
 kubectl cp webroot/static $POD:/data
+
+# build and upload stm32 last
+# so that it doesn't prevent other crates from getting docs updates when it breaks.
+rm -rf webroot
+docserver-builder -i ./embassy-stm32 -o webroot/crates/embassy-stm32/git.zup
+
+POD=$(kubectl -n embassy get po -l app=docserver -o jsonpath={.items[0].metadata.name})
+kubectl cp webroot/crates $POD:/data

.github/ci/test.sh

@@ -28,3 +28,5 @@ cargo test --manifest-path ./embassy-rp/Cargo.toml --no-default-features --featu
 cargo test --manifest-path ./embassy-stm32/Cargo.toml --no-default-features --features nightly,stm32f429vg,exti,time-driver-any,exti
 cargo test --manifest-path ./embassy-stm32/Cargo.toml --no-default-features --features nightly,stm32f732ze,exti,time-driver-any,exti
 cargo test --manifest-path ./embassy-stm32/Cargo.toml --no-default-features --features nightly,stm32f769ni,exti,time-driver-any,exti
+
+cargo test --manifest-path ./embassy-net-adin1110/Cargo.toml

.vscode/settings.json

@@ -6,16 +6,21 @@
   "rust-analyzer.check.allTargets": false,
   "rust-analyzer.check.noDefaultFeatures": true,
   "rust-analyzer.cargo.noDefaultFeatures": true,
-  "rust-analyzer.cargo.target": "thumbv7m-none-eabi",
+  "rust-analyzer.showUnlinkedFileNotification": false,
+  // uncomment the target of your chip.
+  //"rust-analyzer.cargo.target": "thumbv6m-none-eabi",
+  //"rust-analyzer.cargo.target": "thumbv7m-none-eabi",
+  "rust-analyzer.cargo.target": "thumbv7em-none-eabi",
   //"rust-analyzer.cargo.target": "thumbv8m.main-none-eabihf",
   "rust-analyzer.cargo.features": [
-    ///"nightly",
+    // Uncomment if the example has a "nightly" feature.
+    "nightly",
   ],
   "rust-analyzer.linkedProjects": [
-    // Declare for the target you wish to develop
+    // Uncomment ONE line for the chip you want to work on.
-    // "embassy-executor/Cargo.toml",
+    // This makes rust-analyzer work on the example crate and all its dependencies.
-    // "embassy-sync/Cargo.toml",
+    "examples/nrf52840/Cargo.toml",
-    "examples/stm32wl/Cargo.toml",
+    // "examples/nrf52840-rtic/Cargo.toml",
     // "examples/nrf5340/Cargo.toml",
     // "examples/nrf-rtos-trace/Cargo.toml",
     // "examples/rp/Cargo.toml",
@@ -41,5 +46,4 @@
     // "examples/stm32wl/Cargo.toml",
     // "examples/wasm/Cargo.toml",
   ],
-  "rust-analyzer.showUnlinkedFileNotification": false,
 }

ci.sh

@@ -3,7 +3,7 @@
 set -euo pipefail
 
 export RUSTFLAGS=-Dwarnings
-export DEFMT_LOG=trace,embassy_net_esp_hosted=debug,cyw43=info,cyw43_pio=info,smoltcp=info
+export DEFMT_LOG=trace,embassy_hal_internal=debug,embassy_net_esp_hosted=debug,cyw43=info,cyw43_pio=info,smoltcp=info
 
 TARGET=$(rustc -vV | sed -n 's|host: ||p')
 
@@ -81,6 +81,7 @@ cargo batch  \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features nightly,stm32l041f6,defmt,exti,time-driver-any,unstable-traits \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32l151cb-a,defmt,exti,time-driver-any,unstable-traits \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f398ve,defmt,exti,time-driver-any,unstable-traits \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f378cc,defmt,exti,time-driver-any,unstable-traits \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features nightly,stm32g0c1ve,defmt,exti,time-driver-any,unstable-traits \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f217zg,defmt,exti,time-driver-any,unstable-traits \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features nightly,stm32l552ze,defmt,exti,time-driver-any,unstable-traits \

cyw43/Cargo.toml

@@ -24,7 +24,7 @@ cortex-m = "0.7.6"
 cortex-m-rt = "0.7.0"
 futures = { version = "0.3.17", default-features = false, features = ["async-await", "cfg-target-has-atomic", "unstable"] }
 
-embedded-hal-1 = { package = "embedded-hal", version = "1.0.0-alpha.11" }
+embedded-hal-1 = { package = "embedded-hal", version = "1.0.0-rc.1" }
 num_enum = { version = "0.5.7", default-features = false }
 
 [package.metadata.embassy_docs]

cyw43/src/bus.rs

@@ -102,7 +102,7 @@ where
         cmd_buf[0] = cmd;
         cmd_buf[1..][..buf.len()].copy_from_slice(buf);
 
-        self.status = self.spi.cmd_write(&cmd_buf).await;
+        self.status = self.spi.cmd_write(&cmd_buf[..buf.len() + 1]).await;
     }
 
     #[allow(unused)]

docs/modules/ROOT/examples/basic/Cargo.toml

@@ -6,7 +6,7 @@ version = "0.1.0"
 license = "MIT OR Apache-2.0"
 
 [dependencies]
-embassy-executor = { version = "0.2.0", path = "../../../../../embassy-executor", features = ["defmt", "nightly", "integrated-timers", "arch-cortex-m", "executor-thread"] }
+embassy-executor = { version = "0.3.0", path = "../../../../../embassy-executor", features = ["defmt", "nightly", "integrated-timers", "arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.1.0", path = "../../../../../embassy-time", features = ["defmt", "nightly"] }
 embassy-nrf = { version = "0.1.0", path = "../../../../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "nightly"] }
 

docs/modules/ROOT/examples/layer-by-layer/blinky-async/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 cortex-m = "0.7"
 cortex-m-rt = "0.7"
 embassy-stm32 = { version = "0.1.0", features = ["stm32l475vg", "memory-x", "exti"]  }
-embassy-executor = { version = "0.2.0", features = ["nightly", "arch-cortex-m", "executor-thread"] }
+embassy-executor = { version = "0.3.0", features = ["nightly", "arch-cortex-m", "executor-thread"] }
 
 defmt = "0.3.0"
 defmt-rtt = "0.3.0"

embassy-boot/nrf/src/lib.rs

@@ -14,28 +14,17 @@ use embassy_nrf::wdt;
 use embedded_storage::nor_flash::{ErrorType, NorFlash, ReadNorFlash};
 
 /// A bootloader for nRF devices.
-pub struct BootLoader<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize = PAGE_SIZE> {
+pub struct BootLoader<const BUFFER_SIZE: usize = PAGE_SIZE>;
-    boot: embassy_boot::BootLoader<ACTIVE, DFU, STATE>,
-    aligned_buf: AlignedBuffer<BUFFER_SIZE>,
-}
 
-impl<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize>
+impl<const BUFFER_SIZE: usize> BootLoader<BUFFER_SIZE> {
-    BootLoader<ACTIVE, DFU, STATE, BUFFER_SIZE>
+    /// Inspect the bootloader state and perform actions required before booting, such as swapping firmware.
-{
+    pub fn prepare<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash>(
-    /// Create a new bootloader instance using the supplied partitions for active, dfu and state.
+        config: BootLoaderConfig<ACTIVE, DFU, STATE>,
-    pub fn new(config: BootLoaderConfig<ACTIVE, DFU, STATE>) -> Self {
+    ) -> Self {
-        Self {
+        let mut aligned_buf = AlignedBuffer([0; BUFFER_SIZE]);
-            boot: embassy_boot::BootLoader::new(config),
+        let mut boot = embassy_boot::BootLoader::new(config);
-            aligned_buf: AlignedBuffer([0; BUFFER_SIZE]),
+        boot.prepare_boot(&mut aligned_buf.0).expect("Boot prepare error");
-        }
+        Self
-    }
-
-    /// Inspect the bootloader state and perform actions required before booting, such as swapping
-    /// firmware.
-    pub fn prepare(&mut self) {
-        self.boot
-            .prepare_boot(&mut self.aligned_buf.0)
-            .expect("Boot prepare error");
     }
 
     /// Boots the application without softdevice mechanisms.
@@ -45,8 +34,6 @@ impl<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize>
     /// This modifies the stack pointer and reset vector and will run code placed in the active partition.
     #[cfg(not(feature = "softdevice"))]
     pub unsafe fn load(self, start: u32) -> ! {
-        core::mem::drop(self.boot);
-
         let mut p = cortex_m::Peripherals::steal();
         p.SCB.invalidate_icache();
         p.SCB.vtor.write(start);
@@ -59,7 +46,7 @@ impl<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize>
     ///
     /// This modifies the stack pointer and reset vector and will run code placed in the active partition.
     #[cfg(feature = "softdevice")]
-    pub unsafe fn load(&mut self, _app: u32) -> ! {
+    pub unsafe fn load(self, _app: u32) -> ! {
         use nrf_softdevice_mbr as mbr;
         const NRF_SUCCESS: u32 = 0;
 

embassy-boot/rp/src/lib.rs

@@ -15,28 +15,17 @@ use embassy_time::Duration;
 use embedded_storage::nor_flash::{ErrorType, NorFlash, ReadNorFlash};
 
 /// A bootloader for RP2040 devices.
-pub struct BootLoader<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize = ERASE_SIZE> {
+pub struct BootLoader<const BUFFER_SIZE: usize = ERASE_SIZE>;
-    boot: embassy_boot::BootLoader<ACTIVE, DFU, STATE>,
-    aligned_buf: AlignedBuffer<BUFFER_SIZE>,
-}
 
-impl<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize>
+impl<const BUFFER_SIZE: usize> BootLoader<BUFFER_SIZE> {
-    BootLoader<ACTIVE, DFU, STATE, BUFFER_SIZE>
+    /// Inspect the bootloader state and perform actions required before booting, such as swapping firmware
-{
+    pub fn prepare<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash>(
-    /// Create a new bootloader instance using the supplied partitions for active, dfu and state.
+        config: BootLoaderConfig<ACTIVE, DFU, STATE>,
-    pub fn new(config: BootLoaderConfig<ACTIVE, DFU, STATE>) -> Self {
+    ) -> Self {
-        Self {
+        let mut aligned_buf = AlignedBuffer([0; BUFFER_SIZE]);
-            boot: embassy_boot::BootLoader::new(config),
+        let mut boot = embassy_boot::BootLoader::new(config);
-            aligned_buf: AlignedBuffer([0; BUFFER_SIZE]),
+        boot.prepare_boot(aligned_buf.as_mut()).expect("Boot prepare error");
-        }
+        Self
-    }
-
-    /// Inspect the bootloader state and perform actions required before booting, such as swapping
-    /// firmware.
-    pub fn prepare(&mut self) {
-        self.boot
-            .prepare_boot(self.aligned_buf.as_mut())
-            .expect("Boot prepare error");
     }
 
     /// Boots the application.
@@ -45,8 +34,6 @@ impl<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize>
     ///
     /// This modifies the stack pointer and reset vector and will run code placed in the active partition.
     pub unsafe fn load(self, start: u32) -> ! {
-        core::mem::drop(self.boot);
-
         trace!("Loading app at 0x{:x}", start);
         #[allow(unused_mut)]
         let mut p = cortex_m::Peripherals::steal();
@@ -67,7 +54,7 @@ pub struct WatchdogFlash<'d, const SIZE: usize> {
 impl<'d, const SIZE: usize> WatchdogFlash<'d, SIZE> {
     /// Start a new watchdog with a given flash and watchdog peripheral and a timeout
     pub fn start(flash: FLASH, watchdog: WATCHDOG, timeout: Duration) -> Self {
-        let flash = Flash::<_, Blocking, SIZE>::new(flash);
+        let flash = Flash::<_, Blocking, SIZE>::new_blocking(flash);
         let mut watchdog = Watchdog::new(watchdog);
         watchdog.start(timeout);
         Self { flash, watchdog }
@@ -84,11 +71,11 @@ impl<'d, const SIZE: usize> NorFlash for WatchdogFlash<'d, SIZE> {
 
     fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
         self.watchdog.feed();
-        self.flash.erase(from, to)
+        self.flash.blocking_erase(from, to)
     }
     fn write(&mut self, offset: u32, data: &[u8]) -> Result<(), Self::Error> {
         self.watchdog.feed();
-        self.flash.write(offset, data)
+        self.flash.blocking_write(offset, data)
     }
 }
 
@@ -96,7 +83,7 @@ impl<'d, const SIZE: usize> ReadNorFlash for WatchdogFlash<'d, SIZE> {
     const READ_SIZE: usize = <Flash<'d, FLASH, Blocking, SIZE> as ReadNorFlash>::READ_SIZE;
     fn read(&mut self, offset: u32, data: &mut [u8]) -> Result<(), Self::Error> {
         self.watchdog.feed();
-        self.flash.read(offset, data)
+        self.flash.blocking_read(offset, data)
     }
     fn capacity(&self) -> usize {
         self.flash.capacity()

embassy-boot/stm32/src/lib.rs

@@ -11,28 +11,17 @@ pub use embassy_boot::{FirmwareState, FirmwareUpdater};
 use embedded_storage::nor_flash::NorFlash;
 
 /// A bootloader for STM32 devices.
-pub struct BootLoader<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize> {
+pub struct BootLoader;
-    boot: embassy_boot::BootLoader<ACTIVE, DFU, STATE>,
-    aligned_buf: AlignedBuffer<BUFFER_SIZE>,
-}
 
-impl<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize>
+impl BootLoader {
-    BootLoader<ACTIVE, DFU, STATE, BUFFER_SIZE>
+    /// Inspect the bootloader state and perform actions required before booting, such as swapping firmware
-{
+    pub fn prepare<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize>(
-    /// Create a new bootloader instance using the supplied partitions for active, dfu and state.
+        config: BootLoaderConfig<ACTIVE, DFU, STATE>,
-    pub fn new(config: BootLoaderConfig<ACTIVE, DFU, STATE>) -> Self {
+    ) -> Self {
-        Self {
+        let mut aligned_buf = AlignedBuffer([0; BUFFER_SIZE]);
-            boot: embassy_boot::BootLoader::new(config),
+        let mut boot = embassy_boot::BootLoader::new(config);
-            aligned_buf: AlignedBuffer([0; BUFFER_SIZE]),
+        boot.prepare_boot(aligned_buf.as_mut()).expect("Boot prepare error");
-        }
+        Self
-    }
-
-    /// Inspect the bootloader state and perform actions required before booting, such as swapping
-    /// firmware.
-    pub fn prepare(&mut self) {
-        self.boot
-            .prepare_boot(self.aligned_buf.as_mut())
-            .expect("Boot prepare error");
     }
 
     /// Boots the application.
@@ -41,8 +30,6 @@ impl<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize>
     ///
     /// This modifies the stack pointer and reset vector and will run code placed in the active partition.
     pub unsafe fn load(self, start: u32) -> ! {
-        core::mem::drop(self.boot);
-
         trace!("Loading app at 0x{:x}", start);
         #[allow(unused_mut)]
         let mut p = cortex_m::Peripherals::steal();

embassy-embedded-hal/Cargo.toml

@@ -25,8 +25,8 @@ embassy-time = { version = "0.1.2", path = "../embassy-time", optional = true }
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = [
     "unproven",
 ] }
-embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.11" }
+embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }
-embedded-hal-async = { version = "=0.2.0-alpha.2", optional = true }
+embedded-hal-async = { version = "=1.0.0-rc.1", optional = true }
 embedded-storage = "0.3.0"
 embedded-storage-async = { version = "0.4.0", optional = true }
 nb = "1.0.0"

embassy-embedded-hal/src/adapter/blocking_async.rs

@@ -1,4 +1,4 @@
-use embedded_hal_02::{blocking, serial};
+use embedded_hal_02::blocking;
 
 /// Wrapper that implements async traits using blocking implementations.
 ///
@@ -103,15 +103,6 @@ where
     }
 }
 
-// Uart implementatinos
-impl<T, E> embedded_hal_1::serial::ErrorType for BlockingAsync<T>
-where
-    T: serial::Read<u8, Error = E>,
-    E: embedded_hal_1::serial::Error + 'static,
-{
-    type Error = E;
-}
-
 /// NOR flash wrapper
 use embedded_storage::nor_flash::{ErrorType, NorFlash, ReadNorFlash};
 use embedded_storage_async::nor_flash::{NorFlash as AsyncNorFlash, ReadNorFlash as AsyncReadNorFlash};

embassy-executor/CHANGELOG.md

@@ -5,6 +5,13 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## 0.3.0 - 2023-08-25
+
+- Replaced Pender. Implementations now must define an extern function called `__pender`.
+- Made `raw::AvailableTask` public
+- Made `SpawnToken::new_failed` public
+- You can now use arbitrary expressions to specify `#[task(pool_size = X)]`
+
 ## 0.2.1 - 2023-08-10
 
 - Avoid calling `pend()` when waking expired timers

embassy-executor/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "embassy-executor"
-version = "0.2.1"
+version = "0.3.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "async/await executor designed for embedded usage"
@@ -14,7 +14,7 @@ categories = [
 [package.metadata.embassy_docs]
 src_base = "https://github.com/embassy-rs/embassy/blob/embassy-executor-v$VERSION/embassy-executor/src/"
 src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-executor/src/"
-features = ["nightly", "defmt", "pender-callback"]
+features = ["nightly", "defmt"]
 flavors = [
     { name = "std",             target = "x86_64-unknown-linux-gnu",     features = ["arch-std", "executor-thread"] },
     { name = "wasm",            target = "wasm32-unknown-unknown",       features = ["arch-wasm", "executor-thread"] },
@@ -25,7 +25,7 @@ flavors = [
 [package.metadata.docs.rs]
 default-target = "thumbv7em-none-eabi"
 targets = ["thumbv7em-none-eabi"]
-features = ["nightly", "defmt", "pender-callback", "arch-cortex-m", "executor-thread", "executor-interrupt"]
+features = ["nightly", "defmt", "arch-cortex-m", "executor-thread", "executor-interrupt"]
 
 [features]
 
@@ -37,9 +37,6 @@ arch-xtensa = ["_arch"]
 arch-riscv32 = ["_arch"]
 arch-wasm = ["_arch", "dep:wasm-bindgen", "dep:js-sys"]
 
-# Enable creating a `Pender` from an arbitrary function pointer callback.
-pender-callback = []
-
 # Enable the thread-mode executor (using WFE/SEV in Cortex-M, WFI in other embedded archs)
 executor-thread = []
 # Enable the interrupt-mode executor (available in Cortex-M only)
@@ -61,7 +58,7 @@ log = { version = "0.4.14", optional = true }
 rtos-trace = { version = "0.1.2", optional = true }
 
 futures-util = { version = "0.3.17", default-features = false }
-embassy-macros = { version = "0.2.0", path = "../embassy-macros" }
+embassy-macros = { version = "0.2.1", path = "../embassy-macros" }
 embassy-time = { version = "0.1.2", path = "../embassy-time", optional = true}
 atomic-polyfill = "1.0.1"
 critical-section = "1.1"

embassy-executor/src/arch/cortex_m.rs

@@ -1,3 +1,49 @@
+const THREAD_PENDER: usize = usize::MAX;
+
+#[export_name = "__pender"]
+#[cfg(any(feature = "executor-thread", feature = "executor-interrupt"))]
+fn __pender(context: *mut ()) {
+    unsafe {
+        // Safety: `context` is either `usize::MAX` created by `Executor::run`, or a valid interrupt
+        // request number given to `InterruptExecutor::start`.
+
+        let context = context as usize;
+
+        #[cfg(feature = "executor-thread")]
+        // Try to make Rust optimize the branching away if we only use thread mode.
+        if !cfg!(feature = "executor-interrupt") || context == THREAD_PENDER {
+            core::arch::asm!("sev");
+            return;
+        }
+
+        #[cfg(feature = "executor-interrupt")]
+        {
+            use cortex_m::interrupt::InterruptNumber;
+            use cortex_m::peripheral::NVIC;
+
+            #[derive(Clone, Copy)]
+            struct Irq(u16);
+            unsafe impl InterruptNumber for Irq {
+                fn number(self) -> u16 {
+                    self.0
+                }
+            }
+
+            let irq = Irq(context as u16);
+
+            // STIR is faster, but is only available in v7 and higher.
+            #[cfg(not(armv6m))]
+            {
+                let mut nvic: NVIC = core::mem::transmute(());
+                nvic.request(irq);
+            }
+
+            #[cfg(armv6m)]
+            NVIC::pend(irq);
+        }
+    }
+}
+
 #[cfg(feature = "executor-thread")]
 pub use thread::*;
 #[cfg(feature = "executor-thread")]
@@ -8,18 +54,9 @@ mod thread {
     #[cfg(feature = "nightly")]
     pub use embassy_macros::main_cortex_m as main;
 
-    use crate::raw::{Pender, PenderInner};
+    use crate::arch::THREAD_PENDER;
     use crate::{raw, Spawner};
 
-    #[derive(Copy, Clone)]
-    pub(crate) struct ThreadPender;
-
-    impl ThreadPender {
-        pub(crate) fn pend(self) {
-            unsafe { core::arch::asm!("sev") }
-        }
-    }
-
     /// Thread mode executor, using WFE/SEV.
     ///
     /// This is the simplest and most common kind of executor. It runs on
@@ -39,7 +76,7 @@ mod thread {
         /// Create a new Executor.
         pub fn new() -> Self {
             Self {
-                inner: raw::Executor::new(Pender(PenderInner::Thread(ThreadPender))),
+                inner: raw::Executor::new(THREAD_PENDER as *mut ()),
                 not_send: PhantomData,
             }
         }
@@ -86,30 +123,7 @@ mod interrupt {
     use cortex_m::interrupt::InterruptNumber;
     use cortex_m::peripheral::NVIC;
 
-    use crate::raw::{self, Pender, PenderInner};
+    use crate::raw;
-
-    #[derive(Clone, Copy)]
-    pub(crate) struct InterruptPender(u16);
-
-    impl InterruptPender {
-        pub(crate) fn pend(self) {
-            // STIR is faster, but is only available in v7 and higher.
-            #[cfg(not(armv6m))]
-            {
-                let mut nvic: cortex_m::peripheral::NVIC = unsafe { core::mem::transmute(()) };
-                nvic.request(self);
-            }
-
-            #[cfg(armv6m)]
-            cortex_m::peripheral::NVIC::pend(self);
-        }
-    }
-
-    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptPender {
-        fn number(self) -> u16 {
-            self.0
-        }
-    }
 
     /// Interrupt mode executor.
     ///
@@ -194,9 +208,7 @@ mod interrupt {
             unsafe {
                 (&mut *self.executor.get())
                     .as_mut_ptr()
-                    .write(raw::Executor::new(Pender(PenderInner::Interrupt(InterruptPender(
+                    .write(raw::Executor::new(irq.number() as *mut ()))
-                        irq.number(),
-                    )))))
             }
 
             let executor = unsafe { (&*self.executor.get()).assume_init_ref() };

embassy-executor/src/arch/riscv32.rs

@@ -11,22 +11,16 @@ mod thread {
     #[cfg(feature = "nightly")]
     pub use embassy_macros::main_riscv as main;
 
-    use crate::raw::{Pender, PenderInner};
     use crate::{raw, Spawner};
 
-    #[derive(Copy, Clone)]
-    pub(crate) struct ThreadPender;
-
-    impl ThreadPender {
-        #[allow(unused)]
-        pub(crate) fn pend(self) {
-            SIGNAL_WORK_THREAD_MODE.store(true, core::sync::atomic::Ordering::SeqCst);
-        }
-    }
-
     /// global atomic used to keep track of whether there is work to do since sev() is not available on RISCV
     static SIGNAL_WORK_THREAD_MODE: AtomicBool = AtomicBool::new(false);
 
+    #[export_name = "__pender"]
+    fn __pender(_context: *mut ()) {
+        SIGNAL_WORK_THREAD_MODE.store(true, Ordering::SeqCst);
+    }
+
     /// RISCV32 Executor
     pub struct Executor {
         inner: raw::Executor,
@@ -37,7 +31,7 @@ mod thread {
         /// Create a new Executor.
         pub fn new() -> Self {
             Self {
-                inner: raw::Executor::new(Pender(PenderInner::Thread(ThreadPender))),
+                inner: raw::Executor::new(core::ptr::null_mut()),
                 not_send: PhantomData,
             }
         }

embassy-executor/src/arch/std.rs

@@ -11,17 +11,12 @@ mod thread {
     #[cfg(feature = "nightly")]
     pub use embassy_macros::main_std as main;
 
-    use crate::raw::{Pender, PenderInner};
     use crate::{raw, Spawner};
 
-    #[derive(Copy, Clone)]
+    #[export_name = "__pender"]
-    pub(crate) struct ThreadPender(&'static Signaler);
+    fn __pender(context: *mut ()) {
-
+        let signaler: &'static Signaler = unsafe { std::mem::transmute(context) };
-    impl ThreadPender {
+        signaler.signal()
-        #[allow(unused)]
-        pub(crate) fn pend(self) {
-            self.0.signal()
-        }
     }
 
     /// Single-threaded std-based executor.
@@ -34,9 +29,9 @@ mod thread {
     impl Executor {
         /// Create a new Executor.
         pub fn new() -> Self {
-            let signaler = &*Box::leak(Box::new(Signaler::new()));
+            let signaler = Box::leak(Box::new(Signaler::new()));
             Self {
-                inner: raw::Executor::new(Pender(PenderInner::Thread(ThreadPender(signaler)))),
+                inner: raw::Executor::new(signaler as *mut Signaler as *mut ()),
                 not_send: PhantomData,
                 signaler,
             }

embassy-executor/src/arch/wasm.rs

@@ -14,14 +14,12 @@ mod thread {
     use wasm_bindgen::prelude::*;
 
     use crate::raw::util::UninitCell;
-    use crate::raw::{Pender, PenderInner};
     use crate::{raw, Spawner};
 
-    /// WASM executor, wasm_bindgen to schedule tasks on the JS event loop.
+    #[export_name = "__pender"]
-    pub struct Executor {
+    fn __pender(context: *mut ()) {
-        inner: raw::Executor,
+        let signaler: &'static WasmContext = unsafe { std::mem::transmute(context) };
-        ctx: &'static WasmContext,
+        let _ = signaler.promise.then(unsafe { signaler.closure.as_mut() });
-        not_send: PhantomData<*mut ()>,
     }
 
     pub(crate) struct WasmContext {
@@ -29,16 +27,6 @@ mod thread {
         closure: UninitCell<Closure<dyn FnMut(JsValue)>>,
     }
 
-    #[derive(Copy, Clone)]
-    pub(crate) struct ThreadPender(&'static WasmContext);
-
-    impl ThreadPender {
-        #[allow(unused)]
-        pub(crate) fn pend(self) {
-            let _ = self.0.promise.then(unsafe { self.0.closure.as_mut() });
-        }
-    }
-
     impl WasmContext {
         pub fn new() -> Self {
             Self {
@@ -48,14 +36,21 @@ mod thread {
         }
     }
 
+    /// WASM executor, wasm_bindgen to schedule tasks on the JS event loop.
+    pub struct Executor {
+        inner: raw::Executor,
+        ctx: &'static WasmContext,
+        not_send: PhantomData<*mut ()>,
+    }
+
     impl Executor {
         /// Create a new Executor.
         pub fn new() -> Self {
-            let ctx = &*Box::leak(Box::new(WasmContext::new()));
+            let ctx = Box::leak(Box::new(WasmContext::new()));
             Self {
-                inner: raw::Executor::new(Pender(PenderInner::Thread(ThreadPender(ctx)))),
+                inner: raw::Executor::new(ctx as *mut WasmContext as *mut ()),
-                not_send: PhantomData,
                 ctx,
+                not_send: PhantomData,
             }
         }
 

embassy-executor/src/arch/xtensa.rs

@@ -8,22 +8,16 @@ mod thread {
     use core::marker::PhantomData;
     use core::sync::atomic::{AtomicBool, Ordering};
 
-    use crate::raw::{Pender, PenderInner};
     use crate::{raw, Spawner};
 
-    #[derive(Copy, Clone)]
-    pub(crate) struct ThreadPender;
-
-    impl ThreadPender {
-        #[allow(unused)]
-        pub(crate) fn pend(self) {
-            SIGNAL_WORK_THREAD_MODE.store(true, core::sync::atomic::Ordering::SeqCst);
-        }
-    }
-
     /// global atomic used to keep track of whether there is work to do since sev() is not available on Xtensa
     static SIGNAL_WORK_THREAD_MODE: AtomicBool = AtomicBool::new(false);
 
+    #[export_name = "__pender"]
+    fn __pender(_context: *mut ()) {
+        SIGNAL_WORK_THREAD_MODE.store(true, Ordering::SeqCst);
+    }
+
     /// Xtensa Executor
     pub struct Executor {
         inner: raw::Executor,
@@ -34,7 +28,7 @@ mod thread {
         /// Create a new Executor.
         pub fn new() -> Self {
             Self {
-                inner: raw::Executor::new(Pender(PenderInner::Thread(ThreadPender))),
+                inner: raw::Executor::new(core::ptr::null_mut()),
                 not_send: PhantomData,
             }
         }

embassy-executor/src/raw/mod.rs

@@ -147,10 +147,7 @@ impl<F: Future + 'static> TaskStorage<F> {
     pub fn spawn(&'static self, future: impl FnOnce() -> F) -> SpawnToken<impl Sized> {
         let task = AvailableTask::claim(self);
         match task {
-            Some(task) => {
+            Some(task) => task.initialize(future),
-                let task = task.initialize(future);
-                unsafe { SpawnToken::<F>::new(task) }
-            }
             None => SpawnToken::new_failed(),
         }
     }
@@ -186,12 +183,16 @@ impl<F: Future + 'static> TaskStorage<F> {
     }
 }
 
-struct AvailableTask<F: Future + 'static> {
+/// An uninitialized [`TaskStorage`].
+pub struct AvailableTask<F: Future + 'static> {
     task: &'static TaskStorage<F>,
 }
 
 impl<F: Future + 'static> AvailableTask<F> {
-    fn claim(task: &'static TaskStorage<F>) -> Option<Self> {
+    /// Try to claim a [`TaskStorage`].
+    ///
+    /// This function returns `None` if a task has already been spawned and has not finished running.
+    pub fn claim(task: &'static TaskStorage<F>) -> Option<Self> {
         task.raw
             .state
             .compare_exchange(0, STATE_SPAWNED | STATE_RUN_QUEUED, Ordering::AcqRel, Ordering::Acquire)
@@ -199,61 +200,30 @@ impl<F: Future + 'static> AvailableTask<F> {
             .map(|_| Self { task })
     }
 
-    fn initialize(self, future: impl FnOnce() -> F) -> TaskRef {
+    fn initialize_impl<S>(self, future: impl FnOnce() -> F) -> SpawnToken<S> {
         unsafe {
             self.task.raw.poll_fn.set(Some(TaskStorage::<F>::poll));
             self.task.future.write(future());
-        }
+
-        TaskRef::new(self.task)
+            let task = TaskRef::new(self.task);
+
+            SpawnToken::new(task)
         }
     }
 
-/// Raw storage that can hold up to N tasks of the same type.
+    /// Initialize the [`TaskStorage`] to run the given future.
-///
+    pub fn initialize(self, future: impl FnOnce() -> F) -> SpawnToken<F> {
-/// This is essentially a `[TaskStorage<F>; N]`.
+        self.initialize_impl::<F>(future)
-pub struct TaskPool<F: Future + 'static, const N: usize> {
-    pool: [TaskStorage<F>; N],
     }
 
-impl<F: Future + 'static, const N: usize> TaskPool<F, N> {
+    /// Initialize the [`TaskStorage`] to run the given future.
-    /// Create a new TaskPool, with all tasks in non-spawned state.
-    pub const fn new() -> Self {
-        Self {
-            pool: [TaskStorage::NEW; N],
-        }
-    }
-
-    /// Try to spawn a task in the pool.
     ///
-    /// See [`TaskStorage::spawn()`] for details.
+    /// # Safety
     ///
-    /// This will loop over the pool and spawn the task in the first storage that
+    /// `future` must be a closure of the form `move || my_async_fn(args)`, where `my_async_fn`
-    /// is currently free. If none is free, a "poisoned" SpawnToken is returned,
-    /// which will cause [`Spawner::spawn()`](super::Spawner::spawn) to return the error.
-    pub fn spawn(&'static self, future: impl FnOnce() -> F) -> SpawnToken<impl Sized> {
-        let task = self.pool.iter().find_map(AvailableTask::claim);
-        match task {
-            Some(task) => {
-                let task = task.initialize(future);
-                unsafe { SpawnToken::<F>::new(task) }
-            }
-            None => SpawnToken::new_failed(),
-        }
-    }
-
-    /// Like spawn(), but allows the task to be send-spawned if the args are Send even if
-    /// the future is !Send.
-    ///
-    /// Not covered by semver guarantees. DO NOT call this directly. Intended to be used
-    /// by the Embassy macros ONLY.
-    ///
-    /// SAFETY: `future` must be a closure of the form `move || my_async_fn(args)`, where `my_async_fn`
     /// is an `async fn`, NOT a hand-written `Future`.
     #[doc(hidden)]
-    pub unsafe fn _spawn_async_fn<FutFn>(&'static self, future: FutFn) -> SpawnToken<impl Sized>
+    pub unsafe fn __initialize_async_fn<FutFn>(self, future: impl FnOnce() -> F) -> SpawnToken<FutFn> {
-    where
-        FutFn: FnOnce() -> F,
-    {
         // When send-spawning a task, we construct the future in this thread, and effectively
         // "send" it to the executor thread by enqueuing it in its queue. Therefore, in theory,
         // send-spawning should require the future `F` to be `Send`.
@@ -279,66 +249,73 @@ impl<F: Future + 'static, const N: usize> TaskPool<F, N> {
         //
         // This ONLY holds for `async fn` futures. The other `spawn` methods can be called directly
         // by the user, with arbitrary hand-implemented futures. This is why these return `SpawnToken<F>`.
-
+        self.initialize_impl::<FutFn>(future)
-        let task = self.pool.iter().find_map(AvailableTask::claim);
-        match task {
-            Some(task) => {
-                let task = task.initialize(future);
-                unsafe { SpawnToken::<FutFn>::new(task) }
     }
+}
+
+/// Raw storage that can hold up to N tasks of the same type.
+///
+/// This is essentially a `[TaskStorage<F>; N]`.
+pub struct TaskPool<F: Future + 'static, const N: usize> {
+    pool: [TaskStorage<F>; N],
+}
+
+impl<F: Future + 'static, const N: usize> TaskPool<F, N> {
+    /// Create a new TaskPool, with all tasks in non-spawned state.
+    pub const fn new() -> Self {
+        Self {
+            pool: [TaskStorage::NEW; N],
+        }
+    }
+
+    fn spawn_impl<T>(&'static self, future: impl FnOnce() -> F) -> SpawnToken<T> {
+        match self.pool.iter().find_map(AvailableTask::claim) {
+            Some(task) => task.initialize_impl::<T>(future),
             None => SpawnToken::new_failed(),
         }
     }
+
+    /// Try to spawn a task in the pool.
+    ///
+    /// See [`TaskStorage::spawn()`] for details.
+    ///
+    /// This will loop over the pool and spawn the task in the first storage that
+    /// is currently free. If none is free, a "poisoned" SpawnToken is returned,
+    /// which will cause [`Spawner::spawn()`](super::Spawner::spawn) to return the error.
+    pub fn spawn(&'static self, future: impl FnOnce() -> F) -> SpawnToken<impl Sized> {
+        self.spawn_impl::<F>(future)
+    }
+
+    /// Like spawn(), but allows the task to be send-spawned if the args are Send even if
+    /// the future is !Send.
+    ///
+    /// Not covered by semver guarantees. DO NOT call this directly. Intended to be used
+    /// by the Embassy macros ONLY.
+    ///
+    /// SAFETY: `future` must be a closure of the form `move || my_async_fn(args)`, where `my_async_fn`
+    /// is an `async fn`, NOT a hand-written `Future`.
+    #[doc(hidden)]
+    pub unsafe fn _spawn_async_fn<FutFn>(&'static self, future: FutFn) -> SpawnToken<impl Sized>
+    where
+        FutFn: FnOnce() -> F,
+    {
+        // See the comment in AvailableTask::__initialize_async_fn for explanation.
+        self.spawn_impl::<FutFn>(future)
+    }
 }
 
 #[derive(Clone, Copy)]
-pub(crate) enum PenderInner {
+pub(crate) struct Pender(*mut ());
-    #[cfg(feature = "executor-thread")]
-    Thread(crate::arch::ThreadPender),
-    #[cfg(feature = "executor-interrupt")]
-    Interrupt(crate::arch::InterruptPender),
-    #[cfg(feature = "pender-callback")]
-    Callback { func: fn(*mut ()), context: *mut () },
-}
 
-unsafe impl Send for PenderInner {}
+unsafe impl Send for Pender {}
-unsafe impl Sync for PenderInner {}
+unsafe impl Sync for Pender {}
-
-/// Platform/architecture-specific action executed when an executor has pending work.
-///
-/// When a task within an executor is woken, the `Pender` is called. This does a
-/// platform/architecture-specific action to signal there is pending work in the executor.
-/// When this happens, you must arrange for [`Executor::poll`] to be called.
-///
-/// You can think of it as a waker, but for the whole executor.
-pub struct Pender(pub(crate) PenderInner);
 
 impl Pender {
-    /// Create a `Pender` that will call an arbitrary function pointer.
+    pub(crate) fn pend(self) {
-    ///
+        extern "Rust" {
-    /// # Arguments
+            fn __pender(context: *mut ());
-    ///
-    /// - `func`: The function pointer to call.
-    /// - `context`: Opaque context pointer, that will be passed to the function pointer.
-    #[cfg(feature = "pender-callback")]
-    pub fn new_from_callback(func: fn(*mut ()), context: *mut ()) -> Self {
-        Self(PenderInner::Callback {
-            func,
-            context: context.into(),
-        })
-    }
-}
-
-impl Pender {
-    pub(crate) fn pend(&self) {
-        match self.0 {
-            #[cfg(feature = "executor-thread")]
-            PenderInner::Thread(x) => x.pend(),
-            #[cfg(feature = "executor-interrupt")]
-            PenderInner::Interrupt(x) => x.pend(),
-            #[cfg(feature = "pender-callback")]
-            PenderInner::Callback { func, context } => func(context),
         }
+        unsafe { __pender(self.0) };
     }
 }
 
@@ -472,15 +449,31 @@ impl SyncExecutor {
 ///
 /// - To get the executor to do work, call `poll()`. This will poll all queued tasks (all tasks
 ///   that "want to run").
-/// - You must supply a [`Pender`]. The executor will call it to notify you it has work
+/// - You must supply a pender function, as shown below. The executor will call it to notify you
-///   to do. You must arrange for `poll()` to be called as soon as possible.
+///   it has work to do. You must arrange for `poll()` to be called as soon as possible.
+/// - Enabling `arch-xx` features will define a pender function for you. This means that you
+///   are limited to using the executors provided to you by the architecture/platform
+///   implementation. If you need a different executor, you must not enable `arch-xx` features.
 ///
-/// The [`Pender`] can be called from *any* context: any thread, any interrupt priority
+/// The pender can be called from *any* context: any thread, any interrupt priority
 /// level, etc. It may be called synchronously from any `Executor` method call as well.
 /// You must deal with this correctly.
 ///
 /// In particular, you must NOT call `poll` directly from the pender callback, as this violates
 /// the requirement for `poll` to not be called reentrantly.
+///
+/// The pender function must be exported with the name `__pender` and have the following signature:
+///
+/// ```rust
+/// #[export_name = "__pender"]
+/// fn pender(context: *mut ()) {
+///    // schedule `poll()` to be called
+/// }
+/// ```
+///
+/// The `context` argument is a piece of arbitrary data the executor will pass to the pender.
+/// You can set the `context` when calling [`Executor::new()`]. You can use it to, for example,
+/// differentiate between executors, or to pass a pointer to a callback that should be called.
 #[repr(transparent)]
 pub struct Executor {
     pub(crate) inner: SyncExecutor,
@@ -495,12 +488,12 @@ impl Executor {
 
     /// Create a new executor.
     ///
-    /// When the executor has work to do, it will call the [`Pender`].
+    /// When the executor has work to do, it will call the pender function and pass `context` to it.
     ///
-    /// See [`Executor`] docs for details on `Pender`.
+    /// See [`Executor`] docs for details on the pender.
-    pub fn new(pender: Pender) -> Self {
+    pub fn new(context: *mut ()) -> Self {
         Self {
-            inner: SyncExecutor::new(pender),
+            inner: SyncExecutor::new(Pender(context)),
             _not_sync: PhantomData,
         }
     }
@@ -523,16 +516,16 @@ impl Executor {
     /// This loops over all tasks that are queued to be polled (i.e. they're
     /// freshly spawned or they've been woken). Other tasks are not polled.
     ///
-    /// You must call `poll` after receiving a call to the [`Pender`]. It is OK
+    /// You must call `poll` after receiving a call to the pender. It is OK
-    /// to call `poll` even when not requested by the `Pender`, but it wastes
+    /// to call `poll` even when not requested by the pender, but it wastes
     /// energy.
     ///
     /// # Safety
     ///
     /// You must NOT call `poll` reentrantly on the same executor.
     ///
-    /// In particular, note that `poll` may call the `Pender` synchronously. Therefore, you
+    /// In particular, note that `poll` may call the pender synchronously. Therefore, you
-    /// must NOT directly call `poll()` from the `Pender` callback. Instead, the callback has to
+    /// must NOT directly call `poll()` from the pender callback. Instead, the callback has to
     /// somehow schedule for `poll()` to be called later, at a time you know for sure there's
     /// no `poll()` already running.
     pub unsafe fn poll(&'static self) {

embassy-executor/src/spawner.rs

@@ -33,7 +33,8 @@ impl<S> SpawnToken<S> {
         }
     }
 
-    pub(crate) fn new_failed() -> Self {
+    /// Return a SpawnToken that represents a failed spawn.
+    pub fn new_failed() -> Self {
         Self {
             raw_task: None,
             phantom: PhantomData,

embassy-lora/Cargo.toml

@@ -23,9 +23,12 @@ log = { version = "0.4.14", optional = true }
 embassy-time = { version = "0.1.2", path = "../embassy-time", optional = true }
 embassy-sync = { version = "0.2.0", path = "../embassy-sync" }
 embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", default-features = false, optional = true }
-embedded-hal-async = { version = "=0.2.0-alpha.2" }
+embedded-hal-async = { version = "=1.0.0-rc.1" }
 embedded-hal = { version = "0.2", features = ["unproven"] }
 
 futures = { version = "0.3.17", default-features = false, features = [ "async-await" ] }
 lora-phy = { version = "1" }
 lorawan-device = { version = "0.10.0", default-features = false, features = ["async"], optional = true }
+
+[patch.crates-io]
+lora-phy = { git = "https://github.com/embassy-rs/lora-phy", rev = "1323eccc1c470d4259f95f4f315d1be830d572a3"}

embassy-macros/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "embassy-macros"
-version = "0.2.0"
+version = "0.2.1"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "macros for creating the entry point and tasks for embassy-executor"

embassy-net-adin1110/Cargo.toml

@@ -0,0 +1,41 @@
+[package]
+name = "embassy-net-adin1110"
+version = "0.1.0"
+description = "embassy-net driver for the ADIN1110 ethernet chip"
+keywords = ["embedded", "ADIN1110", "embassy-net", "embedded-hal-async", "ethernet", "async"]
+categories = ["embedded", "hardware-support", "no-std", "network-programming", "async"]
+license = "MIT OR Apache-2.0"
+edition = "2021"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+heapless = "0.7.16"
+defmt = { version = "0.3", optional = true }
+log = { version = "0.4.4", default-features = false, optional = true }
+embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }
+embedded-hal-async = { version = "=1.0.0-rc.1" }
+embedded-hal-bus = { version = "=0.1.0-rc.1", features = ["async"] }
+embassy-net-driver-channel = { version = "0.1.0", path = "../embassy-net-driver-channel" }
+embassy-time = { version = "0.1.0" }
+embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
+bitfield = "0.14.0"
+
+
+[dev-dependencies]
+# reenable when https://github.com/dbrgn/embedded-hal-mock/pull/86 is merged.
+#embedded-hal-mock = { git = "https://github.com/dbrgn/embedded-hal-mock", branch = "1-alpha", features = ["embedded-hal-async", "eh1"] }] }
+embedded-hal-mock = { git = "https://github.com/newAM/embedded-hal-mock", branch = "eh1-rc.1", features = ["embedded-hal-async", "eh1"] }
+crc = "3.0.1"
+env_logger = "0.10"
+critical-section = { version = "1.1.1", features = ["std"] }
+futures-test = "0.3.17"
+
+[features]
+default = [ ]
+defmt = [ "dep:defmt" ]
+
+[package.metadata.embassy_docs]
+src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-adin1110-v$VERSION/embassy-net-adin1110/src/"
+src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-adin1110/src/"
+target = "thumbv7em-none-eabi"

embassy-net-adin1110/README.md

@@ -0,0 +1,55 @@
+# SPE ADIN1110 `embassy-net` integration
+
+[`embassy-net`](https://crates.io/crates/embassy-net) integration for the `Analog ADIN1110` SPI SPE ethernet chips.
+
+## What is SPE or Single Pair Ethernet / 10 BASE-T1L
+
+SPE stands for Single Pair Ethernet. As the names implies, SPE uses differential signalling with 2 wires (a twisted-pair) in a cable as the physical medium.
+SPE is full-duplex - it can transmit and receive ethernet packets at the same time. SPE is still ethernet, only the physical layer is different.
+
+SPE also supports [`PoDL (Power over Data Line)`](https://www.ti.com/lit/an/snla395/snla395.pdf), power delivery from 0.5 up to 50 Watts, similar to [`PoE`](https://en.wikipedia.org/wiki/Power_over_Ethernet), but an additional hardware and handshake protocol are needed.
+
+SPE has many link speeds but only `10 BASE-T1L` is able to reach cable lengths up to 1000 meters in `2.4 Vpp` transmit amplitude.
+Currently in 2023, none of the standards are compatible with each other.
+Thus `10 BASE-T1L` won't work with a `10 BASE-T1S`, `100 BASE-T1` or any standard `x BASE-T`.
+
+In the industry SPE is also called [`APL (Advanced Physical Layer)`](https://www.ethernet-apl.org), and is based on the `10 BASE-T1L` standard.
+
+APL can be used in [`intrinsic safety applications/explosion hazardous areas`](https://en.wikipedia.org/wiki/Electrical_equipment_in_hazardous_areas) which has its own name and standard called [`2-WISE (2-wire intrinsically safe ethernet) IEC TS 60079-47:2021`](https://webstore.iec.ch/publication/64292).
+
+`10 BASE-T1L` and `ADIN1110` are designed to support intrinsic safety applications. The power supply energy is fixed and PDoL is not supported.
+
+## Supported SPI modes
+
+`ADIN1110` supports two SPI modes. `Generic` and [`OPEN Alliance 10BASE-T1x MAC-PHY serial interface`](https://opensig.org/download/document/OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdf)
+
+Both modes support with and without additional CRC.
+Currently only `Generic` SPI with or without CRC is supported.
+
+*NOTE:* SPI Mode is selected by the hardware pins `SPI_CFG0` and `SPI_CFG1`. Software can't detect nor change the mode.
+
+## Hardware
+
+- Tested on [`Analog Devices EVAL-ADIN1110EBZ`](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adin1110.html) with an `STM32L4S5QII3P`, see [`spe_adin1110_http_server`](../examples/stm32l4/src/bin/spe_adin1110_http_server.rs) dor an example.
+- [`SparkFun MicroMod Single Pair Ethernet Function Board`](https://www.sparkfun.com/products/19038) or [`SparkFun MicroMod Single Pair Ethernet Kit`](https://www.sparkfun.com/products/19628), supporting multiple microcontrollers. **Make sure to check if it's a microcontroller that is supported by Embassy!**
+
+## Other SPE chips
+
+* [`Analog ADIN2111`](https://www.analog.com/en/products/adin2111.html) 2 Port SPI version. Can work with this driver.
+* [`Analog ADIN1100`](https://www.analog.com/en/products/adin1100.html) RGMII version.
+
+## Testing
+
+ADIN1110 library can tested on the host with a mock SPI driver.
+
+$ `cargo test --target x86_64-unknown-linux-gnu`
+
+## License
+
+This work is licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.

embassy-net-adin1110/src/crc32.rs

@@ -0,0 +1,358 @@
+pub const CRC32R_LOOKUP_TABLE: [u32; 256] = [
+    0x0000_0000,
+    0x7707_3096,
+    0xEE0E_612C,
+    0x9909_51BA,
+    0x076D_C419,
+    0x706A_F48F,
+    0xE963_A535,
+    0x9E64_95A3,
+    0x0EDB_8832,
+    0x79DC_B8A4,
+    0xE0D5_E91E,
+    0x97D2_D988,
+    0x09B6_4C2B,
+    0x7EB1_7CBD,
+    0xE7B8_2D07,
+    0x90BF_1D91,
+    0x1DB7_1064,
+    0x6AB0_20F2,
+    0xF3B9_7148,
+    0x84BE_41DE,
+    0x1ADA_D47D,
+    0x6DDD_E4EB,
+    0xF4D4_B551,
+    0x83D3_85C7,
+    0x136C_9856,
+    0x646B_A8C0,
+    0xFD62_F97A,
+    0x8A65_C9EC,
+    0x1401_5C4F,
+    0x6306_6CD9,
+    0xFA0F_3D63,
+    0x8D08_0DF5,
+    0x3B6E_20C8,
+    0x4C69_105E,
+    0xD560_41E4,
+    0xA267_7172,
+    0x3C03_E4D1,
+    0x4B04_D447,
+    0xD20D_85FD,
+    0xA50A_B56B,
+    0x35B5_A8FA,
+    0x42B2_986C,
+    0xDBBB_C9D6,
+    0xACBC_F940,
+    0x32D8_6CE3,
+    0x45DF_5C75,
+    0xDCD6_0DCF,
+    0xABD1_3D59,
+    0x26D9_30AC,
+    0x51DE_003A,
+    0xC8D7_5180,
+    0xBFD0_6116,
+    0x21B4_F4B5,
+    0x56B3_C423,
+    0xCFBA_9599,
+    0xB8BD_A50F,
+    0x2802_B89E,
+    0x5F05_8808,
+    0xC60C_D9B2,
+    0xB10B_E924,
+    0x2F6F_7C87,
+    0x5868_4C11,
+    0xC161_1DAB,
+    0xB666_2D3D,
+    0x76DC_4190,
+    0x01DB_7106,
+    0x98D2_20BC,
+    0xEFD5_102A,
+    0x71B1_8589,
+    0x06B6_B51F,
+    0x9FBF_E4A5,
+    0xE8B8_D433,
+    0x7807_C9A2,
+    0x0F00_F934,
+    0x9609_A88E,
+    0xE10E_9818,
+    0x7F6A_0DBB,
+    0x086D_3D2D,
+    0x9164_6C97,
+    0xE663_5C01,
+    0x6B6B_51F4,
+    0x1C6C_6162,
+    0x8565_30D8,
+    0xF262_004E,
+    0x6C06_95ED,
+    0x1B01_A57B,
+    0x8208_F4C1,
+    0xF50F_C457,
+    0x65B0_D9C6,
+    0x12B7_E950,
+    0x8BBE_B8EA,
+    0xFCB9_887C,
+    0x62DD_1DDF,
+    0x15DA_2D49,
+    0x8CD3_7CF3,
+    0xFBD4_4C65,
+    0x4DB2_6158,
+    0x3AB5_51CE,
+    0xA3BC_0074,
+    0xD4BB_30E2,
+    0x4ADF_A541,
+    0x3DD8_95D7,
+    0xA4D1_C46D,
+    0xD3D6_F4FB,
+    0x4369_E96A,
+    0x346E_D9FC,
+    0xAD67_8846,
+    0xDA60_B8D0,
+    0x4404_2D73,
+    0x3303_1DE5,
+    0xAA0A_4C5F,
+    0xDD0D_7CC9,
+    0x5005_713C,
+    0x2702_41AA,
+    0xBE0B_1010,
+    0xC90C_2086,
+    0x5768_B525,
+    0x206F_85B3,
+    0xB966_D409,
+    0xCE61_E49F,
+    0x5EDE_F90E,
+    0x29D9_C998,
+    0xB0D0_9822,
+    0xC7D7_A8B4,
+    0x59B3_3D17,
+    0x2EB4_0D81,
+    0xB7BD_5C3B,
+    0xC0BA_6CAD,
+    0xEDB8_8320,
+    0x9ABF_B3B6,
+    0x03B6_E20C,
+    0x74B1_D29A,
+    0xEAD5_4739,
+    0x9DD2_77AF,
+    0x04DB_2615,
+    0x73DC_1683,
+    0xE363_0B12,
+    0x9464_3B84,
+    0x0D6D_6A3E,
+    0x7A6A_5AA8,
+    0xE40E_CF0B,
+    0x9309_FF9D,
+    0x0A00_AE27,
+    0x7D07_9EB1,
+    0xF00F_9344,
+    0x8708_A3D2,
+    0x1E01_F268,
+    0x6906_C2FE,
+    0xF762_575D,
+    0x8065_67CB,
+    0x196C_3671,
+    0x6E6B_06E7,
+    0xFED4_1B76,
+    0x89D3_2BE0,
+    0x10DA_7A5A,
+    0x67DD_4ACC,
+    0xF9B9_DF6F,
+    0x8EBE_EFF9,
+    0x17B7_BE43,
+    0x60B0_8ED5,
+    0xD6D6_A3E8,
+    0xA1D1_937E,
+    0x38D8_C2C4,
+    0x4FDF_F252,
+    0xD1BB_67F1,
+    0xA6BC_5767,
+    0x3FB5_06DD,
+    0x48B2_364B,
+    0xD80D_2BDA,
+    0xAF0A_1B4C,
+    0x3603_4AF6,
+    0x4104_7A60,
+    0xDF60_EFC3,
+    0xA867_DF55,
+    0x316E_8EEF,
+    0x4669_BE79,
+    0xCB61_B38C,
+    0xBC66_831A,
+    0x256F_D2A0,
+    0x5268_E236,
+    0xCC0C_7795,
+    0xBB0B_4703,
+    0x2202_16B9,
+    0x5505_262F,
+    0xC5BA_3BBE,
+    0xB2BD_0B28,
+    0x2BB4_5A92,
+    0x5CB3_6A04,
+    0xC2D7_FFA7,
+    0xB5D0_CF31,
+    0x2CD9_9E8B,
+    0x5BDE_AE1D,
+    0x9B64_C2B0,
+    0xEC63_F226,
+    0x756A_A39C,
+    0x026D_930A,
+    0x9C09_06A9,
+    0xEB0E_363F,
+    0x7207_6785,
+    0x0500_5713,
+    0x95BF_4A82,
+    0xE2B8_7A14,
+    0x7BB1_2BAE,
+    0x0CB6_1B38,
+    0x92D2_8E9B,
+    0xE5D5_BE0D,
+    0x7CDC_EFB7,
+    0x0BDB_DF21,
+    0x86D3_D2D4,
+    0xF1D4_E242,
+    0x68DD_B3F8,
+    0x1FDA_836E,
+    0x81BE_16CD,
+    0xF6B9_265B,
+    0x6FB0_77E1,
+    0x18B7_4777,
+    0x8808_5AE6,
+    0xFF0F_6A70,
+    0x6606_3BCA,
+    0x1101_0B5C,
+    0x8F65_9EFF,
+    0xF862_AE69,
+    0x616B_FFD3,
+    0x166C_CF45,
+    0xA00A_E278,
+    0xD70D_D2EE,
+    0x4E04_8354,
+    0x3903_B3C2,
+    0xA767_2661,
+    0xD060_16F7,
+    0x4969_474D,
+    0x3E6E_77DB,
+    0xAED1_6A4A,
+    0xD9D6_5ADC,
+    0x40DF_0B66,
+    0x37D8_3BF0,
+    0xA9BC_AE53,
+    0xDEBB_9EC5,
+    0x47B2_CF7F,
+    0x30B5_FFE9,
+    0xBDBD_F21C,
+    0xCABA_C28A,
+    0x53B3_9330,
+    0x24B4_A3A6,
+    0xBAD0_3605,
+    0xCDD7_0693,
+    0x54DE_5729,
+    0x23D9_67BF,
+    0xB366_7A2E,
+    0xC461_4AB8,
+    0x5D68_1B02,
+    0x2A6F_2B94,
+    0xB40B_BE37,
+    0xC30C_8EA1,
+    0x5A05_DF1B,
+    0x2D02_EF8D,
+];
+
+#[allow(non_camel_case_types)]
+#[derive(Debug)]
+pub struct ETH_FSC(pub u32);
+
+impl ETH_FSC {
+    pub const CRC32_OK: u32 = 0x2144_df1c;
+
+    #[must_use]
+    pub fn new(data: &[u8]) -> Self {
+        let fsc = data.iter().fold(u32::MAX, |crc, byte| {
+            let idx = u8::try_from(crc & 0xFF).unwrap() ^ byte;
+            CRC32R_LOOKUP_TABLE[usize::from(idx)] ^ (crc >> 8)
+        }) ^ u32::MAX;
+        Self(fsc)
+    }
+
+    #[must_use]
+    pub fn update(self, data: &[u8]) -> Self {
+        let fsc = data.iter().fold(self.0 ^ u32::MAX, |crc, byte| {
+            let idx = u8::try_from(crc & 0xFF).unwrap() ^ byte;
+            CRC32R_LOOKUP_TABLE[usize::from(idx)] ^ (crc >> 8)
+        }) ^ u32::MAX;
+        Self(fsc)
+    }
+
+    #[must_use]
+    pub fn crc_ok(&self) -> bool {
+        self.0 == Self::CRC32_OK
+    }
+
+    #[must_use]
+    pub fn hton_bytes(&self) -> [u8; 4] {
+        self.0.to_le_bytes()
+    }
+
+    #[must_use]
+    pub fn hton(&self) -> u32 {
+        self.0.to_le()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn crc32_ethernet_frame() {
+        let packet_a = &[
+            0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xe0, 0x4c, 0x68, 0xee, 0xee, 0xff, 0x06, 0x00, 0x01, 0x08, 0x00,
+            0x06, 0x04, 0x00, 0x01, 0x00, 0xe0, 0x4c, 0x68, 0x0e, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0xc0, 0xa8, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf2, 0x65, 0x90, 0x3d,
+        ];
+
+        let packet_b = &[
+            0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0x00, 0xe0, 0x4c, 0x68, 0xee, 0xee, 0xdd, 0x06, 0x00, 0x01, 0x08, 0x00,
+            0x06, 0x04, 0x00, 0x02, 0x00, 0xe0, 0x4c, 0x68, 0x09, 0xde, 0xc0, 0xa8, 0x01, 0x02, 0x12, 0x34, 0x56, 0x78,
+            0x9a, 0xbc, 0xc0, 0xa8, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x3d, 0x67, 0x7c,
+        ];
+
+        // Packet A
+        let own_crc = ETH_FSC::new(&packet_a[0..60]);
+        let crc_bytes = own_crc.hton_bytes();
+        println!("{:08x} {:02x?}", own_crc.0, crc_bytes);
+        assert_eq!(&crc_bytes, &packet_a[60..64]);
+
+        let own_crc = ETH_FSC::new(packet_a);
+        println!("{:08x}", own_crc.0);
+        assert_eq!(own_crc.0, ETH_FSC::CRC32_OK);
+
+        // Packet B
+        let own_crc = ETH_FSC::new(&packet_b[0..60]);
+        let crc_bytes = own_crc.hton_bytes();
+        println!("{:08x} {:02x?}", own_crc.0, crc_bytes);
+        assert_eq!(&crc_bytes, &packet_b[60..64]);
+
+        let own_crc = ETH_FSC::new(packet_b);
+        println!("{:08x}", own_crc.0);
+        assert_eq!(own_crc.0, ETH_FSC::CRC32_OK);
+    }
+
+    #[test]
+    fn crc32_update() {
+        let full_data = &[
+            0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0x00, 0xe0, 0x4c, 0x68, 0xee, 0xee, 0xdd, 0x06, 0x00, 0x01, 0x08, 0x00,
+            0x06, 0x04, 0x00, 0x02, 0x00, 0xe0, 0x4c, 0x68, 0x09, 0xde, 0xc0, 0xa8, 0x01, 0x02, 0x12, 0x34, 0x56, 0x78,
+            0x9a, 0xbc, 0xc0, 0xa8, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x3d, 0x67, 0x7c,
+        ];
+
+        let (part_a, part_b) = full_data.split_at(16);
+        let crc_partially = ETH_FSC::new(part_a).update(part_b);
+
+        let crc_full = ETH_FSC::new(full_data);
+
+        assert_eq!(crc_full.0, crc_partially.0);
+    }
+}

embassy-net-adin1110/src/crc8.rs

@@ -0,0 +1,53 @@
+/// CRC-8/ITU
+const CRC8X_TABLE: [u8; 256] = [
+    0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, 0x70, 0x77, 0x7e,
+    0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d, 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb,
+    0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd, 0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, 0xa8,
+    0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd, 0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, 0xff, 0xf8, 0xf1, 0xf6,
+    0xe3, 0xe4, 0xed, 0xea, 0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d,
+    0x9a, 0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, 0x1f, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0d, 0x0a, 0x57, 0x50,
+    0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42, 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a, 0x89, 0x8e, 0x87, 0x80, 0x95,
+    0x92, 0x9b, 0x9c, 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4, 0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec,
+    0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4, 0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, 0x51, 0x56, 0x5f,
+    0x58, 0x4d, 0x4a, 0x43, 0x44, 0x19, 0x1e, 0x17, 0x10, 0x05, 0x02, 0x0b, 0x0c, 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a,
+    0x33, 0x34, 0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63, 0x3e,
+    0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, 0x06, 0x01, 0x08, 0x0f, 0x1a, 0x1d, 0x14, 0x13, 0xae, 0xa9, 0xa0, 0xa7,
+    0xb2, 0xb5, 0xbc, 0xbb, 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83, 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc,
+    0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3,
+];
+
+/// Calculate the crc of a pease of data.
+pub fn crc8(data: &[u8]) -> u8 {
+    data.iter().fold(0, |crc, &byte| CRC8X_TABLE[usize::from(byte ^ crc)])
+}
+
+#[cfg(test)]
+mod tests {
+    use ::crc::{Crc, CRC_8_SMBUS};
+
+    use super::crc8;
+
+    #[test]
+    fn spi_header_crc8() {
+        let data = &[0x80, 0x00];
+
+        let c = Crc::<u8>::new(&CRC_8_SMBUS);
+        let mut dig = c.digest();
+        dig.update(data);
+        let sw_crc = dig.finalize();
+
+        let own_crc = crc8(data);
+
+        assert_eq!(own_crc, sw_crc);
+        assert_eq!(own_crc, 182);
+
+        let data = &[0x80, 0x01];
+        let mut dig = c.digest();
+        dig.update(data);
+        let sw_crc = dig.finalize();
+        let own_crc = crc8(data);
+
+        assert_eq!(own_crc, sw_crc);
+        assert_eq!(own_crc, 177);
+    }
+}

embassy-net-adin1110/src/mdio.rs

@@ -0,0 +1,175 @@
+/// PHY Address: (0..=0x1F), 5-bits long.
+#[allow(dead_code)]
+type PhyAddr = u8;
+
+/// PHY Register: (0..=0x1F), 5-bits long.
+#[allow(dead_code)]
+type RegC22 = u8;
+
+/// PHY Register Clause 45.
+#[allow(dead_code)]
+type RegC45 = u16;
+
+/// PHY Register Value
+#[allow(dead_code)]
+type RegVal = u16;
+
+#[allow(dead_code)]
+const REG13: RegC22 = 13;
+#[allow(dead_code)]
+const REG14: RegC22 = 14;
+
+#[allow(dead_code)]
+const PHYADDR_MASK: u8 = 0x1f;
+#[allow(dead_code)]
+const DEV_MASK: u8 = 0x1f;
+
+#[allow(dead_code)]
+#[repr(u16)]
+enum Reg13Op {
+    Addr = 0b00 << 14,
+    Write = 0b01 << 14,
+    PostReadIncAddr = 0b10 << 14,
+    Read = 0b11 << 14,
+}
+/// `MdioBus` trait
+/// Driver needs to implement the Clause 22
+/// Optional Clause 45 is the device supports this.
+///
+/// Claus 45 methodes are bases on <https://www.ieee802.org/3/efm/public/nov02/oam/pannell_oam_1_1102.pdf>
+pub trait MdioBus {
+    type Error;
+
+    /// Read, Clause 22
+    async fn read_cl22(&mut self, phy_id: PhyAddr, reg: RegC22) -> Result<RegVal, Self::Error>;
+
+    /// Write, Clause 22
+    async fn write_cl22(&mut self, phy_id: PhyAddr, reg: RegC22, reg_val: RegVal) -> Result<(), Self::Error>;
+
+    /// Read, Clause 45
+    /// This is the default implementation.
+    /// Many hardware these days support direct Clause 45 operations.
+    /// Implement this function when your hardware supports it.
+    async fn read_cl45(&mut self, phy_id: PhyAddr, regc45: (u8, RegC45)) -> Result<RegVal, Self::Error> {
+        // Write FN
+        let val = (Reg13Op::Addr as RegVal) | RegVal::from(regc45.0 & DEV_MASK);
+
+        self.write_cl22(phy_id, REG13, val).await?;
+        // Write Addr
+        self.write_cl22(phy_id, REG14, regc45.1).await?;
+
+        // Write FN
+        let val = (Reg13Op::Read as RegVal) | RegVal::from(regc45.0 & DEV_MASK);
+        self.write_cl22(phy_id, REG13, val).await?;
+        // Write Addr
+        self.read_cl22(phy_id, REG14).await
+    }
+
+    /// Write, Clause 45
+    /// This is the default implementation.
+    /// Many hardware these days support direct Clause 45 operations.
+    /// Implement this function when your hardware supports it.
+    async fn write_cl45(&mut self, phy_id: PhyAddr, regc45: (u8, RegC45), reg_val: RegVal) -> Result<(), Self::Error> {
+        let dev_addr = RegVal::from(regc45.0 & DEV_MASK);
+        let reg = regc45.1;
+
+        // Write FN
+        let val = (Reg13Op::Addr as RegVal) | dev_addr;
+        self.write_cl22(phy_id, REG13, val).await?;
+        // Write Addr
+        self.write_cl22(phy_id, REG14, reg).await?;
+
+        // Write FN
+        let val = (Reg13Op::Write as RegVal) | dev_addr;
+        self.write_cl22(phy_id, REG13, val).await?;
+        // Write Addr
+        self.write_cl22(phy_id, REG14, reg_val).await
+    }
+}
+
+// #[cfg(test)]
+// mod tests {
+//     use core::convert::Infallible;
+
+//     use super::{MdioBus, PhyAddr, RegC22, RegVal};
+
+//     #[derive(Debug, PartialEq, Eq)]
+//     enum A {
+//         Read(PhyAddr, RegC22),
+//         Write(PhyAddr, RegC22, RegVal),
+//     }
+
+//     struct MockMdioBus(Vec<A>);
+
+//     impl MockMdioBus {
+//         pub fn clear(&mut self) {
+//             self.0.clear();
+//         }
+//     }
+
+//     impl MdioBus for MockMdioBus {
+//         type Error = Infallible;
+
+//         fn write_cl22(
+//             &mut self,
+//             phy_id: super::PhyAddr,
+//             reg: super::RegC22,
+//             reg_val: super::RegVal,
+//         ) -> Result<(), Self::Error> {
+//             self.0.push(A::Write(phy_id, reg, reg_val));
+//             Ok(())
+//         }
+
+//         fn read_cl22(
+//             &mut self,
+//             phy_id: super::PhyAddr,
+//             reg: super::RegC22,
+//         ) -> Result<super::RegVal, Self::Error> {
+//             self.0.push(A::Read(phy_id, reg));
+//             Ok(0)
+//         }
+//     }
+
+//     #[test]
+//     fn read_test() {
+//         let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
+
+//         mdiobus.clear();
+//         mdiobus.read_cl22(0x01, 0x00).unwrap();
+//         assert_eq!(mdiobus.0, vec![A::Read(0x01, 0x00)]);
+
+//         mdiobus.clear();
+//         mdiobus.read_cl45(0x01, (0xBB, 0x1234)).unwrap();
+//         assert_eq!(
+//             mdiobus.0,
+//             vec![
+//                 #[allow(clippy::identity_op)]
+//                 A::Write(0x01, 13, (0b00 << 14) | 27),
+//                 A::Write(0x01, 14, 0x1234),
+//                 A::Write(0x01, 13, (0b11 << 14) | 27),
+//                 A::Read(0x01, 14)
+//             ]
+//         );
+//     }
+
+//     #[test]
+//     fn write_test() {
+//         let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
+
+//         mdiobus.clear();
+//         mdiobus.write_cl22(0x01, 0x00, 0xABCD).unwrap();
+//         assert_eq!(mdiobus.0, vec![A::Write(0x01, 0x00, 0xABCD)]);
+
+//         mdiobus.clear();
+//         mdiobus.write_cl45(0x01, (0xBB, 0x1234), 0xABCD).unwrap();
+//         assert_eq!(
+//             mdiobus.0,
+//             vec![
+//                 A::Write(0x01, 13, 27),
+//                 A::Write(0x01, 14, 0x1234),
+//                 A::Write(0x01, 13, (0b01 << 14) | 27),
+//                 A::Write(0x01, 14, 0xABCD)
+//             ]
+//         );
+//     }
+// }

embassy-net-adin1110/src/phy.rs

@@ -0,0 +1,142 @@
+use crate::mdio::MdioBus;
+
+#[allow(dead_code, non_camel_case_types, clippy::upper_case_acronyms)]
+#[repr(u8)]
+/// Clause 22 Registers
+pub enum RegsC22 {
+    /// MII Control Register
+    CONTROL = 0x00,
+    /// MII Status Register
+    STATUS = 0x01,
+    /// PHY Identifier 1 Register
+    PHY_ID1 = 0x02,
+    /// PHY Identifier 2 Register.
+    PHY_ID2 = 0x03,
+}
+
+/// Clause 45 Registers
+#[allow(non_snake_case, dead_code)]
+pub mod RegsC45 {
+    /// Device Address: 0x01
+    #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
+    #[repr(u16)]
+    pub enum DA1 {
+        /// PMA/PMD Control 1 Register
+        PMA_PMD_CNTRL1 = 0x0000,
+        /// PMA/PMD Status 1 Register
+        PMA_PMD_STAT1 = 0x0001,
+        /// MSE Value Register
+        MSE_VAL = 0x830B,
+    }
+
+    impl DA1 {
+        #[must_use]
+        pub fn into(self) -> (u8, u16) {
+            (0x01, self as u16)
+        }
+    }
+
+    /// Device Address: 0x03
+    #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
+    #[repr(u16)]
+    pub enum DA3 {
+        /// PCS Control 1 Register
+        PCS_CNTRL1 = 0x0000,
+        /// PCS Status 1 Register
+        PCS_STAT1 = 0x0001,
+        /// PCS Status 2 Register
+        PCS_STAT2 = 0x0008,
+    }
+
+    impl DA3 {
+        #[must_use]
+        pub fn into(self) -> (u8, u16) {
+            (0x03, self as u16)
+        }
+    }
+
+    /// Device Address: 0x07
+    #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
+    #[repr(u16)]
+    pub enum DA7 {
+        /// Extra Autonegotiation Status Register
+        AN_STATUS_EXTRA = 0x8001,
+    }
+
+    impl DA7 {
+        #[must_use]
+        pub fn into(self) -> (u8, u16) {
+            (0x07, self as u16)
+        }
+    }
+
+    /// Device Address: 0x1E
+    #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
+    #[repr(u16)]
+    pub enum DA1E {
+        /// System Interrupt Status Register
+        CRSM_IRQ_STATUS = 0x0010,
+        /// System Interrupt Mask Register
+        CRSM_IRQ_MASK = 0x0020,
+        /// Pin Mux Configuration 1 Register
+        DIGIO_PINMUX = 0x8c56,
+        /// LED Control Register.
+        LED_CNTRL = 0x8C82,
+        /// LED Polarity Register
+        LED_POLARITY = 0x8C83,
+    }
+
+    impl DA1E {
+        #[must_use]
+        pub fn into(self) -> (u8, u16) {
+            (0x1e, self as u16)
+        }
+    }
+
+    /// Device Address: 0x1F
+    #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
+    #[repr(u16)]
+    pub enum DA1F {
+        /// PHY Subsystem Interrupt Status Register
+        PHY_SYBSYS_IRQ_STATUS = 0x0011,
+        /// PHY Subsystem Interrupt Mask Register
+        PHY_SYBSYS_IRQ_MASK = 0x0021,
+    }
+
+    impl DA1F {
+        #[must_use]
+        pub fn into(self) -> (u8, u16) {
+            (0x1f, self as u16)
+        }
+    }
+}
+
+pub struct Phy10BaseT1x(u8);
+
+impl Default for Phy10BaseT1x {
+    fn default() -> Self {
+        Self(0x01)
+    }
+}
+
+impl Phy10BaseT1x {
+    /// Get the both parts of the PHYID.
+    pub async fn get_id<MDIOBUS, MDE>(&self, mdiobus: &mut MDIOBUS) -> Result<u32, MDE>
+    where
+        MDIOBUS: MdioBus<Error = MDE>,
+        MDE: core::fmt::Debug,
+    {
+        let mut phyid = u32::from(mdiobus.read_cl22(self.0, RegsC22::PHY_ID1 as u8).await?) << 16;
+        phyid |= u32::from(mdiobus.read_cl22(self.0, RegsC22::PHY_ID2 as u8).await?);
+        Ok(phyid)
+    }
+
+    /// Get the Mean Squared Error Value.
+    pub async fn get_sqi<MDIOBUS, MDE>(&self, mdiobus: &mut MDIOBUS) -> Result<u16, MDE>
+    where
+        MDIOBUS: MdioBus<Error = MDE>,
+        MDE: core::fmt::Debug,
+    {
+        mdiobus.read_cl45(self.0, RegsC45::DA1::MSE_VAL.into()).await
+    }
+}

embassy-net-adin1110/src/regs.rs

@@ -0,0 +1,408 @@
+use bitfield::{bitfield, bitfield_bitrange, bitfield_fields};
+
+#[allow(non_camel_case_types)]
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(u16)]
+/// SPI REGISTER DETAILS
+/// Table 38.
+pub enum SpiRegisters {
+    IDVER = 0x00,
+    PHYID = 0x01,
+    CAPABILITY = 0x02,
+    RESET = 0x03,
+    CONFIG0 = 0x04,
+    CONFIG2 = 0x06,
+    STATUS0 = 0x08,
+    STATUS1 = 0x09,
+    IMASK0 = 0x0C,
+    IMASK1 = 0x0D,
+    MDIO_ACC = 0x20,
+    TX_FSIZE = 0x30,
+    TX = 0x31,
+    TX_SPACE = 0x32,
+    FIFO_CLR = 0x36,
+    ADDR_FILT_UPR0 = 0x50,
+    ADDR_FILT_LWR0 = 0x51,
+    ADDR_FILT_UPR1 = 0x52,
+    ADDR_FILT_LWR1 = 0x53,
+    ADDR_MSK_LWR0 = 0x70,
+    ADDR_MSK_UPR0 = 0x71,
+    ADDR_MSK_LWR1 = 0x72,
+    ADDR_MSK_UPR1 = 0x73,
+    RX_FSIZE = 0x90,
+    RX = 0x91,
+}
+
+impl From<SpiRegisters> for u16 {
+    fn from(val: SpiRegisters) -> Self {
+        val as u16
+    }
+}
+
+impl From<u16> for SpiRegisters {
+    fn from(value: u16) -> Self {
+        match value {
+            0x00 => Self::IDVER,
+            0x01 => Self::PHYID,
+            0x02 => Self::CAPABILITY,
+            0x03 => Self::RESET,
+            0x04 => Self::CONFIG0,
+            0x06 => Self::CONFIG2,
+            0x08 => Self::STATUS0,
+            0x09 => Self::STATUS1,
+            0x0C => Self::IMASK0,
+            0x0D => Self::IMASK1,
+            0x20 => Self::MDIO_ACC,
+            0x30 => Self::TX_FSIZE,
+            0x31 => Self::TX,
+            0x32 => Self::TX_SPACE,
+            0x36 => Self::FIFO_CLR,
+            0x50 => Self::ADDR_FILT_UPR0,
+            0x51 => Self::ADDR_FILT_LWR0,
+            0x52 => Self::ADDR_FILT_UPR1,
+            0x53 => Self::ADDR_FILT_LWR1,
+            0x70 => Self::ADDR_MSK_LWR0,
+            0x71 => Self::ADDR_MSK_UPR0,
+            0x72 => Self::ADDR_MSK_LWR1,
+            0x73 => Self::ADDR_MSK_UPR1,
+            0x90 => Self::RX_FSIZE,
+            0x91 => Self::RX,
+            e => panic!("Unknown value {e}"),
+        }
+    }
+}
+
+// Register definitions
+bitfield! {
+    /// Status0 Register bits
+    pub struct Status0(u32);
+    impl Debug;
+    u32;
+    /// Control Data Protection Error
+    pub cdpe, _ : 12;
+    /// Transmit Frame Check Squence Error
+    pub txfcse, _: 11;
+    /// Transmit Time Stamp Capture Available C
+    pub ttscac, _ : 10;
+    /// Transmit Time Stamp Capture Available B
+    pub ttscab, _ : 9;
+    /// Transmit Time Stamp Capture Available A
+    pub ttscaa, _ : 8;
+    /// PHY Interrupt for Port 1
+    pub phyint, _ : 7;
+    /// Reset Complete
+    pub resetc, _ : 6;
+    /// Header error
+    pub hdre, _ : 5;
+    /// Loss of Frame Error
+    pub lofe, _ : 4;
+    /// Receiver Buffer Overflow Error
+    pub rxboe, _ : 3;
+    /// Host Tx FIFO Under Run Error
+    pub txbue, _ : 2;
+    /// Host Tx FIFO Overflow
+    pub txboe, _ : 1;
+    /// Transmit Protocol Error
+    pub txpe, _ : 0;
+}
+
+bitfield! {
+    /// Status1 Register bits
+    pub struct Status1(u32);
+    impl Debug;
+    u32;
+    /// ECC Error on Reading the Frame Size from a Tx FIFO
+    pub tx_ecc_err, set_tx_ecc_err: 12;
+    /// ECC Error on Reading the Frame Size from an Rx FIFO
+    pub rx_ecc_err, set_rx_ecc_err : 11;
+    /// Detected an Error on an SPI Transaction
+    pub spi_err, set_spi_err: 10;
+    /// Rx MAC Interframe Gap Error
+    pub p1_rx_ifg_err, set_p1_rx_ifg_err : 8;
+    /// Port1 Rx Ready High Priority
+    pub p1_rx_rdy_hi, set_p1_rx_rdy_hi : 5;
+    /// Port 1 Rx FIFO Contains Data
+    pub p1_rx_rdy, set_p1_rx_rdy : 4;
+    /// Tx Ready
+    pub tx_rdy, set_tx_rdy : 3;
+    /// Link Status Changed
+    pub link_change, set_link_change : 1;
+    /// Port 1 Link Status
+    pub p1_link_status, _ : 0;
+}
+
+bitfield! {
+    /// Config0 Register bits
+    pub struct Config0(u32);
+    impl Debug;
+    u32;
+    /// Configuration Synchronization
+    pub sync, set_sync : 15;
+    /// Transmit Frame Check Sequence Validation Enable
+    pub txfcsve, set_txfcsve : 14;
+    /// !CS Align Receive Frame Enable
+    pub csarfe, set_csarfe : 13;
+    /// Zero Align Receive Frame Enable
+    pub zarfe, set_zarfe : 12;
+    /// Transmit Credit Threshold
+    pub tcxthresh, set_tcxthresh : 11, 10;
+    /// Transmit Cut Through Enable
+    pub txcte, set_txcte : 9;
+    /// Receive Cut Through Enable
+    pub rxcte, set_rxcte : 8;
+    /// Frame Time Stamp Enable
+    pub ftse, set_ftse : 7;
+    /// Receive Frame Time Stamp Select
+    pub ftss, set_ftss : 6;
+    /// Enable Control Data Read Write Protection
+    pub prote, set_prote : 5;
+    /// Enable TX Data Chunk Sequence and Retry
+    pub seqe, set_seqe : 4;
+    /// Chunk Payload Selector (N).
+    pub cps, set_cps : 2, 0;
+}
+
+bitfield! {
+    /// Config2 Register bits
+    pub struct Config2(u32);
+    impl Debug;
+    u32;
+    /// Assert TX_RDY When the Tx FIFO is Empty
+    pub tx_rdy_on_empty, set_tx_rdy_on_empty : 8;
+    /// Determines If the SFD is Detected in the PHY or MAC
+    pub sdf_detect_src, set_sdf_detect_src : 7;
+    /// Statistics Clear on Reading
+    pub stats_clr_on_rd, set_stats_clr_on_rd : 6;
+    /// Enable CRC Append
+    pub crc_append, set_crc_append : 5;
+    /// Admit Frames with IFG Errors on Port 1 (P1)
+    pub p1_rcv_ifg_err_frm, set_p1_rcv_ifg_err_frm : 4;
+    /// Forward Frames Not Matching Any MAC Address to the Host
+    pub p1_fwd_unk2host, set_p1_fwd_unk2host : 2;
+    /// SPI to MDIO Bridge MDC Clock Speed
+    pub mspeed, set_mspeed : 0;
+}
+
+bitfield! {
+    /// IMASK0 Register bits
+    pub struct IMask0(u32);
+    impl Debug;
+    u32;
+    /// Control Data Protection Error Mask
+    pub cppem, set_cppem : 12;
+    /// Transmit Frame Check Sequence Error Mask
+    pub txfcsem, set_txfcsem : 11;
+    /// Transmit Time Stamp Capture Available C Mask
+    pub ttscacm, set_ttscacm : 10;
+    /// Transmit Time Stamp Capture Available B Mask
+    pub ttscabm, set_ttscabm : 9;
+    /// Transmit Time Stamp Capture Available A Mask
+    pub ttscaam, set_ttscaam : 8;
+    /// Physical Layer Interrupt Mask
+    pub phyintm, set_phyintm : 7;
+    /// RESET Complete Mask
+    pub resetcm, set_resetcm : 6;
+    /// Header Error Mask
+    pub hdrem, set_hdrem : 5;
+    /// Loss of Frame Error Mask
+    pub lofem, set_lofem : 4;
+    /// Receive Buffer Overflow Error Mask
+    pub rxboem, set_rxboem : 3;
+    /// Transmit Buffer Underflow Error Mask
+    pub txbuem, set_txbuem : 2;
+    /// Transmit Buffer Overflow Error Mask
+    pub txboem, set_txboem : 1;
+    /// Transmit Protocol Error Mask
+    pub txpem, set_txpem : 0;
+}
+
+bitfield! {
+    /// IMASK1 Register bits
+    pub struct IMask1(u32);
+    impl Debug;
+    u32;
+    /// Mask Bit for TXF_ECC_ERR
+    pub tx_ecc_err_mask, set_tx_ecc_err_mask : 12;
+    /// Mask Bit for RXF_ECC_ERR
+    pub rx_ecc_err_mask, set_rx_ecc_err_mask : 11;
+    /// Mask Bit for SPI_ERR
+    /// This field is only used with the generic SPI protocol
+    pub spi_err_mask, set_spi_err_mask : 10;
+    /// Mask Bit for RX_IFG_ERR
+    pub p1_rx_ifg_err_mask, set_p1_rx_ifg_err_mask : 8;
+    /// Mask Bit for P1_RX_RDY
+    /// This field is only used with the generic SPI protocol
+    pub p1_rx_rdy_mask, set_p1_rx_rdy_mask : 4;
+    /// Mask Bit for TX_FRM_DONE
+    /// This field is only used with the generic SPI protocol
+    pub tx_rdy_mask, set_tx_rdy_mask : 3;
+    /// Mask Bit for LINK_CHANGE
+    pub link_change_mask, set_link_change_mask : 1;
+}
+
+/// LED Functions
+#[repr(u8)]
+pub enum LedFunc {
+    LinkupTxRxActicity = 0,
+    LinkupTxActicity,
+    LinkupRxActicity,
+    LinkupOnly,
+    TxRxActivity,
+    TxActivity,
+    RxActivity,
+    LinkupRxEr,
+    LinkupRxTxEr,
+    RxEr,
+    RxTxEr,
+    TxSop,
+    RxSop,
+    On,
+    Off,
+    Blink,
+    TxLevel2P4,
+    TxLevel1P0,
+    Master,
+    Slave,
+    IncompatiableLinkCfg,
+    AnLinkGood,
+    AnComplete,
+    TsTimer,
+    LocRcvrStatus,
+    RemRcvrStatus,
+    Clk25Ref,
+    TxTCLK,
+    Clk120MHz,
+}
+
+impl From<LedFunc> for u8 {
+    fn from(val: LedFunc) -> Self {
+        val as u8
+    }
+}
+
+impl From<u8> for LedFunc {
+    fn from(value: u8) -> Self {
+        match value {
+            0 => LedFunc::LinkupTxRxActicity,
+            1 => LedFunc::LinkupTxActicity,
+            2 => LedFunc::LinkupRxActicity,
+            3 => LedFunc::LinkupOnly,
+            4 => LedFunc::TxRxActivity,
+            5 => LedFunc::TxActivity,
+            6 => LedFunc::RxActivity,
+            7 => LedFunc::LinkupRxEr,
+            8 => LedFunc::LinkupRxTxEr,
+            9 => LedFunc::RxEr,
+            10 => LedFunc::RxTxEr,
+            11 => LedFunc::TxSop,
+            12 => LedFunc::RxSop,
+            13 => LedFunc::On,
+            14 => LedFunc::Off,
+            15 => LedFunc::Blink,
+            16 => LedFunc::TxLevel2P4,
+            17 => LedFunc::TxLevel1P0,
+            18 => LedFunc::Master,
+            19 => LedFunc::Slave,
+            20 => LedFunc::IncompatiableLinkCfg,
+            21 => LedFunc::AnLinkGood,
+            22 => LedFunc::AnComplete,
+            23 => LedFunc::TsTimer,
+            24 => LedFunc::LocRcvrStatus,
+            25 => LedFunc::RemRcvrStatus,
+            26 => LedFunc::Clk25Ref,
+            27 => LedFunc::TxTCLK,
+            28 => LedFunc::Clk120MHz,
+            e => panic!("Invalid value {e}"),
+        }
+    }
+}
+
+/// LED Control Register
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub struct LedCntrl(pub u16);
+bitfield_bitrange! {struct LedCntrl(u16)}
+
+impl LedCntrl {
+    bitfield_fields! {
+        u8;
+        /// LED 0 Pin Function
+        pub from into LedFunc, led0_function, set_led0_function: 4, 0;
+        /// LED 0 Mode Selection
+        pub led0_mode, set_led0_mode: 5;
+        /// Qualify Certain LED 0 Options with Link Status.
+        pub led0_link_st_qualify, set_led0_link_st_qualify: 6;
+        /// LED 0 Enable
+        pub led0_en, set_led0_en: 7;
+        /// LED 1 Pin Function
+        pub from into LedFunc, led1_function, set_led1_function: 12, 8;
+        /// /// LED 1 Mode Selection
+        pub led1_mode, set_led1_mode: 13;
+        /// Qualify Certain LED 1 Options with Link Status.
+        pub led1_link_st_qualify, set_led1_link_st_qualify: 14;
+        /// LED 1 Enable
+        pub led1_en, set_led1_en: 15;
+    }
+
+    pub fn new() -> Self {
+        LedCntrl(0)
+    }
+}
+
+// LED Polarity
+#[repr(u8)]
+pub enum LedPol {
+    AutoSense = 0,
+    ActiveHigh,
+    ActiveLow,
+}
+
+impl From<LedPol> for u8 {
+    fn from(val: LedPol) -> Self {
+        val as u8
+    }
+}
+
+impl From<u8> for LedPol {
+    fn from(value: u8) -> Self {
+        match value {
+            0 => LedPol::AutoSense,
+            1 => LedPol::ActiveHigh,
+            2 => LedPol::ActiveLow,
+            e => panic!("Invalid value {e}"),
+        }
+    }
+}
+
+/// LED Control Register
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub struct LedPolarity(pub u16);
+bitfield_bitrange! {struct LedPolarity(u16)}
+
+impl LedPolarity {
+    bitfield_fields! {
+        u8;
+        /// LED 1 Polarity
+        pub from into LedPol, led1_polarity, set_led1_polarity: 3, 2;
+        /// LED 0 Polarity
+        pub from into LedPol, led0_polarity, set_led0_polarity: 1, 0;
+    }
+}
+
+/// SPI Header
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub struct SpiHeader(pub u16);
+bitfield_bitrange! {struct SpiHeader(u16)}
+
+impl SpiHeader {
+    bitfield_fields! {
+        u16;
+        /// Mask Bit for TXF_ECC_ERR
+        pub control, set_control : 15;
+        pub full_duplex, set_full_duplex : 14;
+        /// Read or Write to register
+        pub write, set_write : 13;
+        /// Registers ID/addr
+        pub from into SpiRegisters, addr, set_addr: 11, 0;
+    }
+}

embassy-net-driver-channel/README.md

@@ -76,7 +76,7 @@ These `embassy-net` drivers are implemented using this crate. You can look at th
 
 - [`cyw43`](https://github.com/embassy-rs/embassy/tree/main/cyw43) for WiFi on CYW43xx chips, used in the Raspberry Pi Pico W
 - [`embassy-usb`](https://github.com/embassy-rs/embassy/tree/main/embassy-usb) for Ethernet-over-USB (CDC NCM) support.
-- [`embassy-net-w5500`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-w5500) for Wiznet W5500 SPI Ethernet MAC+PHY chip.
+- [`embassy-net-wiznet`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-wiznet) for Wiznet SPI Ethernet MAC+PHY chips.
 - [`embassy-net-esp-hosted`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-esp-hosted) for using ESP32 chips with the [`esp-hosted`](https://github.com/espressif/esp-hosted) firmware as WiFi adapters for another non-ESP32 MCU.
 
 

embassy-net-driver-channel/src/lib.rs

@@ -8,6 +8,7 @@ use core::cell::RefCell;
 use core::mem::MaybeUninit;
 use core::task::{Context, Poll};
 
+use driver::HardwareAddress;
 pub use embassy_net_driver as driver;
 use embassy_net_driver::{Capabilities, LinkState, Medium};
 use embassy_sync::blocking_mutex::raw::NoopRawMutex;
@@ -73,6 +74,18 @@ impl<'d, const MTU: usize> Runner<'d, MTU> {
         )
     }
 
+    pub fn borrow_split(&mut self) -> (StateRunner<'_>, RxRunner<'_, MTU>, TxRunner<'_, MTU>) {
+        (
+            StateRunner { shared: self.shared },
+            RxRunner {
+                rx_chan: self.rx_chan.borrow(),
+            },
+            TxRunner {
+                tx_chan: self.tx_chan.borrow(),
+            },
+        )
+    }
+
     pub fn state_runner(&self) -> StateRunner<'d> {
         StateRunner { shared: self.shared }
     }
@@ -218,7 +231,11 @@ pub fn new<'d, const MTU: usize, const N_RX: usize, const N_TX: usize>(
 ) -> (Runner<'d, MTU>, Device<'d, MTU>) {
     let mut caps = Capabilities::default();
     caps.max_transmission_unit = MTU;
-    caps.medium = Medium::Ethernet;
+    caps.medium = match &hardware_address {
+        HardwareAddress::Ethernet(_) => Medium::Ethernet,
+        HardwareAddress::Ieee802154(_) => Medium::Ieee802154,
+        HardwareAddress::Ip => Medium::Ip,
+    };
 
     // safety: this is a self-referential struct, however:
     // - it can't move while the `'d` borrow is active.

embassy-net-enc28j60/Cargo.toml

@@ -0,0 +1,23 @@
+[package]
+name = "embassy-net-enc28j60"
+version = "0.1.0"
+description = "embassy-net driver for the ENC28J60 ethernet chip"
+keywords = ["embedded", "enc28j60", "embassy-net", "embedded-hal-async", "ethernet", "async"]
+categories = ["embedded", "hardware-support", "no-std", "network-programming", "async"]
+license = "MIT OR Apache-2.0"
+edition = "2021"
+
+[dependencies]
+embedded-hal = { version = "1.0.0-rc.1" }
+embedded-hal-async = { version = "=1.0.0-rc.1" }
+embassy-net-driver = { version = "0.1.0", path = "../embassy-net-driver" }
+embassy-time = { version = "0.1.2", path = "../embassy-time" }
+embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
+
+defmt = { version = "0.3", optional = true }
+log = { version = "0.4.14", optional = true }
+
+[package.metadata.embassy_docs]
+src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-enc28j60-v$VERSION/embassy-net-enc28j60/src/"
+src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-enc28j60/src/"
+target = "thumbv7em-none-eabi"

embassy-net-enc28j60/README.md

@@ -0,0 +1,19 @@
+# `embassy-net-enc28j60`
+
+[`embassy-net`](https://crates.io/crates/embassy-net) integration for the Microchip ENC28J60 Ethernet chip.
+
+Based on [@japaric](https://github.com/japaric)'s [`enc28j60`](https://github.com/japaric/enc28j60) crate.
+
+## Interoperability
+
+This crate can run on any executor.
+
+## License
+
+This work is licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.

embassy-net-enc28j60/src/bank0.rs

@@ -0,0 +1,69 @@
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum Register {
+    ERDPTL = 0x00,
+    ERDPTH = 0x01,
+    EWRPTL = 0x02,
+    EWRPTH = 0x03,
+    ETXSTL = 0x04,
+    ETXSTH = 0x05,
+    ETXNDL = 0x06,
+    ETXNDH = 0x07,
+    ERXSTL = 0x08,
+    ERXSTH = 0x09,
+    ERXNDL = 0x0a,
+    ERXNDH = 0x0b,
+    ERXRDPTL = 0x0c,
+    ERXRDPTH = 0x0d,
+    ERXWRPTL = 0x0e,
+    ERXWRPTH = 0x0f,
+    EDMASTL = 0x10,
+    EDMASTH = 0x11,
+    EDMANDL = 0x12,
+    EDMANDH = 0x13,
+    EDMADSTL = 0x14,
+    EDMADSTH = 0x15,
+    EDMACSL = 0x16,
+    EDMACSH = 0x17,
+}
+
+impl Register {
+    pub(crate) fn addr(&self) -> u8 {
+        *self as u8
+    }
+
+    pub(crate) fn is_eth_register(&self) -> bool {
+        match *self {
+            Register::ERDPTL => true,
+            Register::ERDPTH => true,
+            Register::EWRPTL => true,
+            Register::EWRPTH => true,
+            Register::ETXSTL => true,
+            Register::ETXSTH => true,
+            Register::ETXNDL => true,
+            Register::ETXNDH => true,
+            Register::ERXSTL => true,
+            Register::ERXSTH => true,
+            Register::ERXNDL => true,
+            Register::ERXNDH => true,
+            Register::ERXRDPTL => true,
+            Register::ERXRDPTH => true,
+            Register::ERXWRPTL => true,
+            Register::ERXWRPTH => true,
+            Register::EDMASTL => true,
+            Register::EDMASTH => true,
+            Register::EDMANDL => true,
+            Register::EDMANDH => true,
+            Register::EDMADSTL => true,
+            Register::EDMADSTH => true,
+            Register::EDMACSL => true,
+            Register::EDMACSH => true,
+        }
+    }
+}
+
+impl Into<super::Register> for Register {
+    fn into(self) -> super::Register {
+        super::Register::Bank0(self)
+    }
+}

embassy-net-enc28j60/src/bank1.rs

@@ -0,0 +1,84 @@
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum Register {
+    EHT0 = 0x00,
+    EHT1 = 0x01,
+    EHT2 = 0x02,
+    EHT3 = 0x03,
+    EHT4 = 0x04,
+    EHT5 = 0x05,
+    EHT6 = 0x06,
+    EHT7 = 0x07,
+    EPMM0 = 0x08,
+    EPMM1 = 0x09,
+    EPMM2 = 0x0a,
+    EPMM3 = 0x0b,
+    EPMM4 = 0x0c,
+    EPMM5 = 0x0d,
+    EPMM6 = 0x0e,
+    EPMM7 = 0x0f,
+    EPMCSL = 0x10,
+    EPMCSH = 0x11,
+    EPMOL = 0x14,
+    EPMOH = 0x15,
+    ERXFCON = 0x18,
+    EPKTCNT = 0x19,
+}
+
+impl Register {
+    pub(crate) fn addr(&self) -> u8 {
+        *self as u8
+    }
+
+    pub(crate) fn is_eth_register(&self) -> bool {
+        match *self {
+            Register::EHT0 => true,
+            Register::EHT1 => true,
+            Register::EHT2 => true,
+            Register::EHT3 => true,
+            Register::EHT4 => true,
+            Register::EHT5 => true,
+            Register::EHT6 => true,
+            Register::EHT7 => true,
+            Register::EPMM0 => true,
+            Register::EPMM1 => true,
+            Register::EPMM2 => true,
+            Register::EPMM3 => true,
+            Register::EPMM4 => true,
+            Register::EPMM5 => true,
+            Register::EPMM6 => true,
+            Register::EPMM7 => true,
+            Register::EPMCSL => true,
+            Register::EPMCSH => true,
+            Register::EPMOL => true,
+            Register::EPMOH => true,
+            Register::ERXFCON => true,
+            Register::EPKTCNT => true,
+        }
+    }
+}
+
+impl Into<super::Register> for Register {
+    fn into(self) -> super::Register {
+        super::Register::Bank1(self)
+    }
+}
+
+register!(ERXFCON, 0b1010_0001, u8, {
+    #[doc = "Broadcast Filter Enable bit"]
+    bcen @ 0,
+    #[doc = "Multicast Filter Enable bit"]
+    mcen @ 1,
+    #[doc = "Hash Table Filter Enable bit"]
+    hten @ 2,
+    #[doc = "Magic Packet™ Filter Enable bit"]
+    mpen @ 3,
+    #[doc = "Pattern Match Filter Enable bit"]
+    pmen @ 4,
+    #[doc = "Post-Filter CRC Check Enable bit"]
+    crcen @ 5,
+    #[doc = "AND/OR Filter Select bit"]
+    andor @ 6,
+    #[doc = "Unicast Filter Enable bit"]
+    ucen @ 7,
+});

embassy-net-enc28j60/src/bank2.rs

@@ -0,0 +1,86 @@
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum Register {
+    MACON1 = 0x00,
+    MACON3 = 0x02,
+    MACON4 = 0x03,
+    MABBIPG = 0x04,
+    MAIPGL = 0x06,
+    MAIPGH = 0x07,
+    MACLCON1 = 0x08,
+    MACLCON2 = 0x09,
+    MAMXFLL = 0x0a,
+    MAMXFLH = 0x0b,
+    MICMD = 0x12,
+    MIREGADR = 0x14,
+    MIWRL = 0x16,
+    MIWRH = 0x17,
+    MIRDL = 0x18,
+    MIRDH = 0x19,
+}
+
+impl Register {
+    pub(crate) fn addr(&self) -> u8 {
+        *self as u8
+    }
+
+    pub(crate) fn is_eth_register(&self) -> bool {
+        match *self {
+            Register::MACON1 => false,
+            Register::MACON3 => false,
+            Register::MACON4 => false,
+            Register::MABBIPG => false,
+            Register::MAIPGL => false,
+            Register::MAIPGH => false,
+            Register::MACLCON1 => false,
+            Register::MACLCON2 => false,
+            Register::MAMXFLL => false,
+            Register::MAMXFLH => false,
+            Register::MICMD => false,
+            Register::MIREGADR => false,
+            Register::MIWRL => false,
+            Register::MIWRH => false,
+            Register::MIRDL => false,
+            Register::MIRDH => false,
+        }
+    }
+}
+
+impl Into<super::Register> for Register {
+    fn into(self) -> super::Register {
+        super::Register::Bank2(self)
+    }
+}
+
+register!(MACON1, 0, u8, {
+    #[doc = "Enable packets to be received by the MAC"]
+    marxen @ 0,
+    #[doc = "Control frames will be discarded after being processed by the MAC"]
+    passall @ 1,
+    #[doc = "Inhibit transmissions when pause control frames are received"]
+    rxpaus @ 2,
+    #[doc = "Allow the MAC to transmit pause control frames"]
+    txpaus @ 3,
+});
+
+register!(MACON3, 0, u8, {
+    #[doc = "MAC will operate in Full-Duplex mode"]
+    fuldpx @ 0,
+    #[doc = "The type/length field of transmitted and received frames will be checked"]
+    frmlnen @ 1,
+    #[doc = "Frames bigger than MAMXFL will be aborted when transmitted or received"]
+    hfrmen @ 2,
+    #[doc = "No proprietary header is present"]
+    phdren @ 3,
+    #[doc = "MAC will append a valid CRC to all frames transmitted regardless of PADCFG bit"]
+    txcrcen @ 4,
+    #[doc = "All short frames will be zero-padded to 64 bytes and a valid CRC will then be appended"]
+    padcfg @ 5..7,
+});
+
+register!(MICMD, 0, u8, {
+    #[doc = "MII Read Enable bit"]
+    miird @ 0,
+    #[doc = "MII Scan Enable bit"]
+    miiscan @ 1,
+});

embassy-net-enc28j60/src/bank3.rs

@@ -0,0 +1,53 @@
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum Register {
+    MAADR5 = 0x00,
+    MAADR6 = 0x01,
+    MAADR3 = 0x02,
+    MAADR4 = 0x03,
+    MAADR1 = 0x04,
+    MAADR2 = 0x05,
+    EBSTSD = 0x06,
+    EBSTCON = 0x07,
+    EBSTCSL = 0x08,
+    EBSTCSH = 0x09,
+    MISTAT = 0x0a,
+    EREVID = 0x12,
+    ECOCON = 0x15,
+    EFLOCON = 0x17,
+    EPAUSL = 0x18,
+    EPAUSH = 0x19,
+}
+
+impl Register {
+    pub(crate) fn addr(&self) -> u8 {
+        *self as u8
+    }
+
+    pub(crate) fn is_eth_register(&self) -> bool {
+        match *self {
+            Register::MAADR5 => false,
+            Register::MAADR6 => false,
+            Register::MAADR3 => false,
+            Register::MAADR4 => false,
+            Register::MAADR1 => false,
+            Register::MAADR2 => false,
+            Register::EBSTSD => true,
+            Register::EBSTCON => true,
+            Register::EBSTCSL => true,
+            Register::EBSTCSH => true,
+            Register::MISTAT => false,
+            Register::EREVID => true,
+            Register::ECOCON => true,
+            Register::EFLOCON => true,
+            Register::EPAUSL => true,
+            Register::EPAUSH => true,
+        }
+    }
+}
+
+impl Into<super::Register> for Register {
+    fn into(self) -> super::Register {
+        super::Register::Bank3(self)
+    }
+}

embassy-net-enc28j60/src/common.rs

@@ -0,0 +1,106 @@
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum Register {
+    ECON1 = 0x1f,
+    ECON2 = 0x1e,
+    EIE = 0x1b,
+    EIR = 0x1c,
+    ESTAT = 0x1d,
+}
+
+impl Register {
+    pub(crate) fn addr(&self) -> u8 {
+        *self as u8
+    }
+
+    pub(crate) fn is_eth_register(&self) -> bool {
+        match *self {
+            Register::ECON1 => true,
+            Register::ECON2 => true,
+            Register::EIE => true,
+            Register::EIR => true,
+            Register::ESTAT => true,
+        }
+    }
+}
+
+impl Into<super::Register> for Register {
+    fn into(self) -> super::Register {
+        super::Register::Common(self)
+    }
+}
+
+register!(EIE, 0, u8, {
+    #[doc = "Receive Error Interrupt Enable bit"]
+    rxerie @ 0,
+    #[doc = "Transmit Error Interrupt Enable bit"]
+    txerie @ 1,
+    #[doc = "Transmit Enable bit"]
+    txie @ 3,
+    #[doc = "Link Status Change Interrupt Enable bit"]
+    linkie @ 4,
+    #[doc = "DMA Interrupt Enable bit"]
+    dmaie @ 5,
+    #[doc = "Receive Packet Pending Interrupt Enable bit"]
+    pktie @ 6,
+    #[doc = "Global INT Interrupt Enable bit"]
+    intie @ 7,
+});
+
+register!(EIR, 0, u8, {
+    #[doc = "Receive Error Interrupt Flag bit"]
+    rxerif @ 0,
+    #[doc = "Transmit Error Interrupt Flag bit"]
+    txerif @ 1,
+    #[doc = "Transmit Interrupt Flag bit"]
+    txif @ 3,
+    #[doc = "Link Change Interrupt Flag bit"]
+    linkif @ 4,
+    #[doc = "DMA Interrupt Flag bit"]
+    dmaif @ 5,
+    #[doc = "Receive Packet Pending Interrupt Flag bit"]
+    pktif @ 6,
+});
+
+register!(ESTAT, 0, u8, {
+    #[doc = "Clock Ready bit"]
+    clkrdy @ 0,
+    #[doc = "Transmit Abort Error bit"]
+    txabrt @ 1,
+    #[doc = "Receive Busy bit"]
+    rxbusy @ 2,
+    #[doc = "Late Collision Error bit"]
+    latecol @ 4,
+    #[doc = "Ethernet Buffer Error Status bit"]
+    bufer @ 6,
+    #[doc = "INT Interrupt Flag bit"]
+    int @ 7,
+});
+
+register!(ECON2, 0b1000_0000, u8, {
+    #[doc = "Voltage Regulator Power Save Enable bit"]
+    vrps @ 3,
+    #[doc = "Power Save Enable bit"]
+    pwrsv @ 5,
+    #[doc = "Packet Decrement bit"]
+    pktdec @ 6,
+    #[doc = "Automatic Buffer Pointer Increment Enable bit"]
+    autoinc @ 7,
+});
+
+register!(ECON1, 0, u8, {
+    #[doc = "Bank Select bits"]
+    bsel @ 0..1,
+    #[doc = "Receive Enable bi"]
+    rxen @ 2,
+    #[doc = "Transmit Request to Send bit"]
+    txrts @ 3,
+    #[doc = "DMA Checksum Enable bit"]
+    csumen @ 4,
+    #[doc = "DMA Start and Busy Status bit"]
+    dmast @ 5,
+    #[doc = "Receive Logic Reset bit"]
+    rxrst @ 6,
+    #[doc = "Transmit Logic Reset bit"]
+    txrst @ 7,
+});

embassy-net-enc28j60/src/fmt.rs

@@ -0,0 +1,225 @@
+#![macro_use]
+#![allow(unused_macros)]
+
+#[cfg(all(feature = "defmt", feature = "log"))]
+compile_error!("You may not enable both `defmt` and `log` features.");
+
+macro_rules! assert {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::assert!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::assert!($($x)*);
+        }
+    };
+}
+
+macro_rules! assert_eq {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::assert_eq!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::assert_eq!($($x)*);
+        }
+    };
+}
+
+macro_rules! assert_ne {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::assert_ne!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::assert_ne!($($x)*);
+        }
+    };
+}
+
+macro_rules! debug_assert {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::debug_assert!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug_assert!($($x)*);
+        }
+    };
+}
+
+macro_rules! debug_assert_eq {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::debug_assert_eq!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug_assert_eq!($($x)*);
+        }
+    };
+}
+
+macro_rules! debug_assert_ne {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::debug_assert_ne!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug_assert_ne!($($x)*);
+        }
+    };
+}
+
+macro_rules! todo {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::todo!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::todo!($($x)*);
+        }
+    };
+}
+
+macro_rules! unreachable {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::unreachable!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::unreachable!($($x)*);
+        }
+    };
+}
+
+macro_rules! panic {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::panic!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::panic!($($x)*);
+        }
+    };
+}
+
+macro_rules! trace {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::trace!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::trace!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+macro_rules! debug {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::debug!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+macro_rules! info {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::info!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::info!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+macro_rules! warn {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::warn!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::warn!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+macro_rules! error {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::error!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::error!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+#[cfg(feature = "defmt")]
+macro_rules! unwrap {
+    ($($x:tt)*) => {
+        ::defmt::unwrap!($($x)*)
+    };
+}
+
+#[cfg(not(feature = "defmt"))]
+macro_rules! unwrap {
+    ($arg:expr) => {
+        match $crate::fmt::Try::into_result($arg) {
+            ::core::result::Result::Ok(t) => t,
+            ::core::result::Result::Err(e) => {
+                ::core::panic!("unwrap of `{}` failed: {:?}", ::core::stringify!($arg), e);
+            }
+        }
+    };
+    ($arg:expr, $($msg:expr),+ $(,)? ) => {
+        match $crate::fmt::Try::into_result($arg) {
+            ::core::result::Result::Ok(t) => t,
+            ::core::result::Result::Err(e) => {
+                ::core::panic!("unwrap of `{}` failed: {}: {:?}", ::core::stringify!($arg), ::core::format_args!($($msg,)*), e);
+            }
+        }
+    }
+}
+
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+pub struct NoneError;
+
+pub trait Try {
+    type Ok;
+    type Error;
+    fn into_result(self) -> Result<Self::Ok, Self::Error>;
+}
+
+impl<T> Try for Option<T> {
+    type Ok = T;
+    type Error = NoneError;
+
+    #[inline]
+    fn into_result(self) -> Result<T, NoneError> {
+        self.ok_or(NoneError)
+    }
+}
+
+impl<T, E> Try for Result<T, E> {
+    type Ok = T;
+    type Error = E;
+
+    #[inline]
+    fn into_result(self) -> Self {
+        self
+    }
+}

embassy-net-enc28j60/src/header.rs

@@ -0,0 +1,30 @@
+register!(RxStatus, 0, u32, {
+    #[doc = "Indicates length of the received frame"]
+    byte_count @ 0..15,
+    #[doc = "Indicates a packet over 50,000 bit times occurred or that a packet was dropped since the last receive"]
+    long_event @ 16,
+    #[doc = "Indicates that at some time since the last receive, a carrier event was detected"]
+    carrier_event @ 18,
+    #[doc = "Indicates that frame CRC field value does not match the CRC calculated by the MAC"]
+    crc_error @ 20,
+    #[doc = "Indicates that frame length field value in the packet does not match the actual data byte length and specifies a valid length"]
+    length_check_error @ 21,
+    #[doc = "Indicates that frame type/length field was larger than 1500 bytes (type field)"]
+    length_out_of_range @ 22,
+    #[doc = "Indicates that at the packet had a valid CRC and no symbol errors"]
+    received_ok @ 23,
+    #[doc = "Indicates packet received had a valid Multicast address"]
+    multicast @ 24,
+    #[doc = "Indicates packet received had a valid Broadcast address."]
+    broadcast @ 25,
+    #[doc = "Indicates that after the end of this packet, an additional 1 to 7 bits were received"]
+    dribble_nibble @ 26,
+    #[doc = "Current frame was recognized as a control frame for having a valid type/length designating it as a control frame"]
+    receive_control_frame @ 27,
+    #[doc = "Current frame was recognized as a control frame containing a valid pause frame opcode and a valid destination address"]
+    receive_pause_control_frame @ 28,
+    #[doc = "Current frame was recognized as a control frame but it contained an unknown opcode"]
+    receive_unknown_opcode @ 29,
+    #[doc = "Current frame was recognized as a VLAN tagged frame"]
+    receive_vlan_type_detected @ 30,
+});

embassy-net-enc28j60/src/lib.rs

@@ -0,0 +1,717 @@
+#![no_std]
+#![doc = include_str!("../README.md")]
+#![warn(missing_docs)]
+
+// must go first.
+mod fmt;
+
+#[macro_use]
+mod macros;
+mod bank0;
+mod bank1;
+mod bank2;
+mod bank3;
+mod common;
+mod header;
+mod phy;
+mod traits;
+
+use core::cmp;
+use core::convert::TryInto;
+
+use embassy_net_driver::{Capabilities, HardwareAddress, LinkState, Medium};
+use embassy_time::Duration;
+use embedded_hal::digital::OutputPin;
+use embedded_hal::spi::{Operation, SpiDevice};
+use traits::U16Ext;
+
+// Total buffer size (see section 3.2)
+const BUF_SZ: u16 = 8 * 1024;
+
+// Maximum frame length
+const MAX_FRAME_LENGTH: u16 = 1518; // value recommended in the data sheet
+
+// Size of the Frame check sequence (32-bit CRC)
+const CRC_SZ: u16 = 4;
+
+// define the boundaries of the TX and RX buffers
+// to workaround errata #5 we do the opposite of what section 6.1 of the data sheet
+// says: we place the RX buffer at address 0 and the TX buffer after it
+const RXST: u16 = 0x0000;
+const RXND: u16 = 0x19ff;
+const TXST: u16 = 0x1a00;
+const _TXND: u16 = 0x1fff;
+
+const MTU: usize = 1514; // 1500 IP + 14 ethernet header
+
+/// ENC28J60 embassy-net driver
+pub struct Enc28j60<S, O> {
+    mac_addr: [u8; 6],
+
+    spi: S,
+    rst: Option<O>,
+
+    bank: Bank,
+
+    // address of the next packet in buffer memory
+    next_packet: u16,
+}
+
+impl<S, O> Enc28j60<S, O>
+where
+    S: SpiDevice,
+    O: OutputPin,
+{
+    /// Create a new ENC28J60 driver instance.
+    ///
+    /// The RST pin is optional. If None, reset will be done with a SPI
+    /// soft reset command, instead of via the RST pin.
+    pub fn new(spi: S, rst: Option<O>, mac_addr: [u8; 6]) -> Self {
+        let mut res = Self {
+            mac_addr,
+            spi,
+            rst,
+
+            bank: Bank::Bank0,
+            next_packet: RXST,
+        };
+        res.init();
+        res
+    }
+
+    fn init(&mut self) {
+        if let Some(rst) = &mut self.rst {
+            rst.set_low().unwrap();
+            embassy_time::block_for(Duration::from_millis(5));
+            rst.set_high().unwrap();
+            embassy_time::block_for(Duration::from_millis(5));
+        } else {
+            embassy_time::block_for(Duration::from_millis(5));
+            self.soft_reset();
+            embassy_time::block_for(Duration::from_millis(5));
+        }
+
+        debug!(
+            "enc28j60: erevid {=u8:x}",
+            self.read_control_register(bank3::Register::EREVID)
+        );
+        debug!("enc28j60: waiting for clk");
+        while common::ESTAT(self.read_control_register(common::Register::ESTAT)).clkrdy() == 0 {}
+        debug!("enc28j60: clk ok");
+
+        if self.read_control_register(bank3::Register::EREVID) == 0 {
+            panic!("ErevidIsZero");
+        }
+
+        // disable CLKOUT output
+        self.write_control_register(bank3::Register::ECOCON, 0);
+
+        self.init_rx();
+
+        // TX start
+        // "It is recommended that an even address be used for ETXST"
+        debug_assert_eq!(TXST % 2, 0);
+        self.write_control_register(bank0::Register::ETXSTL, TXST.low());
+        self.write_control_register(bank0::Register::ETXSTH, TXST.high());
+
+        // TX end is set in `transmit`
+
+        // MAC initialization (see section 6.5)
+        // 1. Set the MARXEN bit in MACON1 to enable the MAC to receive frames.
+        self.write_control_register(
+            bank2::Register::MACON1,
+            bank2::MACON1::default().marxen(1).passall(0).rxpaus(1).txpaus(1).bits(),
+        );
+
+        // 2. Configure the PADCFG, TXCRCEN and FULDPX bits of MACON3.
+        self.write_control_register(
+            bank2::Register::MACON3,
+            bank2::MACON3::default().frmlnen(1).txcrcen(1).padcfg(0b001).bits(),
+        );
+
+        // 4. Program the MAMXFL registers with the maximum frame length to be permitted to be
+        // received or transmitted
+        self.write_control_register(bank2::Register::MAMXFLL, MAX_FRAME_LENGTH.low());
+        self.write_control_register(bank2::Register::MAMXFLH, MAX_FRAME_LENGTH.high());
+
+        // 5. Configure the Back-to-Back Inter-Packet Gap register, MABBIPG.
+        // Use recommended value of 0x12
+        self.write_control_register(bank2::Register::MABBIPG, 0x12);
+
+        // 6. Configure the Non-Back-to-Back Inter-Packet Gap register low byte, MAIPGL.
+        // Use recommended value of 0x12
+        self.write_control_register(bank2::Register::MAIPGL, 0x12);
+        self.write_control_register(bank2::Register::MAIPGH, 0x0c);
+
+        // 9. Program the local MAC address into the MAADR1:MAADR6 registers
+        self.write_control_register(bank3::Register::MAADR1, self.mac_addr[0]);
+        self.write_control_register(bank3::Register::MAADR2, self.mac_addr[1]);
+        self.write_control_register(bank3::Register::MAADR3, self.mac_addr[2]);
+        self.write_control_register(bank3::Register::MAADR4, self.mac_addr[3]);
+        self.write_control_register(bank3::Register::MAADR5, self.mac_addr[4]);
+        self.write_control_register(bank3::Register::MAADR6, self.mac_addr[5]);
+
+        // Set the PHCON2.HDLDIS bit to prevent automatic loopback of the data which is transmitted
+        self.write_phy_register(phy::Register::PHCON2, phy::PHCON2::default().hdldis(1).bits());
+
+        // Globally enable interrupts
+        //self.bit_field_set(common::Register::EIE, common::EIE::mask().intie());
+
+        // Set the per packet control byte; we'll always use the value 0
+        self.write_buffer_memory(Some(TXST), &mut [0]);
+
+        // Enable reception
+        self.bit_field_set(common::Register::ECON1, common::ECON1::mask().rxen());
+    }
+
+    fn init_rx(&mut self) {
+        // RX start
+        // "It is recommended that the ERXST Pointer be programmed with an even address"
+        self.write_control_register(bank0::Register::ERXSTL, RXST.low());
+        self.write_control_register(bank0::Register::ERXSTH, RXST.high());
+
+        // RX read pointer
+        // NOTE Errata #14 so we are using an *odd* address here instead of ERXST
+        self.write_control_register(bank0::Register::ERXRDPTL, RXND.low());
+        self.write_control_register(bank0::Register::ERXRDPTH, RXND.high());
+
+        // RX end
+        self.write_control_register(bank0::Register::ERXNDL, RXND.low());
+        self.write_control_register(bank0::Register::ERXNDH, RXND.high());
+
+        // decrease the packet count to 0
+        while self.read_control_register(bank1::Register::EPKTCNT) != 0 {
+            self.bit_field_set(common::Register::ECON2, common::ECON2::mask().pktdec());
+        }
+
+        self.next_packet = RXST;
+    }
+
+    fn reset_rx(&mut self) {
+        self.bit_field_set(common::Register::ECON1, common::ECON1::mask().rxrst());
+        self.bit_field_clear(common::Register::ECON1, common::ECON1::mask().rxrst());
+        self.init_rx();
+        self.bit_field_set(common::Register::ECON1, common::ECON1::mask().rxen());
+    }
+
+    /// Flushes the transmit buffer, ensuring all pending transmissions have completed
+    /// NOTE: The returned packet *must* be `read` or `ignore`-d, otherwise this method will always
+    /// return `None` on subsequent invocations
+    pub fn receive<'a>(&mut self, buf: &'a mut [u8]) -> Option<&'a mut [u8]> {
+        if self.pending_packets() == 0 {
+            // Errata #6: we can't rely on PKTIF so we check PKTCNT
+            return None;
+        }
+
+        let curr_packet = self.next_packet;
+
+        // read out the first 6 bytes
+        let mut temp_buf = [0; 6];
+        self.read_buffer_memory(Some(curr_packet), &mut temp_buf);
+
+        // next packet pointer
+        let next_packet = u16::from_parts(temp_buf[0], temp_buf[1]);
+        // status vector
+        let status = header::RxStatus(u32::from_le_bytes(temp_buf[2..].try_into().unwrap()));
+        let len_with_crc = status.byte_count() as u16;
+
+        if len_with_crc < CRC_SZ || len_with_crc > 1600 || next_packet > RXND {
+            warn!("RX buffer corrupted, resetting RX logic to recover...");
+            self.reset_rx();
+            return None;
+        }
+
+        let len = len_with_crc - CRC_SZ;
+        self.read_buffer_memory(None, &mut buf[..len as usize]);
+
+        // update ERXRDPT
+        // due to Errata #14 we must write an odd address to ERXRDPT
+        // we know that ERXST = 0, that ERXND is odd and that next_packet is even
+        let rxrdpt = if self.next_packet < 1 || self.next_packet > RXND + 1 {
+            RXND
+        } else {
+            self.next_packet - 1
+        };
+        // "To move ERXRDPT, the host controller must write to ERXRDPTL first."
+        self.write_control_register(bank0::Register::ERXRDPTL, rxrdpt.low());
+        self.write_control_register(bank0::Register::ERXRDPTH, rxrdpt.high());
+
+        // decrease the packet count
+        self.bit_field_set(common::Register::ECON2, common::ECON2::mask().pktdec());
+
+        self.next_packet = next_packet;
+
+        Some(&mut buf[..len as usize])
+    }
+
+    fn wait_tx_ready(&mut self) {
+        for _ in 0u32..10000 {
+            if common::ECON1(self.read_control_register(common::Register::ECON1)).txrts() == 0 {
+                return;
+            }
+        }
+
+        // work around errata #12 by resetting the transmit logic before every new
+        // transmission
+        self.bit_field_set(common::Register::ECON1, common::ECON1::mask().txrst());
+        self.bit_field_clear(common::Register::ECON1, common::ECON1::mask().txrst());
+        //self.bit_field_clear(common::Register::EIR, {
+        //    let mask = common::EIR::mask();
+        //    mask.txerif() | mask.txif()
+        //});
+    }
+
+    /// Starts the transmission of `bytes`
+    ///
+    /// It's up to the caller to ensure that `bytes` is a valid Ethernet frame. The interface will
+    /// take care of appending a (4 byte) CRC to the frame and of padding the frame to the minimum
+    /// size allowed by the Ethernet specification (64 bytes, or 46 bytes of payload).
+    ///
+    /// NOTE This method will flush any previous transmission that's in progress
+    ///
+    /// # Panics
+    ///
+    /// If `bytes` length is greater than 1514, the maximum frame length allowed by the interface,
+    /// or greater than the transmit buffer
+    pub fn transmit(&mut self, bytes: &[u8]) {
+        assert!(bytes.len() <= self.mtu() as usize);
+
+        self.wait_tx_ready();
+
+        // NOTE the plus one is to not overwrite the per packet control byte
+        let wrpt = TXST + 1;
+
+        // 1. ETXST was set during initialization
+
+        // 2. write the frame to the IC memory
+        self.write_buffer_memory(Some(wrpt), bytes);
+
+        let txnd = wrpt + bytes.len() as u16 - 1;
+
+        // 3. Set the end address of the transmit buffer
+        self.write_control_register(bank0::Register::ETXNDL, txnd.low());
+        self.write_control_register(bank0::Register::ETXNDH, txnd.high());
+
+        // 4. reset interrupt flag
+        //self.bit_field_clear(common::Register::EIR, common::EIR::mask().txif());
+
+        // 5. start transmission
+        self.bit_field_set(common::Register::ECON1, common::ECON1::mask().txrts());
+
+        // Wait until transmission finishes
+        //while common::ECON1(self.read_control_register(common::Register::ECON1)).txrts() == 1 {}
+
+        /*
+        // read the transmit status vector
+        let mut tx_stat = [0; 7];
+        self.read_buffer_memory(None, &mut tx_stat);
+
+        let stat = common::ESTAT(self.read_control_register(common::Register::ESTAT));
+
+        if stat.txabrt() == 1 {
+            // work around errata #12 by reading the transmit status vector
+            if stat.latecol() == 1 || (tx_stat[2] & (1 << 5)) != 0 {
+                panic!("LateCollision")
+            } else {
+                panic!("TransmitAbort")
+            }
+        }*/
+    }
+
+    /// Get whether the link is up
+    pub fn is_link_up(&mut self) -> bool {
+        let bits = self.read_phy_register(phy::Register::PHSTAT2);
+        phy::PHSTAT2(bits).lstat() == 1
+    }
+
+    /// Returns the interface Maximum Transmission Unit (MTU)
+    ///
+    /// The value returned by this function will never exceed 1514 bytes. The actual value depends
+    /// on the memory assigned to the transmission buffer when initializing the device
+    pub fn mtu(&self) -> u16 {
+        cmp::min(BUF_SZ - RXND - 1, MAX_FRAME_LENGTH - CRC_SZ)
+    }
+
+    /* Miscellaneous */
+    /// Returns the number of packets that have been received but have not been processed yet
+    pub fn pending_packets(&mut self) -> u8 {
+        self.read_control_register(bank1::Register::EPKTCNT)
+    }
+
+    /// Adjusts the receive filter to *accept* these packet types
+    pub fn accept(&mut self, packets: &[Packet]) {
+        let mask = bank1::ERXFCON::mask();
+        let mut val = 0;
+        for packet in packets {
+            match packet {
+                Packet::Broadcast => val |= mask.bcen(),
+                Packet::Multicast => val |= mask.mcen(),
+                Packet::Unicast => val |= mask.ucen(),
+            }
+        }
+
+        self.bit_field_set(bank1::Register::ERXFCON, val)
+    }
+
+    /// Adjusts the receive filter to *ignore* these packet types
+    pub fn ignore(&mut self, packets: &[Packet]) {
+        let mask = bank1::ERXFCON::mask();
+        let mut val = 0;
+        for packet in packets {
+            match packet {
+                Packet::Broadcast => val |= mask.bcen(),
+                Packet::Multicast => val |= mask.mcen(),
+                Packet::Unicast => val |= mask.ucen(),
+            }
+        }
+
+        self.bit_field_clear(bank1::Register::ERXFCON, val)
+    }
+
+    /* Private */
+    /* Read */
+    fn read_control_register<R>(&mut self, register: R) -> u8
+    where
+        R: Into<Register>,
+    {
+        self._read_control_register(register.into())
+    }
+
+    fn _read_control_register(&mut self, register: Register) -> u8 {
+        self.change_bank(register);
+
+        if register.is_eth_register() {
+            let mut buffer = [Instruction::RCR.opcode() | register.addr(), 0];
+            self.spi.transfer_in_place(&mut buffer).unwrap();
+            buffer[1]
+        } else {
+            // MAC, MII regs need a dummy byte.
+            let mut buffer = [Instruction::RCR.opcode() | register.addr(), 0, 0];
+            self.spi.transfer_in_place(&mut buffer).unwrap();
+            buffer[2]
+        }
+    }
+
+    fn read_phy_register(&mut self, register: phy::Register) -> u16 {
+        // set PHY register address
+        self.write_control_register(bank2::Register::MIREGADR, register.addr());
+
+        // start read operation
+        self.write_control_register(bank2::Register::MICMD, bank2::MICMD::default().miird(1).bits());
+
+        // wait until the read operation finishes
+        while self.read_control_register(bank3::Register::MISTAT) & 0b1 != 0 {}
+
+        self.write_control_register(bank2::Register::MICMD, bank2::MICMD::default().miird(0).bits());
+
+        let l = self.read_control_register(bank2::Register::MIRDL);
+        let h = self.read_control_register(bank2::Register::MIRDH);
+        (l as u16) | (h as u16) << 8
+    }
+
+    /* Write */
+    fn _write_control_register(&mut self, register: Register, value: u8) {
+        self.change_bank(register);
+
+        let buffer = [Instruction::WCR.opcode() | register.addr(), value];
+        self.spi.write(&buffer).unwrap();
+    }
+
+    fn write_control_register<R>(&mut self, register: R, value: u8)
+    where
+        R: Into<Register>,
+    {
+        self._write_control_register(register.into(), value)
+    }
+
+    fn write_phy_register(&mut self, register: phy::Register, value: u16) {
+        // set PHY register address
+        self.write_control_register(bank2::Register::MIREGADR, register.addr());
+
+        self.write_control_register(bank2::Register::MIWRL, (value & 0xff) as u8);
+        // this starts the write operation
+        self.write_control_register(bank2::Register::MIWRH, (value >> 8) as u8);
+
+        // wait until the write operation finishes
+        while self.read_control_register(bank3::Register::MISTAT) & 0b1 != 0 {}
+    }
+
+    /* RMW */
+    fn modify_control_register<R, F>(&mut self, register: R, f: F)
+    where
+        F: FnOnce(u8) -> u8,
+        R: Into<Register>,
+    {
+        self._modify_control_register(register.into(), f)
+    }
+
+    fn _modify_control_register<F>(&mut self, register: Register, f: F)
+    where
+        F: FnOnce(u8) -> u8,
+    {
+        let r = self._read_control_register(register);
+        self._write_control_register(register, f(r))
+    }
+
+    /* Auxiliary */
+    fn change_bank(&mut self, register: Register) {
+        let bank = register.bank();
+
+        if let Some(bank) = bank {
+            if self.bank == bank {
+                // already on the register bank
+                return;
+            }
+
+            // change bank
+            self.bank = bank;
+            match bank {
+                Bank::Bank0 => self.bit_field_clear(common::Register::ECON1, 0b11),
+                Bank::Bank1 => self.modify_control_register(common::Register::ECON1, |r| (r & !0b11) | 0b01),
+                Bank::Bank2 => self.modify_control_register(common::Register::ECON1, |r| (r & !0b11) | 0b10),
+                Bank::Bank3 => self.bit_field_set(common::Register::ECON1, 0b11),
+            }
+        } else {
+            // common register
+        }
+    }
+
+    /* Primitive operations */
+    fn bit_field_clear<R>(&mut self, register: R, mask: u8)
+    where
+        R: Into<Register>,
+    {
+        self._bit_field_clear(register.into(), mask)
+    }
+
+    fn _bit_field_clear(&mut self, register: Register, mask: u8) {
+        debug_assert!(register.is_eth_register());
+
+        self.change_bank(register);
+
+        self.spi
+            .write(&[Instruction::BFC.opcode() | register.addr(), mask])
+            .unwrap();
+    }
+
+    fn bit_field_set<R>(&mut self, register: R, mask: u8)
+    where
+        R: Into<Register>,
+    {
+        self._bit_field_set(register.into(), mask)
+    }
+
+    fn _bit_field_set(&mut self, register: Register, mask: u8) {
+        debug_assert!(register.is_eth_register());
+
+        self.change_bank(register);
+
+        self.spi
+            .write(&[Instruction::BFS.opcode() | register.addr(), mask])
+            .unwrap();
+    }
+
+    fn read_buffer_memory(&mut self, addr: Option<u16>, buf: &mut [u8]) {
+        if let Some(addr) = addr {
+            self.write_control_register(bank0::Register::ERDPTL, addr.low());
+            self.write_control_register(bank0::Register::ERDPTH, addr.high());
+        }
+
+        self.spi
+            .transaction(&mut [Operation::Write(&[Instruction::RBM.opcode()]), Operation::Read(buf)])
+            .unwrap();
+    }
+
+    fn soft_reset(&mut self) {
+        self.spi.write(&[Instruction::SRC.opcode()]).unwrap();
+    }
+
+    fn write_buffer_memory(&mut self, addr: Option<u16>, buffer: &[u8]) {
+        if let Some(addr) = addr {
+            self.write_control_register(bank0::Register::EWRPTL, addr.low());
+            self.write_control_register(bank0::Register::EWRPTH, addr.high());
+        }
+
+        self.spi
+            .transaction(&mut [Operation::Write(&[Instruction::WBM.opcode()]), Operation::Write(buffer)])
+            .unwrap();
+    }
+}
+
+#[derive(Clone, Copy, PartialEq)]
+enum Bank {
+    Bank0,
+    Bank1,
+    Bank2,
+    Bank3,
+}
+
+#[derive(Clone, Copy)]
+enum Instruction {
+    /// Read Control Register
+    RCR = 0b000_00000,
+    /// Read Buffer Memory
+    RBM = 0b001_11010,
+    /// Write Control Register
+    WCR = 0b010_00000,
+    /// Write Buffer Memory
+    WBM = 0b011_11010,
+    /// Bit Field Set
+    BFS = 0b100_00000,
+    /// Bit Field Clear
+    BFC = 0b101_00000,
+    /// System Reset Command
+    SRC = 0b111_11111,
+}
+
+impl Instruction {
+    fn opcode(&self) -> u8 {
+        *self as u8
+    }
+}
+
+#[derive(Clone, Copy)]
+enum Register {
+    Bank0(bank0::Register),
+    Bank1(bank1::Register),
+    Bank2(bank2::Register),
+    Bank3(bank3::Register),
+    Common(common::Register),
+}
+
+impl Register {
+    fn addr(&self) -> u8 {
+        match *self {
+            Register::Bank0(r) => r.addr(),
+            Register::Bank1(r) => r.addr(),
+            Register::Bank2(r) => r.addr(),
+            Register::Bank3(r) => r.addr(),
+            Register::Common(r) => r.addr(),
+        }
+    }
+
+    fn bank(&self) -> Option<Bank> {
+        Some(match *self {
+            Register::Bank0(_) => Bank::Bank0,
+            Register::Bank1(_) => Bank::Bank1,
+            Register::Bank2(_) => Bank::Bank2,
+            Register::Bank3(_) => Bank::Bank3,
+            Register::Common(_) => return None,
+        })
+    }
+
+    fn is_eth_register(&self) -> bool {
+        match *self {
+            Register::Bank0(r) => r.is_eth_register(),
+            Register::Bank1(r) => r.is_eth_register(),
+            Register::Bank2(r) => r.is_eth_register(),
+            Register::Bank3(r) => r.is_eth_register(),
+            Register::Common(r) => r.is_eth_register(),
+        }
+    }
+}
+
+/// Packet type, used to configure receive filters
+#[non_exhaustive]
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum Packet {
+    /// Broadcast packets
+    Broadcast,
+    /// Multicast packets
+    Multicast,
+    /// Unicast packets
+    Unicast,
+}
+
+static mut TX_BUF: [u8; MTU] = [0; MTU];
+static mut RX_BUF: [u8; MTU] = [0; MTU];
+
+impl<S, O> embassy_net_driver::Driver for Enc28j60<S, O>
+where
+    S: SpiDevice,
+    O: OutputPin,
+{
+    type RxToken<'a> = RxToken<'a>
+    where
+        Self: 'a;
+
+    type TxToken<'a> = TxToken<'a, S, O>
+    where
+        Self: 'a;
+
+    fn receive(&mut self, cx: &mut core::task::Context) -> Option<(Self::RxToken<'_>, Self::TxToken<'_>)> {
+        let rx_buf = unsafe { &mut RX_BUF };
+        let tx_buf = unsafe { &mut TX_BUF };
+        if let Some(pkt) = self.receive(rx_buf) {
+            let n = pkt.len();
+            Some((RxToken { buf: &mut pkt[..n] }, TxToken { buf: tx_buf, eth: self }))
+        } else {
+            cx.waker().wake_by_ref();
+            None
+        }
+    }
+
+    fn transmit(&mut self, _cx: &mut core::task::Context) -> Option<Self::TxToken<'_>> {
+        let tx_buf = unsafe { &mut TX_BUF };
+        Some(TxToken { buf: tx_buf, eth: self })
+    }
+
+    fn link_state(&mut self, cx: &mut core::task::Context) -> LinkState {
+        cx.waker().wake_by_ref();
+        match self.is_link_up() {
+            true => LinkState::Up,
+            false => LinkState::Down,
+        }
+    }
+
+    fn capabilities(&self) -> Capabilities {
+        let mut caps = Capabilities::default();
+        caps.max_transmission_unit = MTU;
+        caps.medium = Medium::Ethernet;
+        caps
+    }
+
+    fn hardware_address(&self) -> HardwareAddress {
+        HardwareAddress::Ethernet(self.mac_addr)
+    }
+}
+
+/// embassy-net RX token.
+pub struct RxToken<'a> {
+    buf: &'a mut [u8],
+}
+
+impl<'a> embassy_net_driver::RxToken for RxToken<'a> {
+    fn consume<R, F>(self, f: F) -> R
+    where
+        F: FnOnce(&mut [u8]) -> R,
+    {
+        f(self.buf)
+    }
+}
+
+/// embassy-net TX token.
+pub struct TxToken<'a, S, O>
+where
+    S: SpiDevice,
+    O: OutputPin,
+{
+    eth: &'a mut Enc28j60<S, O>,
+    buf: &'a mut [u8],
+}
+
+impl<'a, S, O> embassy_net_driver::TxToken for TxToken<'a, S, O>
+where
+    S: SpiDevice,
+    O: OutputPin,
+{
+    fn consume<R, F>(self, len: usize, f: F) -> R
+    where
+        F: FnOnce(&mut [u8]) -> R,
+    {
+        assert!(len <= self.buf.len());
+        let r = f(&mut self.buf[..len]);
+        self.eth.transmit(&self.buf[..len]);
+        r
+    }
+}

embassy-net-enc28j60/src/macros.rs

@@ -0,0 +1,89 @@
+macro_rules! register {
+    ($REGISTER:ident, $reset_value:expr, $uxx:ty, {
+        $(#[$($attr:tt)*] $bitfield:ident @ $range:expr,)+
+    }) => {
+        #[derive(Clone, Copy)]
+        pub(crate) struct $REGISTER<MODE> {
+            bits: $uxx,
+            _mode: ::core::marker::PhantomData<MODE>,
+        }
+
+        impl $REGISTER<super::traits::Mask> {
+            #[allow(dead_code)]
+            pub(crate) fn mask() -> $REGISTER<super::traits::Mask> {
+                $REGISTER { bits: 0, _mode: ::core::marker::PhantomData }
+            }
+
+            $(
+                #[allow(dead_code)]
+                pub(crate) fn $bitfield(&self) -> $uxx {
+                    use super::traits::OffsetSize;
+
+                    let size = $range.size();
+                    let offset = $range.offset();
+                    ((1 << size) - 1) << offset
+                }
+            )+
+        }
+
+        impl ::core::default::Default for $REGISTER<super::traits::W> {
+            fn default() -> Self {
+                $REGISTER { bits: $reset_value, _mode: ::core::marker::PhantomData }
+            }
+        }
+
+        #[allow(non_snake_case)]
+        #[allow(dead_code)]
+        pub(crate) fn $REGISTER(bits: $uxx) -> $REGISTER<super::traits::R> {
+            $REGISTER { bits, _mode: ::core::marker::PhantomData }
+        }
+
+        impl $REGISTER<super::traits::R> {
+            #[allow(dead_code)]
+            pub(crate) fn modify(self) -> $REGISTER<super::traits::W> {
+                $REGISTER { bits: self.bits, _mode: ::core::marker::PhantomData }
+            }
+
+            $(
+                #[$($attr)*]
+                #[allow(dead_code)]
+                pub(crate) fn $bitfield(&self) -> $uxx {
+                    use super::traits::OffsetSize;
+
+                    let offset = $range.offset();
+                    let size = $range.size();
+                    let mask = (1 << size) - 1;
+
+                    (self.bits >> offset) & mask
+                }
+            )+
+        }
+
+        impl $REGISTER<super::traits::W> {
+            #[allow(dead_code)]
+            pub(crate) fn bits(self) -> $uxx {
+                self.bits
+            }
+
+            $(
+                #[$($attr)*]
+                #[allow(dead_code)]
+                pub(crate) fn $bitfield(&mut self, mut bits: $uxx) -> &mut Self {
+                    use super::traits::OffsetSize;
+
+                    let offset = $range.offset();
+                    let size = $range.size();
+                    let mask = (1 << size) - 1;
+
+                    debug_assert!(bits <= mask);
+                    bits &= mask;
+
+                    self.bits &= !(mask << offset);
+                    self.bits |= bits << offset;
+
+                    self
+                }
+            )+
+        }
+    }
+}

embassy-net-enc28j60/src/phy.rs

@@ -0,0 +1,35 @@
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum Register {
+    PHCON1 = 0x00,
+    PHSTAT1 = 0x01,
+    PHID1 = 0x02,
+    PHID2 = 0x03,
+    PHCON2 = 0x10,
+    PHSTAT2 = 0x11,
+    PHIE = 0x12,
+    PHIR = 0x13,
+    PHLCON = 0x14,
+}
+
+impl Register {
+    pub(crate) fn addr(&self) -> u8 {
+        *self as u8
+    }
+}
+
+register!(PHCON2, 0, u16, {
+    #[doc = "PHY Half-Duplex Loopback Disable bit"]
+    hdldis @ 8,
+    #[doc = "Jabber Correction Disable bit"]
+    jabber @ 10,
+    #[doc = "Twisted-Pair Transmitter Disable bit"]
+    txdis @ 13,
+    #[doc = "PHY Force Linkup bit"]
+    frclnk @ 14,
+});
+
+register!(PHSTAT2, 0, u16, {
+    #[doc = "Link Status bit"]
+    lstat @ 10,
+});

embassy-net-enc28j60/src/traits.rs

@@ -0,0 +1,57 @@
+use core::ops::Range;
+
+pub(crate) trait OffsetSize {
+    fn offset(self) -> u8;
+    fn size(self) -> u8;
+}
+
+impl OffsetSize for u8 {
+    fn offset(self) -> u8 {
+        self
+    }
+
+    fn size(self) -> u8 {
+        1
+    }
+}
+
+impl OffsetSize for Range<u8> {
+    fn offset(self) -> u8 {
+        self.start
+    }
+
+    fn size(self) -> u8 {
+        self.end - self.start
+    }
+}
+
+pub(crate) trait U16Ext {
+    fn from_parts(low: u8, high: u8) -> Self;
+
+    fn low(self) -> u8;
+
+    fn high(self) -> u8;
+}
+
+impl U16Ext for u16 {
+    fn from_parts(low: u8, high: u8) -> u16 {
+        ((high as u16) << 8) + low as u16
+    }
+
+    fn low(self) -> u8 {
+        (self & 0xff) as u8
+    }
+
+    fn high(self) -> u8 {
+        (self >> 8) as u8
+    }
+}
+
+#[derive(Clone, Copy)]
+pub struct Mask;
+
+#[derive(Clone, Copy)]
+pub struct R;
+
+#[derive(Clone, Copy)]
+pub struct W;

embassy-net-esp-hosted/Cargo.toml

@@ -12,8 +12,8 @@ embassy-sync = { version = "0.2.0", path = "../embassy-sync"}
 embassy-futures = { version = "0.1.0", path = "../embassy-futures"}
 embassy-net-driver-channel = { version = "0.1.0", path = "../embassy-net-driver-channel"}
 
-embedded-hal = { version = "1.0.0-alpha.11" }
+embedded-hal = { version = "1.0.0-rc.1" }
-embedded-hal-async = { version = "=0.2.0-alpha.2" }
+embedded-hal-async = { version = "=1.0.0-rc.1" }
 
 noproto = { git="https://github.com/embassy-rs/noproto", default-features = false, features = ["derive"] }
 #noproto = { version = "0.1", path = "/home/dirbaio/noproto", default-features = false, features = ["derive"] }

embassy-net-esp-hosted/src/control.rs

@@ -5,9 +5,12 @@ use heapless::String;
 use crate::ioctl::Shared;
 use crate::proto::{self, CtrlMsg};
 
-#[derive(Debug)]
+#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub struct Error {
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-    pub status: u32,
+pub enum Error {
+    Failed(u32),
+    Timeout,
+    Internal,
 }
 
 pub struct Control<'a> {
@@ -23,58 +26,78 @@ enum WifiMode {
     ApSta = 3,
 }
 
+macro_rules! ioctl {
+    ($self:ident, $req_variant:ident, $resp_variant:ident, $req:ident, $resp:ident) => {
+        let mut msg = proto::CtrlMsg {
+            msg_id: proto::CtrlMsgId::$req_variant as _,
+            msg_type: proto::CtrlMsgType::Req as _,
+            payload: Some(proto::CtrlMsgPayload::$req_variant($req)),
+        };
+        $self.ioctl(&mut msg).await?;
+        let Some(proto::CtrlMsgPayload::$resp_variant($resp)) = msg.payload else {
+            warn!("unexpected response variant");
+            return Err(Error::Internal);
+        };
+        if $resp.resp != 0 {
+            return Err(Error::Failed($resp.resp));
+        }
+    };
+}
+
 impl<'a> Control<'a> {
     pub(crate) fn new(state_ch: ch::StateRunner<'a>, shared: &'a Shared) -> Self {
         Self { state_ch, shared }
     }
 
-    pub async fn init(&mut self) {
+    pub async fn init(&mut self) -> Result<(), Error> {
         debug!("wait for init event...");
         self.shared.init_wait().await;
 
-        debug!("set wifi mode");
+        debug!("set heartbeat");
-        self.set_wifi_mode(WifiMode::Sta as _).await;
+        self.set_heartbeat(10).await?;
 
-        let mac_addr = self.get_mac_addr().await;
+        debug!("set wifi mode");
+        self.set_wifi_mode(WifiMode::Sta as _).await?;
+
+        let mac_addr = self.get_mac_addr().await?;
         debug!("mac addr: {:02x}", mac_addr);
         self.state_ch.set_ethernet_address(mac_addr);
+
+        Ok(())
     }
 
-    pub async fn join(&mut self, ssid: &str, password: &str) {
+    pub async fn connect(&mut self, ssid: &str, password: &str) -> Result<(), Error> {
-        let req = proto::CtrlMsg {
+        let req = proto::CtrlMsgReqConnectAp {
-            msg_id: proto::CtrlMsgId::ReqConnectAp as _,
-            msg_type: proto::CtrlMsgType::Req as _,
-            payload: Some(proto::CtrlMsgPayload::ReqConnectAp(proto::CtrlMsgReqConnectAp {
             ssid: String::from(ssid),
             pwd: String::from(password),
             bssid: String::new(),
             listen_interval: 3,
             is_wpa3_supported: false,
-            })),
         };
-        let resp = self.ioctl(req).await;
+        ioctl!(self, ReqConnectAp, RespConnectAp, req, resp);
-        let proto::CtrlMsgPayload::RespConnectAp(resp) = resp.payload.unwrap() else {
-            panic!("unexpected resp")
-        };
-        assert_eq!(resp.resp, 0);
         self.state_ch.set_link_state(LinkState::Up);
+        Ok(())
     }
 
-    async fn get_mac_addr(&mut self) -> [u8; 6] {
+    pub async fn disconnect(&mut self) -> Result<(), Error> {
-        let req = proto::CtrlMsg {
+        let req = proto::CtrlMsgReqGetStatus {};
-            msg_id: proto::CtrlMsgId::ReqGetMacAddress as _,
+        ioctl!(self, ReqDisconnectAp, RespDisconnectAp, req, resp);
-            msg_type: proto::CtrlMsgType::Req as _,
+        self.state_ch.set_link_state(LinkState::Down);
-            payload: Some(proto::CtrlMsgPayload::ReqGetMacAddress(
+        Ok(())
-                proto::CtrlMsgReqGetMacAddress {
+    }
+
+    /// duration in seconds, clamped to [10, 3600]
+    async fn set_heartbeat(&mut self, duration: u32) -> Result<(), Error> {
+        let req = proto::CtrlMsgReqConfigHeartbeat { enable: true, duration };
+        ioctl!(self, ReqConfigHeartbeat, RespConfigHeartbeat, req, resp);
+        Ok(())
+    }
+
+    async fn get_mac_addr(&mut self) -> Result<[u8; 6], Error> {
+        let req = proto::CtrlMsgReqGetMacAddress {
             mode: WifiMode::Sta as _,
-                },
-            )),
         };
-        let resp = self.ioctl(req).await;
+        ioctl!(self, ReqGetMacAddress, RespGetMacAddress, req, resp);
-        let proto::CtrlMsgPayload::RespGetMacAddress(resp) = resp.payload.unwrap() else {
-            panic!("unexpected resp")
-        };
-        assert_eq!(resp.resp, 0);
 
         // WHY IS THIS A STRING? WHYYYY
         fn nibble_from_hex(b: u8) -> u8 {
@@ -88,32 +111,32 @@ impl<'a> Control<'a> {
 
         let mac = resp.mac.as_bytes();
         let mut res = [0; 6];
-        assert_eq!(mac.len(), 17);
+        if mac.len() != 17 {
+            warn!("unexpected MAC respnse length");
+            return Err(Error::Internal);
+        }
         for (i, b) in res.iter_mut().enumerate() {
             *b = (nibble_from_hex(mac[i * 3]) << 4) | nibble_from_hex(mac[i * 3 + 1])
         }
-        res
+        Ok(res)
     }
 
-    async fn set_wifi_mode(&mut self, mode: u32) {
+    async fn set_wifi_mode(&mut self, mode: u32) -> Result<(), Error> {
-        let req = proto::CtrlMsg {
+        let req = proto::CtrlMsgReqSetMode { mode };
-            msg_id: proto::CtrlMsgId::ReqSetWifiMode as _,
+        ioctl!(self, ReqSetWifiMode, RespSetWifiMode, req, resp);
-            msg_type: proto::CtrlMsgType::Req as _,
+
-            payload: Some(proto::CtrlMsgPayload::ReqSetWifiMode(proto::CtrlMsgReqSetMode { mode })),
+        Ok(())
-        };
-        let resp = self.ioctl(req).await;
-        let proto::CtrlMsgPayload::RespSetWifiMode(resp) = resp.payload.unwrap() else {
-            panic!("unexpected resp")
-        };
-        assert_eq!(resp.resp, 0);
     }
 
-    async fn ioctl(&mut self, req: CtrlMsg) -> CtrlMsg {
+    async fn ioctl(&mut self, msg: &mut CtrlMsg) -> Result<(), Error> {
-        debug!("ioctl req: {:?}", &req);
+        debug!("ioctl req: {:?}", &msg);
 
         let mut buf = [0u8; 128];
 
-        let req_len = noproto::write(&req, &mut buf).unwrap();
+        let req_len = noproto::write(msg, &mut buf).map_err(|_| {
+            warn!("failed to serialize control request");
+            Error::Internal
+        })?;
 
         struct CancelOnDrop<'a>(&'a Shared);
 
@@ -135,9 +158,12 @@ impl<'a> Control<'a> {
 
         ioctl.defuse();
 
-        let res = noproto::read(&buf[..resp_len]).unwrap();
+        *msg = noproto::read(&buf[..resp_len]).map_err(|_| {
-        debug!("ioctl resp: {:?}", &res);
+            warn!("failed to serialize control request");
+            Error::Internal
+        })?;
+        debug!("ioctl resp: {:?}", msg);
 
-        res
+        Ok(())
     }
 }

embassy-net-esp-hosted/src/lib.rs

@@ -1,17 +1,15 @@
 #![no_std]
 
-use control::Control;
+use embassy_futures::select::{select4, Either4};
-use embassy_futures::select::{select3, Either3};
 use embassy_net_driver_channel as ch;
+use embassy_net_driver_channel::driver::LinkState;
 use embassy_time::{Duration, Instant, Timer};
 use embedded_hal::digital::{InputPin, OutputPin};
 use embedded_hal_async::digital::Wait;
 use embedded_hal_async::spi::SpiDevice;
-use ioctl::Shared;
-use proto::CtrlMsg;
 
-use crate::ioctl::PendingIoctl;
+use crate::ioctl::{PendingIoctl, Shared};
-use crate::proto::CtrlMsgPayload;
+use crate::proto::{CtrlMsg, CtrlMsgPayload};
 
 mod proto;
 
@@ -21,6 +19,8 @@ mod fmt;
 mod control;
 mod ioctl;
 
+pub use control::*;
+
 const MTU: usize = 1514;
 
 macro_rules! impl_bytes {
@@ -95,6 +95,7 @@ enum InterfaceType {
 }
 
 const MAX_SPI_BUFFER_SIZE: usize = 1600;
+const HEARTBEAT_MAX_GAP: Duration = Duration::from_secs(20);
 
 pub struct State {
     shared: Shared,
@@ -129,12 +130,14 @@ where
 
     let mut runner = Runner {
         ch: ch_runner,
+        state_ch,
         shared: &state.shared,
         next_seq: 1,
         handshake,
         ready,
         reset,
         spi,
+        heartbeat_deadline: Instant::now() + HEARTBEAT_MAX_GAP,
     };
     runner.init().await;
 
@@ -143,9 +146,11 @@ where
 
 pub struct Runner<'a, SPI, IN, OUT> {
     ch: ch::Runner<'a, MTU>,
+    state_ch: ch::StateRunner<'a>,
     shared: &'a Shared,
 
     next_seq: u16,
+    heartbeat_deadline: Instant,
 
     spi: SPI,
     handshake: IN,
@@ -177,9 +182,10 @@ where
             let ioctl = self.shared.ioctl_wait_pending();
             let tx = self.ch.tx_buf();
             let ev = async { self.ready.wait_for_high().await.unwrap() };
+            let hb = Timer::at(self.heartbeat_deadline);
 
-            match select3(ioctl, tx, ev).await {
+            match select4(ioctl, tx, ev, hb).await {
-                Either3::First(PendingIoctl { buf, req_len }) => {
+                Either4::First(PendingIoctl { buf, req_len }) => {
                     tx_buf[12..24].copy_from_slice(b"\x01\x08\x00ctrlResp\x02");
                     tx_buf[24..26].copy_from_slice(&(req_len as u16).to_le_bytes());
                     tx_buf[26..][..req_len].copy_from_slice(&unsafe { &*buf }[..req_len]);
@@ -198,7 +204,7 @@ where
                     header.checksum = checksum(&tx_buf[..26 + req_len]);
                     tx_buf[0..12].copy_from_slice(&header.to_bytes());
                 }
-                Either3::Second(packet) => {
+                Either4::Second(packet) => {
                     tx_buf[12..][..packet.len()].copy_from_slice(packet);
 
                     let mut header = PayloadHeader {
@@ -217,9 +223,12 @@ where
 
                     self.ch.tx_done();
                 }
-                Either3::Third(()) => {
+                Either4::Third(()) => {
                     tx_buf[..PayloadHeader::SIZE].fill(0);
                 }
+                Either4::Fourth(()) => {
+                    panic!("heartbeat from esp32 stopped")
+                }
             }
 
             if tx_buf[0] != 0 {
@@ -308,7 +317,7 @@ where
         }
     }
 
-    fn handle_event(&self, data: &[u8]) {
+    fn handle_event(&mut self, data: &[u8]) {
         let Ok(event) = noproto::read::<CtrlMsg>(data) else {
             warn!("failed to parse event");
             return;
@@ -323,6 +332,11 @@ where
 
         match payload {
             CtrlMsgPayload::EventEspInit(_) => self.shared.init_done(),
+            CtrlMsgPayload::EventHeartbeat(_) => self.heartbeat_deadline = Instant::now() + HEARTBEAT_MAX_GAP,
+            CtrlMsgPayload::EventStationDisconnectFromAp(e) => {
+                info!("disconnected, code {}", e.resp);
+                self.state_ch.set_link_state(LinkState::Down);
+            }
             _ => {}
         }
     }

embassy-net-ppp/Cargo.toml

@@ -0,0 +1,28 @@
+[package]
+name = "embassy-net-ppp"
+version = "0.1.0"
+description = "embassy-net driver for PPP over Serial"
+keywords = ["embedded", "ppp", "embassy-net", "embedded-hal-async", "ethernet", "async"]
+categories = ["embedded", "hardware-support", "no-std", "network-programming", "async"]
+license = "MIT OR Apache-2.0"
+edition = "2021"
+
+[features]
+defmt = ["dep:defmt", "ppproto/defmt"]
+log = ["dep:log", "ppproto/log"]
+
+[dependencies]
+defmt = { version = "0.3", optional = true }
+log = { version = "0.4.14", optional = true }
+
+embedded-io-async = { version = "0.5.0" }
+embassy-net-driver-channel = { version = "0.1.0", path = "../embassy-net-driver-channel" }
+embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
+ppproto = { version = "0.1.1"}
+embassy-sync = { version = "0.2.0", path = "../embassy-sync" }
+
+[package.metadata.embassy_docs]
+src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-ppp-v$VERSION/embassy-net-ppp/src/"
+src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-ppp/src/"
+target = "thumbv7em-none-eabi"
+features = ["defmt"]

embassy-net-ppp/README.md

@@ -0,0 +1,19 @@
+# `embassy-net-ppp`
+
+[`embassy-net`](https://crates.io/crates/embassy-net) integration for PPP over Serial.
+
+## Interoperability
+
+This crate can run on any executor.
+
+It supports any serial port implementing [`embedded-io-async`](https://crates.io/crates/embedded-io-async).
+
+## License
+
+This work is licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.

embassy-net-ppp/src/fmt.rs

@@ -0,0 +1,257 @@
+#![macro_use]
+#![allow(unused_macros)]
+
+use core::fmt::{Debug, Display, LowerHex};
+
+#[cfg(all(feature = "defmt", feature = "log"))]
+compile_error!("You may not enable both `defmt` and `log` features.");
+
+macro_rules! assert {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::assert!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::assert!($($x)*);
+        }
+    };
+}
+
+macro_rules! assert_eq {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::assert_eq!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::assert_eq!($($x)*);
+        }
+    };
+}
+
+macro_rules! assert_ne {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::assert_ne!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::assert_ne!($($x)*);
+        }
+    };
+}
+
+macro_rules! debug_assert {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::debug_assert!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug_assert!($($x)*);
+        }
+    };
+}
+
+macro_rules! debug_assert_eq {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::debug_assert_eq!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug_assert_eq!($($x)*);
+        }
+    };
+}
+
+macro_rules! debug_assert_ne {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::debug_assert_ne!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug_assert_ne!($($x)*);
+        }
+    };
+}
+
+macro_rules! todo {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::todo!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::todo!($($x)*);
+        }
+    };
+}
+
+#[cfg(not(feature = "defmt"))]
+macro_rules! unreachable {
+    ($($x:tt)*) => {
+        ::core::unreachable!($($x)*)
+    };
+}
+
+#[cfg(feature = "defmt")]
+macro_rules! unreachable {
+    ($($x:tt)*) => {
+        ::defmt::unreachable!($($x)*);
+    };
+}
+
+macro_rules! panic {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::panic!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::panic!($($x)*);
+        }
+    };
+}
+
+macro_rules! trace {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::trace!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::trace!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+macro_rules! debug {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::debug!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+macro_rules! info {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::info!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::info!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+macro_rules! warn {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::warn!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::warn!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+macro_rules! error {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::error!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::error!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+#[cfg(feature = "defmt")]
+macro_rules! unwrap {
+    ($($x:tt)*) => {
+        ::defmt::unwrap!($($x)*)
+    };
+}
+
+#[cfg(not(feature = "defmt"))]
+macro_rules! unwrap {
+    ($arg:expr) => {
+        match $crate::fmt::Try::into_result($arg) {
+            ::core::result::Result::Ok(t) => t,
+            ::core::result::Result::Err(e) => {
+                ::core::panic!("unwrap of `{}` failed: {:?}", ::core::stringify!($arg), e);
+            }
+        }
+    };
+    ($arg:expr, $($msg:expr),+ $(,)? ) => {
+        match $crate::fmt::Try::into_result($arg) {
+            ::core::result::Result::Ok(t) => t,
+            ::core::result::Result::Err(e) => {
+                ::core::panic!("unwrap of `{}` failed: {}: {:?}", ::core::stringify!($arg), ::core::format_args!($($msg,)*), e);
+            }
+        }
+    }
+}
+
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+pub struct NoneError;
+
+pub trait Try {
+    type Ok;
+    type Error;
+    fn into_result(self) -> Result<Self::Ok, Self::Error>;
+}
+
+impl<T> Try for Option<T> {
+    type Ok = T;
+    type Error = NoneError;
+
+    #[inline]
+    fn into_result(self) -> Result<T, NoneError> {
+        self.ok_or(NoneError)
+    }
+}
+
+impl<T, E> Try for Result<T, E> {
+    type Ok = T;
+    type Error = E;
+
+    #[inline]
+    fn into_result(self) -> Self {
+        self
+    }
+}
+
+pub struct Bytes<'a>(pub &'a [u8]);
+
+impl<'a> Debug for Bytes<'a> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "{:#02x?}", self.0)
+    }
+}
+
+impl<'a> Display for Bytes<'a> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "{:#02x?}", self.0)
+    }
+}
+
+impl<'a> LowerHex for Bytes<'a> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "{:#02x?}", self.0)
+    }
+}
+
+#[cfg(feature = "defmt")]
+impl<'a> defmt::Format for Bytes<'a> {
+    fn format(&self, fmt: defmt::Formatter) {
+        defmt::write!(fmt, "{:02x}", self.0)
+    }
+}

embassy-net-ppp/src/lib.rs

@@ -0,0 +1,180 @@
+#![no_std]
+#![warn(missing_docs)]
+#![doc = include_str!("../README.md")]
+
+// must be first
+mod fmt;
+
+use core::convert::Infallible;
+use core::mem::MaybeUninit;
+
+use embassy_futures::select::{select, Either};
+use embassy_net_driver_channel as ch;
+use embassy_net_driver_channel::driver::LinkState;
+use embedded_io_async::{BufRead, Write, WriteAllError};
+use ppproto::pppos::{BufferFullError, PPPoS, PPPoSAction};
+pub use ppproto::{Config, Ipv4Status};
+
+const MTU: usize = 1500;
+
+/// Type alias for the embassy-net driver.
+pub type Device<'d> = embassy_net_driver_channel::Device<'d, MTU>;
+
+/// Internal state for the embassy-net integration.
+pub struct State<const N_RX: usize, const N_TX: usize> {
+    ch_state: ch::State<MTU, N_RX, N_TX>,
+}
+
+impl<const N_RX: usize, const N_TX: usize> State<N_RX, N_TX> {
+    /// Create a new `State`.
+    pub const fn new() -> Self {
+        Self {
+            ch_state: ch::State::new(),
+        }
+    }
+}
+
+/// Background runner for the driver.
+///
+/// You must call `.run()` in a background task for the driver to operate.
+pub struct Runner<'d> {
+    ch: ch::Runner<'d, MTU>,
+}
+
+/// Error returned by [`Runner::run`].
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum RunError<E> {
+    /// Reading from the serial port failed.
+    Read(E),
+    /// Writing to the serial port failed.
+    Write(E),
+    /// Writing to the serial port wrote zero bytes, indicating it can't accept more data.
+    WriteZero,
+    /// Writing to the serial got EOF.
+    Eof,
+}
+
+impl<E> From<WriteAllError<E>> for RunError<E> {
+    fn from(value: WriteAllError<E>) -> Self {
+        match value {
+            WriteAllError::Other(e) => Self::Write(e),
+            WriteAllError::WriteZero => Self::WriteZero,
+        }
+    }
+}
+
+impl<'d> Runner<'d> {
+    /// You must call this in a background task for the driver to operate.
+    ///
+    /// If reading/writing to the underlying serial port fails, the link state
+    /// is set to Down and the error is returned.
+    ///
+    /// It is allowed to cancel this function's future (i.e. drop it). This will terminate
+    /// the PPP connection and set the link state to Down.
+    ///
+    /// After this function returns or is canceled, you can call it again to establish
+    /// a new PPP connection.
+    pub async fn run<RW: BufRead + Write>(
+        &mut self,
+        mut rw: RW,
+        config: ppproto::Config<'_>,
+        mut on_ipv4_up: impl FnMut(Ipv4Status),
+    ) -> Result<Infallible, RunError<RW::Error>> {
+        let mut ppp = PPPoS::new(config);
+        ppp.open().unwrap();
+
+        let (state_chan, mut rx_chan, mut tx_chan) = self.ch.borrow_split();
+        state_chan.set_link_state(LinkState::Down);
+        let _ondrop = OnDrop::new(|| state_chan.set_link_state(LinkState::Down));
+
+        let mut rx_buf = [0; 2048];
+        let mut tx_buf = [0; 2048];
+
+        let mut needs_poll = true;
+        let mut was_up = false;
+
+        loop {
+            let rx_fut = async {
+                let buf = rx_chan.rx_buf().await;
+                let rx_data = match needs_poll {
+                    true => &[][..],
+                    false => match rw.fill_buf().await {
+                        Ok(rx_data) if rx_data.len() == 0 => return Err(RunError::Eof),
+                        Ok(rx_data) => rx_data,
+                        Err(e) => return Err(RunError::Read(e)),
+                    },
+                };
+                Ok((buf, rx_data))
+            };
+            let tx_fut = tx_chan.tx_buf();
+            match select(rx_fut, tx_fut).await {
+                Either::First(r) => {
+                    needs_poll = false;
+
+                    let (buf, rx_data) = r?;
+                    let n = ppp.consume(rx_data, &mut rx_buf);
+                    rw.consume(n);
+
+                    match ppp.poll(&mut tx_buf, &mut rx_buf) {
+                        PPPoSAction::None => {}
+                        PPPoSAction::Received(rg) => {
+                            let pkt = &rx_buf[rg];
+                            buf[..pkt.len()].copy_from_slice(pkt);
+                            rx_chan.rx_done(pkt.len());
+                        }
+                        PPPoSAction::Transmit(n) => rw.write_all(&tx_buf[..n]).await?,
+                    }
+
+                    let status = ppp.status();
+                    match status.phase {
+                        ppproto::Phase::Open => {
+                            if !was_up {
+                                on_ipv4_up(status.ipv4.unwrap());
+                            }
+                            was_up = true;
+                            state_chan.set_link_state(LinkState::Up);
+                        }
+                        _ => {
+                            was_up = false;
+                            state_chan.set_link_state(LinkState::Down);
+                        }
+                    }
+                }
+                Either::Second(pkt) => {
+                    match ppp.send(pkt, &mut tx_buf) {
+                        Ok(n) => rw.write_all(&tx_buf[..n]).await?,
+                        Err(BufferFullError) => unreachable!(),
+                    }
+                    tx_chan.tx_done();
+                }
+            }
+        }
+    }
+}
+
+/// Create a PPP embassy-net driver instance.
+///
+/// This returns two structs:
+/// - a `Device` that you must pass to the `embassy-net` stack.
+/// - a `Runner`. You must call `.run()` on it in a background task.
+pub fn new<'a, const N_RX: usize, const N_TX: usize>(state: &'a mut State<N_RX, N_TX>) -> (Device<'a>, Runner<'a>) {
+    let (runner, device) = ch::new(&mut state.ch_state, ch::driver::HardwareAddress::Ip);
+    (device, Runner { ch: runner })
+}
+
+struct OnDrop<F: FnOnce()> {
+    f: MaybeUninit<F>,
+}
+
+impl<F: FnOnce()> OnDrop<F> {
+    fn new(f: F) -> Self {
+        Self { f: MaybeUninit::new(f) }
+    }
+}
+
+impl<F: FnOnce()> Drop for OnDrop<F> {
+    fn drop(&mut self) {
+        unsafe { self.f.as_ptr().read()() }
+    }
+}

embassy-net-w5500/README.md

@@ -1,7 +0,0 @@
-# WIZnet W5500 `embassy-net` integration
-
-[`embassy-net`](https://crates.io/crates/embassy-net) integration for the WIZnet W5500 SPI ethernet chip, operating in MACRAW mode.
-
-Supports any SPI driver implementing [`embedded-hal-async`](https://crates.io/crates/embedded-hal-async)
-
-See [`examples`](https://github.com/kalkyl/embassy-net-w5500/tree/main/examples) directory for usage examples with the rp2040 [`WIZnet W5500-EVB-Pico`](https://www.wiznet.io/product-item/w5500-evb-pico/) module.

embassy-net-w5500/src/device.rs

@@ -1,131 +0,0 @@
-use embedded_hal_async::spi::SpiDevice;
-
-use crate::socket;
-use crate::spi::SpiInterface;
-
-pub const MODE: u16 = 0x00;
-pub const MAC: u16 = 0x09;
-pub const SOCKET_INTR: u16 = 0x18;
-pub const PHY_CFG: u16 = 0x2E;
-
-#[repr(u8)]
-pub enum RegisterBlock {
-    Common = 0x00,
-    Socket0 = 0x01,
-    TxBuf = 0x02,
-    RxBuf = 0x03,
-}
-
-/// W5500 in MACRAW mode
-#[derive(Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct W5500<SPI> {
-    bus: SpiInterface<SPI>,
-}
-
-impl<SPI: SpiDevice> W5500<SPI> {
-    /// Create and initialize the W5500 driver
-    pub async fn new(spi: SPI, mac_addr: [u8; 6]) -> Result<W5500<SPI>, SPI::Error> {
-        let mut bus = SpiInterface(spi);
-        // Reset device
-        bus.write_frame(RegisterBlock::Common, MODE, &[0x80]).await?;
-
-        // Enable interrupt pin
-        bus.write_frame(RegisterBlock::Common, SOCKET_INTR, &[0x01]).await?;
-        // Enable receive interrupt
-        bus.write_frame(
-            RegisterBlock::Socket0,
-            socket::SOCKET_INTR_MASK,
-            &[socket::Interrupt::Receive as u8],
-        )
-        .await?;
-
-        // Set MAC address
-        bus.write_frame(RegisterBlock::Common, MAC, &mac_addr).await?;
-
-        // Set the raw socket RX/TX buffer sizes to  16KB
-        bus.write_frame(RegisterBlock::Socket0, socket::TXBUF_SIZE, &[16])
-            .await?;
-        bus.write_frame(RegisterBlock::Socket0, socket::RXBUF_SIZE, &[16])
-            .await?;
-
-        // MACRAW mode with MAC filtering.
-        let mode: u8 = (1 << 2) | (1 << 7);
-        bus.write_frame(RegisterBlock::Socket0, socket::MODE, &[mode]).await?;
-        socket::command(&mut bus, socket::Command::Open).await?;
-
-        Ok(Self { bus })
-    }
-
-    /// Read bytes from the RX buffer. Returns the number of bytes read.
-    async fn read_bytes(&mut self, buffer: &mut [u8], offset: u16) -> Result<usize, SPI::Error> {
-        let rx_size = socket::get_rx_size(&mut self.bus).await? as usize;
-
-        let read_buffer = if rx_size > buffer.len() + offset as usize {
-            buffer
-        } else {
-            &mut buffer[..rx_size - offset as usize]
-        };
-
-        let read_ptr = socket::get_rx_read_ptr(&mut self.bus).await?.wrapping_add(offset);
-        self.bus.read_frame(RegisterBlock::RxBuf, read_ptr, read_buffer).await?;
-        socket::set_rx_read_ptr(&mut self.bus, read_ptr.wrapping_add(read_buffer.len() as u16)).await?;
-
-        Ok(read_buffer.len())
-    }
-
-    /// Read an ethernet frame from the device. Returns the number of bytes read.
-    pub async fn read_frame(&mut self, frame: &mut [u8]) -> Result<usize, SPI::Error> {
-        let rx_size = socket::get_rx_size(&mut self.bus).await? as usize;
-        if rx_size == 0 {
-            return Ok(0);
-        }
-
-        socket::reset_interrupt(&mut self.bus, socket::Interrupt::Receive).await?;
-
-        // First two bytes gives the size of the received ethernet frame
-        let expected_frame_size: usize = {
-            let mut frame_bytes = [0u8; 2];
-            assert!(self.read_bytes(&mut frame_bytes[..], 0).await? == 2);
-            u16::from_be_bytes(frame_bytes) as usize - 2
-        };
-
-        // Read the ethernet frame
-        let read_buffer = if frame.len() > expected_frame_size {
-            &mut frame[..expected_frame_size]
-        } else {
-            frame
-        };
-
-        let recvd_frame_size = self.read_bytes(read_buffer, 2).await?;
-
-        // Register RX as completed
-        socket::command(&mut self.bus, socket::Command::Receive).await?;
-
-        // If the whole frame wasn't read, drop it
-        if recvd_frame_size < expected_frame_size {
-            Ok(0)
-        } else {
-            Ok(recvd_frame_size)
-        }
-    }
-
-    /// Write an ethernet frame to the device. Returns number of bytes written
-    pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
-        while socket::get_tx_free_size(&mut self.bus).await? < frame.len() as u16 {}
-        let write_ptr = socket::get_tx_write_ptr(&mut self.bus).await?;
-        self.bus.write_frame(RegisterBlock::TxBuf, write_ptr, frame).await?;
-        socket::set_tx_write_ptr(&mut self.bus, write_ptr.wrapping_add(frame.len() as u16)).await?;
-        socket::command(&mut self.bus, socket::Command::Send).await?;
-        Ok(frame.len())
-    }
-
-    pub async fn is_link_up(&mut self) -> bool {
-        let mut link = [0];
-        self.bus
-            .read_frame(RegisterBlock::Common, PHY_CFG, &mut link)
-            .await
-            .ok();
-        link[0] & 1 == 1
-    }
-}

embassy-net-w5500/src/socket.rs

@@ -1,80 +0,0 @@
-use embedded_hal_async::spi::SpiDevice;
-
-use crate::device::RegisterBlock;
-use crate::spi::SpiInterface;
-
-pub const MODE: u16 = 0x00;
-pub const COMMAND: u16 = 0x01;
-pub const RXBUF_SIZE: u16 = 0x1E;
-pub const TXBUF_SIZE: u16 = 0x1F;
-pub const TX_FREE_SIZE: u16 = 0x20;
-pub const TX_DATA_WRITE_PTR: u16 = 0x24;
-pub const RECVD_SIZE: u16 = 0x26;
-pub const RX_DATA_READ_PTR: u16 = 0x28;
-pub const SOCKET_INTR_MASK: u16 = 0x2C;
-
-#[repr(u8)]
-pub enum Command {
-    Open = 0x01,
-    Send = 0x20,
-    Receive = 0x40,
-}
-
-pub const INTR: u16 = 0x02;
-#[repr(u8)]
-pub enum Interrupt {
-    Receive = 0b00100_u8,
-}
-
-pub async fn reset_interrupt<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, code: Interrupt) -> Result<(), SPI::Error> {
-    let data = [code as u8];
-    bus.write_frame(RegisterBlock::Socket0, INTR, &data).await
-}
-
-pub async fn get_tx_write_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
-    let mut data = [0u8; 2];
-    bus.read_frame(RegisterBlock::Socket0, TX_DATA_WRITE_PTR, &mut data)
-        .await?;
-    Ok(u16::from_be_bytes(data))
-}
-
-pub async fn set_tx_write_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, ptr: u16) -> Result<(), SPI::Error> {
-    let data = ptr.to_be_bytes();
-    bus.write_frame(RegisterBlock::Socket0, TX_DATA_WRITE_PTR, &data).await
-}
-
-pub async fn get_rx_read_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
-    let mut data = [0u8; 2];
-    bus.read_frame(RegisterBlock::Socket0, RX_DATA_READ_PTR, &mut data)
-        .await?;
-    Ok(u16::from_be_bytes(data))
-}
-
-pub async fn set_rx_read_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, ptr: u16) -> Result<(), SPI::Error> {
-    let data = ptr.to_be_bytes();
-    bus.write_frame(RegisterBlock::Socket0, RX_DATA_READ_PTR, &data).await
-}
-
-pub async fn command<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, command: Command) -> Result<(), SPI::Error> {
-    let data = [command as u8];
-    bus.write_frame(RegisterBlock::Socket0, COMMAND, &data).await
-}
-
-pub async fn get_rx_size<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
-    loop {
-        // Wait until two sequential reads are equal
-        let mut res0 = [0u8; 2];
-        bus.read_frame(RegisterBlock::Socket0, RECVD_SIZE, &mut res0).await?;
-        let mut res1 = [0u8; 2];
-        bus.read_frame(RegisterBlock::Socket0, RECVD_SIZE, &mut res1).await?;
-        if res0 == res1 {
-            break Ok(u16::from_be_bytes(res0));
-        }
-    }
-}
-
-pub async fn get_tx_free_size<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
-    let mut data = [0; 2];
-    bus.read_frame(RegisterBlock::Socket0, TX_FREE_SIZE, &mut data).await?;
-    Ok(u16::from_be_bytes(data))
-}

embassy-net-w5500/src/spi.rs

@@ -1,32 +0,0 @@
-use embedded_hal_async::spi::{Operation, SpiDevice};
-
-use crate::device::RegisterBlock;
-
-#[derive(Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct SpiInterface<SPI>(pub SPI);
-
-impl<SPI: SpiDevice> SpiInterface<SPI> {
-    pub async fn read_frame(&mut self, block: RegisterBlock, address: u16, data: &mut [u8]) -> Result<(), SPI::Error> {
-        let address_phase = address.to_be_bytes();
-        let control_phase = [(block as u8) << 3];
-        let operations = &mut [
-            Operation::Write(&address_phase),
-            Operation::Write(&control_phase),
-            Operation::TransferInPlace(data),
-        ];
-        self.0.transaction(operations).await
-    }
-
-    pub async fn write_frame(&mut self, block: RegisterBlock, address: u16, data: &[u8]) -> Result<(), SPI::Error> {
-        let address_phase = address.to_be_bytes();
-        let control_phase = [(block as u8) << 3 | 0b0000_0100];
-        let data_phase = data;
-        let operations = &mut [
-            Operation::Write(&address_phase[..]),
-            Operation::Write(&control_phase),
-            Operation::Write(&data_phase),
-        ];
-        self.0.transaction(operations).await
-    }
-}

embassy-net-wiznet/Cargo.toml

@@ -1,21 +1,22 @@
 [package]
-name = "embassy-net-w5500"
+name = "embassy-net-wiznet"
 version = "0.1.0"
-description = "embassy-net driver for the W5500 ethernet chip"
+description = "embassy-net driver for WIZnet SPI Ethernet chips"
-keywords = ["embedded", "w5500", "embassy-net", "embedded-hal-async", "ethernet", "async"]
+keywords = ["embedded", "wiznet", "embassy-net", "embedded-hal-async", "ethernet", "async"]
 categories = ["embedded", "hardware-support", "no-std", "network-programming", "async"]
 license = "MIT OR Apache-2.0"
 edition = "2021"
 
 [dependencies]
-embedded-hal = { version = "1.0.0-alpha.11" }
+embedded-hal = { version = "1.0.0-rc.1" }
-embedded-hal-async = { version = "=0.2.0-alpha.2" }
+embedded-hal-async = { version = "=1.0.0-rc.1" }
 embassy-net-driver-channel = { version = "0.1.0", path = "../embassy-net-driver-channel" }
 embassy-time = { version = "0.1.2", path = "../embassy-time" }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
 defmt = { version = "0.3", optional = true }
 
 [package.metadata.embassy_docs]
-src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-w5500-v$VERSION/embassy-net-w5500/src/"
+src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-wiznet-v$VERSION/embassy-net-wiznet/src/"
-src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-w5500/src/"
+src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-wiznet/src/"
 target = "thumbv7em-none-eabi"
+features = ["defmt"]

embassy-net-wiznet/README.md

@@ -0,0 +1,27 @@
+# WIZnet `embassy-net` integration
+
+[`embassy-net`](https://crates.io/crates/embassy-net) integration for the WIZnet SPI ethernet chips, operating in MACRAW mode.
+
+See [`examples`](https://github.com/embassy-rs/embassy/tree/main/examples/rp) directory for usage examples with the rp2040 [`WIZnet W5500-EVB-Pico`](https://www.wiznet.io/product-item/w5500-evb-pico/) module.
+
+## Supported chips
+
+- W5500
+- W5100S
+
+## Interoperability
+
+This crate can run on any executor.
+
+It supports any SPI driver implementing [`embedded-hal-async`](https://crates.io/crates/embedded-hal-async).
+
+
+## License
+
+This work is licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.

embassy-net-wiznet/src/chip/mod.rs

@@ -0,0 +1,48 @@
+mod w5500;
+pub use w5500::W5500;
+mod w5100s;
+pub use w5100s::W5100S;
+
+pub(crate) mod sealed {
+    use embedded_hal_async::spi::SpiDevice;
+
+    pub trait Chip {
+        type Address;
+
+        const COMMON_MODE: Self::Address;
+        const COMMON_MAC: Self::Address;
+        const COMMON_SOCKET_INTR: Self::Address;
+        const COMMON_PHY_CFG: Self::Address;
+        const SOCKET_MODE: Self::Address;
+        const SOCKET_COMMAND: Self::Address;
+        const SOCKET_RXBUF_SIZE: Self::Address;
+        const SOCKET_TXBUF_SIZE: Self::Address;
+        const SOCKET_TX_FREE_SIZE: Self::Address;
+        const SOCKET_TX_DATA_WRITE_PTR: Self::Address;
+        const SOCKET_RECVD_SIZE: Self::Address;
+        const SOCKET_RX_DATA_READ_PTR: Self::Address;
+        const SOCKET_INTR_MASK: Self::Address;
+        const SOCKET_INTR: Self::Address;
+
+        const SOCKET_MODE_VALUE: u8;
+
+        const BUF_SIZE: u16;
+        const AUTO_WRAP: bool;
+
+        fn rx_addr(addr: u16) -> Self::Address;
+        fn tx_addr(addr: u16) -> Self::Address;
+
+        async fn bus_read<SPI: SpiDevice>(
+            spi: &mut SPI,
+            address: Self::Address,
+            data: &mut [u8],
+        ) -> Result<(), SPI::Error>;
+        async fn bus_write<SPI: SpiDevice>(
+            spi: &mut SPI,
+            address: Self::Address,
+            data: &[u8],
+        ) -> Result<(), SPI::Error>;
+    }
+}
+
+pub trait Chip: sealed::Chip {}

embassy-net-wiznet/src/chip/w5100s.rs

@@ -0,0 +1,61 @@
+use embedded_hal_async::spi::{Operation, SpiDevice};
+
+const SOCKET_BASE: u16 = 0x400;
+const TX_BASE: u16 = 0x4000;
+const RX_BASE: u16 = 0x6000;
+
+pub enum W5100S {}
+
+impl super::Chip for W5100S {}
+impl super::sealed::Chip for W5100S {
+    type Address = u16;
+
+    const COMMON_MODE: Self::Address = 0x00;
+    const COMMON_MAC: Self::Address = 0x09;
+    const COMMON_SOCKET_INTR: Self::Address = 0x16;
+    const COMMON_PHY_CFG: Self::Address = 0x3c;
+
+    const SOCKET_MODE: Self::Address = SOCKET_BASE + 0x00;
+    const SOCKET_COMMAND: Self::Address = SOCKET_BASE + 0x01;
+    const SOCKET_RXBUF_SIZE: Self::Address = SOCKET_BASE + 0x1E;
+    const SOCKET_TXBUF_SIZE: Self::Address = SOCKET_BASE + 0x1F;
+    const SOCKET_TX_FREE_SIZE: Self::Address = SOCKET_BASE + 0x20;
+    const SOCKET_TX_DATA_WRITE_PTR: Self::Address = SOCKET_BASE + 0x24;
+    const SOCKET_RECVD_SIZE: Self::Address = SOCKET_BASE + 0x26;
+    const SOCKET_RX_DATA_READ_PTR: Self::Address = SOCKET_BASE + 0x28;
+    const SOCKET_INTR_MASK: Self::Address = SOCKET_BASE + 0x2C;
+    const SOCKET_INTR: Self::Address = SOCKET_BASE + 0x02;
+
+    const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 6);
+
+    const BUF_SIZE: u16 = 0x2000;
+    const AUTO_WRAP: bool = false;
+
+    fn rx_addr(addr: u16) -> Self::Address {
+        RX_BASE + addr
+    }
+
+    fn tx_addr(addr: u16) -> Self::Address {
+        TX_BASE + addr
+    }
+
+    async fn bus_read<SPI: SpiDevice>(
+        spi: &mut SPI,
+        address: Self::Address,
+        data: &mut [u8],
+    ) -> Result<(), SPI::Error> {
+        spi.transaction(&mut [
+            Operation::Write(&[0x0F, (address >> 8) as u8, address as u8]),
+            Operation::Read(data),
+        ])
+        .await
+    }
+
+    async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
+        spi.transaction(&mut [
+            Operation::Write(&[0xF0, (address >> 8) as u8, address as u8]),
+            Operation::Write(data),
+        ])
+        .await
+    }
+}

embassy-net-wiznet/src/chip/w5500.rs

@@ -0,0 +1,72 @@
+use embedded_hal_async::spi::{Operation, SpiDevice};
+
+#[repr(u8)]
+pub enum RegisterBlock {
+    Common = 0x00,
+    Socket0 = 0x01,
+    TxBuf = 0x02,
+    RxBuf = 0x03,
+}
+
+pub enum W5500 {}
+
+impl super::Chip for W5500 {}
+impl super::sealed::Chip for W5500 {
+    type Address = (RegisterBlock, u16);
+
+    const COMMON_MODE: Self::Address = (RegisterBlock::Common, 0x00);
+    const COMMON_MAC: Self::Address = (RegisterBlock::Common, 0x09);
+    const COMMON_SOCKET_INTR: Self::Address = (RegisterBlock::Common, 0x18);
+    const COMMON_PHY_CFG: Self::Address = (RegisterBlock::Common, 0x2E);
+
+    const SOCKET_MODE: Self::Address = (RegisterBlock::Socket0, 0x00);
+    const SOCKET_COMMAND: Self::Address = (RegisterBlock::Socket0, 0x01);
+    const SOCKET_RXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x1E);
+    const SOCKET_TXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x1F);
+    const SOCKET_TX_FREE_SIZE: Self::Address = (RegisterBlock::Socket0, 0x20);
+    const SOCKET_TX_DATA_WRITE_PTR: Self::Address = (RegisterBlock::Socket0, 0x24);
+    const SOCKET_RECVD_SIZE: Self::Address = (RegisterBlock::Socket0, 0x26);
+    const SOCKET_RX_DATA_READ_PTR: Self::Address = (RegisterBlock::Socket0, 0x28);
+    const SOCKET_INTR_MASK: Self::Address = (RegisterBlock::Socket0, 0x2C);
+    const SOCKET_INTR: Self::Address = (RegisterBlock::Socket0, 0x02);
+
+    const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 7);
+
+    const BUF_SIZE: u16 = 0x4000;
+    const AUTO_WRAP: bool = true;
+
+    fn rx_addr(addr: u16) -> Self::Address {
+        (RegisterBlock::RxBuf, addr)
+    }
+
+    fn tx_addr(addr: u16) -> Self::Address {
+        (RegisterBlock::TxBuf, addr)
+    }
+
+    async fn bus_read<SPI: SpiDevice>(
+        spi: &mut SPI,
+        address: Self::Address,
+        data: &mut [u8],
+    ) -> Result<(), SPI::Error> {
+        let address_phase = address.1.to_be_bytes();
+        let control_phase = [(address.0 as u8) << 3];
+        let operations = &mut [
+            Operation::Write(&address_phase),
+            Operation::Write(&control_phase),
+            Operation::TransferInPlace(data),
+        ];
+        spi.transaction(operations).await
+    }
+
+    async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
+        let address_phase = address.1.to_be_bytes();
+        let control_phase = [(address.0 as u8) << 3 | 0b0000_0100];
+        let data_phase = data;
+        let operations = &mut [
+            Operation::Write(&address_phase[..]),
+            Operation::Write(&control_phase),
+            Operation::Write(&data_phase),
+        ];
+        spi.transaction(operations).await
+    }
+}

embassy-net-wiznet/src/device.rs

@@ -0,0 +1,195 @@
+use core::marker::PhantomData;
+
+use embedded_hal_async::spi::SpiDevice;
+
+use crate::chip::Chip;
+
+#[repr(u8)]
+enum Command {
+    Open = 0x01,
+    Send = 0x20,
+    Receive = 0x40,
+}
+
+#[repr(u8)]
+enum Interrupt {
+    Receive = 0b00100_u8,
+}
+
+/// Wiznet chip in MACRAW mode
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub(crate) struct WiznetDevice<C, SPI> {
+    spi: SPI,
+    _phantom: PhantomData<C>,
+}
+
+impl<C: Chip, SPI: SpiDevice> WiznetDevice<C, SPI> {
+    /// Create and initialize the driver
+    pub async fn new(spi: SPI, mac_addr: [u8; 6]) -> Result<Self, SPI::Error> {
+        let mut this = Self {
+            spi,
+            _phantom: PhantomData,
+        };
+
+        // Reset device
+        this.bus_write(C::COMMON_MODE, &[0x80]).await?;
+
+        // Enable interrupt pin
+        this.bus_write(C::COMMON_SOCKET_INTR, &[0x01]).await?;
+        // Enable receive interrupt
+        this.bus_write(C::SOCKET_INTR_MASK, &[Interrupt::Receive as u8]).await?;
+
+        // Set MAC address
+        this.bus_write(C::COMMON_MAC, &mac_addr).await?;
+
+        // Set the raw socket RX/TX buffer sizes.
+        let buf_kbs = (C::BUF_SIZE / 1024) as u8;
+        this.bus_write(C::SOCKET_TXBUF_SIZE, &[buf_kbs]).await?;
+        this.bus_write(C::SOCKET_RXBUF_SIZE, &[buf_kbs]).await?;
+
+        // MACRAW mode with MAC filtering.
+        this.bus_write(C::SOCKET_MODE, &[C::SOCKET_MODE_VALUE]).await?;
+        this.command(Command::Open).await?;
+
+        Ok(this)
+    }
+
+    async fn bus_read(&mut self, address: C::Address, data: &mut [u8]) -> Result<(), SPI::Error> {
+        C::bus_read(&mut self.spi, address, data).await
+    }
+
+    async fn bus_write(&mut self, address: C::Address, data: &[u8]) -> Result<(), SPI::Error> {
+        C::bus_write(&mut self.spi, address, data).await
+    }
+
+    async fn reset_interrupt(&mut self, code: Interrupt) -> Result<(), SPI::Error> {
+        let data = [code as u8];
+        self.bus_write(C::SOCKET_INTR, &data).await
+    }
+
+    async fn get_tx_write_ptr(&mut self) -> Result<u16, SPI::Error> {
+        let mut data = [0u8; 2];
+        self.bus_read(C::SOCKET_TX_DATA_WRITE_PTR, &mut data).await?;
+        Ok(u16::from_be_bytes(data))
+    }
+
+    async fn set_tx_write_ptr(&mut self, ptr: u16) -> Result<(), SPI::Error> {
+        let data = ptr.to_be_bytes();
+        self.bus_write(C::SOCKET_TX_DATA_WRITE_PTR, &data).await
+    }
+
+    async fn get_rx_read_ptr(&mut self) -> Result<u16, SPI::Error> {
+        let mut data = [0u8; 2];
+        self.bus_read(C::SOCKET_RX_DATA_READ_PTR, &mut data).await?;
+        Ok(u16::from_be_bytes(data))
+    }
+
+    async fn set_rx_read_ptr(&mut self, ptr: u16) -> Result<(), SPI::Error> {
+        let data = ptr.to_be_bytes();
+        self.bus_write(C::SOCKET_RX_DATA_READ_PTR, &data).await
+    }
+
+    async fn command(&mut self, command: Command) -> Result<(), SPI::Error> {
+        let data = [command as u8];
+        self.bus_write(C::SOCKET_COMMAND, &data).await
+    }
+
+    async fn get_rx_size(&mut self) -> Result<u16, SPI::Error> {
+        loop {
+            // Wait until two sequential reads are equal
+            let mut res0 = [0u8; 2];
+            self.bus_read(C::SOCKET_RECVD_SIZE, &mut res0).await?;
+            let mut res1 = [0u8; 2];
+            self.bus_read(C::SOCKET_RECVD_SIZE, &mut res1).await?;
+            if res0 == res1 {
+                break Ok(u16::from_be_bytes(res0));
+            }
+        }
+    }
+
+    async fn get_tx_free_size(&mut self) -> Result<u16, SPI::Error> {
+        let mut data = [0; 2];
+        self.bus_read(C::SOCKET_TX_FREE_SIZE, &mut data).await?;
+        Ok(u16::from_be_bytes(data))
+    }
+
+    /// Read bytes from the RX buffer.
+    async fn read_bytes(&mut self, read_ptr: &mut u16, buffer: &mut [u8]) -> Result<(), SPI::Error> {
+        if C::AUTO_WRAP {
+            self.bus_read(C::rx_addr(*read_ptr), buffer).await?;
+        } else {
+            let addr = *read_ptr % C::BUF_SIZE;
+            if addr as usize + buffer.len() <= C::BUF_SIZE as usize {
+                self.bus_read(C::rx_addr(addr), buffer).await?;
+            } else {
+                let n = C::BUF_SIZE - addr;
+                self.bus_read(C::rx_addr(addr), &mut buffer[..n as usize]).await?;
+                self.bus_read(C::rx_addr(0), &mut buffer[n as usize..]).await?;
+            }
+        }
+
+        *read_ptr = (*read_ptr).wrapping_add(buffer.len() as u16);
+
+        Ok(())
+    }
+
+    /// Read an ethernet frame from the device. Returns the number of bytes read.
+    pub async fn read_frame(&mut self, frame: &mut [u8]) -> Result<usize, SPI::Error> {
+        let rx_size = self.get_rx_size().await? as usize;
+        if rx_size == 0 {
+            return Ok(0);
+        }
+
+        self.reset_interrupt(Interrupt::Receive).await?;
+
+        let mut read_ptr = self.get_rx_read_ptr().await?;
+
+        // First two bytes gives the size of the received ethernet frame
+        let expected_frame_size: usize = {
+            let mut frame_bytes = [0u8; 2];
+            self.read_bytes(&mut read_ptr, &mut frame_bytes).await?;
+            u16::from_be_bytes(frame_bytes) as usize - 2
+        };
+
+        // Read the ethernet frame
+        self.read_bytes(&mut read_ptr, &mut frame[..expected_frame_size])
+            .await?;
+
+        // Register RX as completed
+        self.set_rx_read_ptr(read_ptr).await?;
+        self.command(Command::Receive).await?;
+
+        Ok(expected_frame_size)
+    }
+
+    /// Write an ethernet frame to the device. Returns number of bytes written
+    pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
+        while self.get_tx_free_size().await? < frame.len() as u16 {}
+        let write_ptr = self.get_tx_write_ptr().await?;
+
+        if C::AUTO_WRAP {
+            self.bus_write(C::tx_addr(write_ptr), frame).await?;
+        } else {
+            let addr = write_ptr % C::BUF_SIZE;
+            if addr as usize + frame.len() <= C::BUF_SIZE as usize {
+                self.bus_write(C::tx_addr(addr), frame).await?;
+            } else {
+                let n = C::BUF_SIZE - addr;
+                self.bus_write(C::tx_addr(addr), &frame[..n as usize]).await?;
+                self.bus_write(C::tx_addr(0), &frame[n as usize..]).await?;
+            }
+        }
+
+        self.set_tx_write_ptr(write_ptr.wrapping_add(frame.len() as u16))
+            .await?;
+        self.command(Command::Send).await?;
+        Ok(frame.len())
+    }
+
+    pub async fn is_link_up(&mut self) -> bool {
+        let mut link = [0];
+        self.bus_read(C::COMMON_PHY_CFG, &mut link).await.ok();
+        link[0] & 1 == 1
+    }
+}

embassy-net-wiznet/src/lib.rs

@@ -1,9 +1,9 @@
-//! [`embassy-net`](https://crates.io/crates/embassy-net) driver for the WIZnet W5500 ethernet chip.
+//! [`embassy-net`](https://crates.io/crates/embassy-net) driver for WIZnet ethernet chips.
 #![no_std]
+#![feature(async_fn_in_trait)]
 
+pub mod chip;
 mod device;
-mod socket;
-mod spi;
 
 use embassy_futures::select::{select, Either};
 use embassy_net_driver_channel as ch;
@@ -13,10 +13,12 @@ use embedded_hal::digital::OutputPin;
 use embedded_hal_async::digital::Wait;
 use embedded_hal_async::spi::SpiDevice;
 
-use crate::device::W5500;
+use crate::chip::Chip;
+use crate::device::WiznetDevice;
+
 const MTU: usize = 1514;
 
-/// Type alias for the embassy-net driver for W5500
+/// Type alias for the embassy-net driver.
 pub type Device<'d> = embassy_net_driver_channel::Device<'d, MTU>;
 
 /// Internal state for the embassy-net integration.
@@ -33,18 +35,18 @@ impl<const N_RX: usize, const N_TX: usize> State<N_RX, N_TX> {
     }
 }
 
-/// Background runner for the W5500.
+/// Background runner for the driver.
 ///
-/// You must call `.run()` in a background task for the W5500 to operate.
+/// You must call `.run()` in a background task for the driver to operate.
-pub struct Runner<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> {
+pub struct Runner<'d, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin> {
-    mac: W5500<SPI>,
+    mac: WiznetDevice<C, SPI>,
     ch: ch::Runner<'d, MTU>,
     int: INT,
     _reset: RST,
 }
 
-/// You must call this in a background task for the W5500 to operate.
+/// You must call this in a background task for the driver to operate.
-impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
+impl<'d, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, C, SPI, INT, RST> {
     pub async fn run(mut self) -> ! {
         let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split();
         loop {
@@ -78,23 +80,29 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
     }
 }
 
-/// Obtain a driver for using the W5500 with [`embassy-net`](https://crates.io/crates/embassy-net).
+/// Create a Wiznet ethernet chip driver for [`embassy-net`](https://crates.io/crates/embassy-net).
-pub async fn new<'a, const N_RX: usize, const N_TX: usize, SPI: SpiDevice, INT: Wait, RST: OutputPin>(
+///
+/// This returns two structs:
+/// - a `Device` that you must pass to the `embassy-net` stack.
+/// - a `Runner`. You must call `.run()` on it in a background task.
+pub async fn new<'a, const N_RX: usize, const N_TX: usize, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin>(
     mac_addr: [u8; 6],
     state: &'a mut State<N_RX, N_TX>,
     spi_dev: SPI,
     int: INT,
     mut reset: RST,
-) -> (Device<'a>, Runner<'a, SPI, INT, RST>) {
+) -> (Device<'a>, Runner<'a, C, SPI, INT, RST>) {
-    // Reset the W5500.
+    // Reset the chip.
     reset.set_low().ok();
     // Ensure the reset is registered.
     Timer::after(Duration::from_millis(1)).await;
     reset.set_high().ok();
-    // Wait for the W5500 to achieve PLL lock.
-    Timer::after(Duration::from_millis(2)).await;
 
-    let mac = W5500::new(spi_dev, mac_addr).await.unwrap();
+    // Wait for PLL lock. Some chips are slower than others.
+    // Slowest is w5100s which is 100ms, so let's just wait that.
+    Timer::after(Duration::from_millis(100)).await;
+
+    let mac = WiznetDevice::new(spi_dev, mac_addr).await.unwrap();
 
     let (runner, device) = ch::new(&mut state.ch_state, ch::driver::HardwareAddress::Ethernet(mac_addr));
     (

embassy-net/Cargo.toml

@@ -9,6 +9,7 @@ categories = [
     "embedded",
     "no-std",
     "asynchronous",
+    "network-programming",
 ]
 
 [package.metadata.embassy_docs]

embassy-net/README.md

@@ -22,7 +22,7 @@ unimplemented features of the network protocols.
 - [`cyw43`](https://github.com/embassy-rs/embassy/tree/main/cyw43) for WiFi on CYW43xx chips, used in the Raspberry Pi Pico W
 - [`embassy-usb`](https://github.com/embassy-rs/embassy/tree/main/embassy-usb) for Ethernet-over-USB (CDC NCM) support.
 - [`embassy-stm32`](https://github.com/embassy-rs/embassy/tree/main/embassy-stm32) for the builtin Ethernet MAC in all STM32 chips (STM32F1, STM32F2, STM32F4, STM32F7, STM32H7, STM32H5).
-- [`embassy-net-w5500`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-w5500) for Wiznet W5500 SPI Ethernet MAC+PHY chip.
+- [`embassy-net-wiznet`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-wiznet) for Wiznet SPI Ethernet MAC+PHY chips (W5100S, W5500)
 - [`embassy-net-esp-hosted`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-esp-hosted) for using ESP32 chips with the [`esp-hosted`](https://github.com/espressif/esp-hosted) firmware as WiFi adapters for another non-ESP32 MCU.
 
 ## Examples

embassy-net/src/lib.rs

@@ -3,6 +3,9 @@
 #![warn(missing_docs)]
 #![doc = include_str!("../README.md")]
 
+#[cfg(not(any(feature = "proto-ipv4", feature = "proto-ipv6")))]
+compile_error!("You must enable at least one of the following features: proto-ipv4, proto-ipv6");
+
 // This mod MUST go first, so that the others see its macros.
 pub(crate) mod fmt;
 
@@ -20,7 +23,7 @@ use core::future::{poll_fn, Future};
 use core::task::{Context, Poll};
 
 pub use embassy_net_driver as driver;
-use embassy_net_driver::{Driver, LinkState, Medium};
+use embassy_net_driver::{Driver, LinkState};
 use embassy_sync::waitqueue::WakerRegistration;
 use embassy_time::{Instant, Timer};
 use futures::pin_mut;
@@ -133,6 +136,8 @@ impl Default for DhcpConfig {
 }
 
 /// Network stack configuration.
+#[derive(Debug, Clone, Default)]
+#[non_exhaustive]
 pub struct Config {
     /// IPv4 configuration
     #[cfg(feature = "proto-ipv4")]
@@ -181,23 +186,27 @@ impl Config {
 
 /// Network stack IPv4 configuration.
 #[cfg(feature = "proto-ipv4")]
+#[derive(Debug, Clone, Default)]
 pub enum ConfigV4 {
+    /// Do not configure IPv4.
+    #[default]
+    None,
     /// Use a static IPv4 address configuration.
     Static(StaticConfigV4),
     /// Use DHCP to obtain an IP address configuration.
     #[cfg(feature = "dhcpv4")]
     Dhcp(DhcpConfig),
-    /// Do not configure IPv6.
-    None,
 }
 
 /// Network stack IPv6 configuration.
 #[cfg(feature = "proto-ipv6")]
+#[derive(Debug, Clone, Default)]
 pub enum ConfigV6 {
+    /// Do not configure IPv6.
+    #[default]
+    None,
     /// Use a static IPv6 address configuration.
     Static(StaticConfigV6),
-    /// Do not configure IPv6.
-    None,
 }
 
 /// A network stack.
@@ -240,7 +249,10 @@ fn to_smoltcp_hardware_address(addr: driver::HardwareAddress) -> HardwareAddress
         driver::HardwareAddress::Ip => HardwareAddress::Ip,
 
         #[allow(unreachable_patterns)]
-        _ => panic!("Unsupported address {:?}. Make sure to enable medium-ethernet or medium-ieee802154 in embassy-net's Cargo features.", addr),
+        _ => panic!(
+            "Unsupported medium {:?}. Make sure to enable the right medium feature in embassy-net's Cargo features.",
+            addr
+        ),
     }
 }
 
@@ -276,7 +288,6 @@ impl<D: Driver + 'static> Stack<D> {
             next_local_port,
         };
 
-        #[cfg_attr(feature = "medium-ieee802154", allow(unused_mut))]
         let mut inner = Inner {
             device,
             link_up: false,
@@ -295,30 +306,11 @@ impl<D: Driver + 'static> Stack<D> {
             dns_waker: WakerRegistration::new(),
         };
 
-        #[cfg(feature = "medium-ieee802154")]
-        let _ = config;
-
         #[cfg(feature = "proto-ipv4")]
-        match config.ipv4 {
+        inner.set_config_v4(&mut socket, config.ipv4);
-            ConfigV4::Static(config) => {
-                inner.apply_config_v4(&mut socket, config);
-            }
-            #[cfg(feature = "dhcpv4")]
-            ConfigV4::Dhcp(config) => {
-                let mut dhcp_socket = smoltcp::socket::dhcpv4::Socket::new();
-                inner.apply_dhcp_config(&mut dhcp_socket, config);
-                let handle = socket.sockets.add(dhcp_socket);
-                inner.dhcp_socket = Some(handle);
-            }
-            ConfigV4::None => {}
-        }
         #[cfg(feature = "proto-ipv6")]
-        match config.ipv6 {
+        inner.set_config_v6(&mut socket, config.ipv6);
-            ConfigV6::Static(config) => {
+        inner.apply_static_config(&mut socket);
-                inner.apply_config_v6(&mut socket, config);
-            }
-            ConfigV6::None => {}
-        }
 
         Self {
             socket: RefCell::new(socket),
@@ -372,15 +364,36 @@ impl<D: Driver + 'static> Stack<D> {
     }
 
     /// Get the current IPv4 configuration.
+    ///
+    /// If using DHCP, this will be None if DHCP hasn't been able to
+    /// acquire an IP address, or Some if it has.
     #[cfg(feature = "proto-ipv4")]
     pub fn config_v4(&self) -> Option<StaticConfigV4> {
-        self.with(|_s, i| i.static_v4.clone())
+        self.with(|_, i| i.static_v4.clone())
     }
 
     /// Get the current IPv6 configuration.
     #[cfg(feature = "proto-ipv6")]
     pub fn config_v6(&self) -> Option<StaticConfigV6> {
-        self.with(|_s, i| i.static_v6.clone())
+        self.with(|_, i| i.static_v6.clone())
+    }
+
+    /// Set the IPv4 configuration.
+    #[cfg(feature = "proto-ipv4")]
+    pub fn set_config_v4(&self, config: ConfigV4) {
+        self.with_mut(|s, i| {
+            i.set_config_v4(s, config);
+            i.apply_static_config(s);
+        })
+    }
+
+    /// Set the IPv6 configuration.
+    #[cfg(feature = "proto-ipv6")]
+    pub fn set_config_v6(&self, config: ConfigV6) {
+        self.with_mut(|s, i| {
+            i.set_config_v6(s, config);
+            i.apply_static_config(s);
+        })
     }
 
     /// Run the network stack.
@@ -582,166 +595,125 @@ impl SocketStack {
 
 impl<D: Driver + 'static> Inner<D> {
     #[cfg(feature = "proto-ipv4")]
-    fn apply_config_v4(&mut self, s: &mut SocketStack, config: StaticConfigV4) {
+    pub fn set_config_v4(&mut self, _s: &mut SocketStack, config: ConfigV4) {
-        debug!("Acquired IP configuration:");
+        // Handle static config.
+        self.static_v4 = match config.clone() {
+            ConfigV4::None => None,
+            #[cfg(feature = "dhcpv4")]
+            ConfigV4::Dhcp(_) => None,
+            ConfigV4::Static(c) => Some(c),
+        };
 
-        debug!("   IP address:      {}", config.address);
+        // Handle DHCP config.
-        s.iface.update_ip_addrs(|addrs| {
+        #[cfg(feature = "dhcpv4")]
-            if let Some((index, _)) = addrs
+        match config {
-                .iter()
+            ConfigV4::Dhcp(c) => {
-                .enumerate()
+                // Create the socket if it doesn't exist.
-                .find(|(_, &addr)| matches!(addr, IpCidr::Ipv4(_)))
+                if self.dhcp_socket.is_none() {
-            {
+                    let socket = smoltcp::socket::dhcpv4::Socket::new();
-                addrs.remove(index);
+                    let handle = _s.sockets.add(socket);
+                    self.dhcp_socket = Some(handle);
                 }
+
+                // Configure it
+                let socket = _s.sockets.get_mut::<dhcpv4::Socket>(self.dhcp_socket.unwrap());
+                socket.set_ignore_naks(c.ignore_naks);
+                socket.set_max_lease_duration(c.max_lease_duration.map(crate::time::duration_to_smoltcp));
+                socket.set_ports(c.server_port, c.client_port);
+                socket.set_retry_config(c.retry_config);
+                socket.reset();
+            }
+            _ => {
+                // Remove DHCP socket if any.
+                if let Some(socket) = self.dhcp_socket {
+                    _s.sockets.remove(socket);
+                    self.dhcp_socket = None;
+                }
+            }
+        }
+    }
+
+    #[cfg(feature = "proto-ipv6")]
+    pub fn set_config_v6(&mut self, _s: &mut SocketStack, config: ConfigV6) {
+        self.static_v6 = match config {
+            ConfigV6::None => None,
+            ConfigV6::Static(c) => Some(c),
+        };
+    }
+
+    fn apply_static_config(&mut self, s: &mut SocketStack) {
+        let mut addrs = Vec::new();
+        #[cfg(feature = "dns")]
+        let mut dns_servers: Vec<_, 6> = Vec::new();
+        #[cfg(feature = "proto-ipv4")]
+        let mut gateway_v4 = None;
+        #[cfg(feature = "proto-ipv6")]
+        let mut gateway_v6 = None;
+
+        #[cfg(feature = "proto-ipv4")]
+        if let Some(config) = &self.static_v4 {
+            debug!("IPv4: UP");
+            debug!("   IP address:      {:?}", config.address);
+            debug!("   Default gateway: {:?}", config.gateway);
+
             addrs.push(IpCidr::Ipv4(config.address)).unwrap();
-        });
+            gateway_v4 = config.gateway.into();
+            #[cfg(feature = "dns")]
+            for s in &config.dns_servers {
+                debug!("   DNS server:      {:?}", s);
+                dns_servers.push(s.clone().into()).unwrap();
+            }
+        } else {
+            info!("IPv4: DOWN");
+        }
 
-        #[cfg(feature = "medium-ip")]
+        #[cfg(feature = "proto-ipv6")]
-        let skip_gateway = self.device.capabilities().medium != Medium::Ip;
+        if let Some(config) = &self.static_v6 {
-        #[cfg(not(feature = "medium-ip"))]
+            debug!("IPv6: UP");
-        let skip_gateway = false;
+            debug!("   IP address:      {:?}", config.address);
+            debug!("   Default gateway: {:?}", config.gateway);
 
-        if !skip_gateway {
+            addrs.push(IpCidr::Ipv6(config.address)).unwrap();
-            if let Some(gateway) = config.gateway {
+            gateway_v6 = config.gateway.into();
-                debug!("   Default gateway: {}", gateway);
+            #[cfg(feature = "dns")]
+            for s in &config.dns_servers {
+                debug!("   DNS server:      {:?}", s);
+                dns_servers.push(s.clone().into()).unwrap();
+            }
+        } else {
+            info!("IPv6: DOWN");
+        }
+
+        // Apply addresses
+        s.iface.update_ip_addrs(|a| *a = addrs);
+
+        // Apply gateways
+        #[cfg(feature = "proto-ipv4")]
+        if let Some(gateway) = gateway_v4 {
             s.iface.routes_mut().add_default_ipv4_route(gateway).unwrap();
         } else {
-                debug!("   Default gateway: None");
             s.iface.routes_mut().remove_default_ipv4_route();
         }
-        }
-        for (i, s) in config.dns_servers.iter().enumerate() {
-            debug!("   DNS server {}:    {}", i, s);
-        }
-
-        self.static_v4 = Some(config);
-
-        #[cfg(feature = "dns")]
-        {
-            self.update_dns_servers(s)
-        }
-    }
-
-    /// Replaces the current IPv6 static configuration with a newly supplied config.
         #[cfg(feature = "proto-ipv6")]
-    fn apply_config_v6(&mut self, s: &mut SocketStack, config: StaticConfigV6) {
+        if let Some(gateway) = gateway_v6 {
-        #[cfg(feature = "medium-ethernet")]
-        let medium = self.device.capabilities().medium;
-
-        debug!("Acquired IPv6 configuration:");
-
-        debug!("   IP address:      {}", config.address);
-        s.iface.update_ip_addrs(|addrs| {
-            if let Some((index, _)) = addrs
-                .iter()
-                .enumerate()
-                .find(|(_, &addr)| matches!(addr, IpCidr::Ipv6(_)))
-            {
-                addrs.remove(index);
-            }
-            addrs.push(IpCidr::Ipv6(config.address)).unwrap();
-        });
-
-        #[cfg(feature = "medium-ethernet")]
-        if Medium::Ethernet == medium {
-            if let Some(gateway) = config.gateway {
-                debug!("   Default gateway: {}", gateway);
             s.iface.routes_mut().add_default_ipv6_route(gateway).unwrap();
         } else {
-                debug!("   Default gateway: None");
             s.iface.routes_mut().remove_default_ipv6_route();
         }
-        }
-        for (i, s) in config.dns_servers.iter().enumerate() {
-            debug!("   DNS server {}:    {}", i, s);
-        }
-
-        self.static_v6 = Some(config);
 
+        // Apply DNS servers
         #[cfg(feature = "dns")]
-        {
+        s.sockets
-            self.update_dns_servers(s)
+            .get_mut::<smoltcp::socket::dns::Socket>(self.dns_socket)
-        }
+            .update_servers(&dns_servers[..]);
-    }
-
-    #[cfg(feature = "dns")]
-    fn update_dns_servers(&mut self, s: &mut SocketStack) {
-        let socket = s.sockets.get_mut::<smoltcp::socket::dns::Socket>(self.dns_socket);
-
-        let servers_v4;
-        #[cfg(feature = "proto-ipv4")]
-        {
-            servers_v4 = self
-                .static_v4
-                .iter()
-                .flat_map(|cfg| cfg.dns_servers.iter().map(|c| IpAddress::Ipv4(*c)));
-        };
-        #[cfg(not(feature = "proto-ipv4"))]
-        {
-            servers_v4 = core::iter::empty();
-        }
-
-        let servers_v6;
-        #[cfg(feature = "proto-ipv6")]
-        {
-            servers_v6 = self
-                .static_v6
-                .iter()
-                .flat_map(|cfg| cfg.dns_servers.iter().map(|c| IpAddress::Ipv6(*c)));
-        }
-        #[cfg(not(feature = "proto-ipv6"))]
-        {
-            servers_v6 = core::iter::empty();
-        }
-
-        // Prefer the v6 DNS servers over the v4 servers
-        let servers: Vec<IpAddress, 6> = servers_v6.chain(servers_v4).collect();
-        socket.update_servers(&servers[..]);
-    }
-
-    #[cfg(feature = "dhcpv4")]
-    fn apply_dhcp_config(&self, socket: &mut smoltcp::socket::dhcpv4::Socket, config: DhcpConfig) {
-        socket.set_ignore_naks(config.ignore_naks);
-        socket.set_max_lease_duration(config.max_lease_duration.map(crate::time::duration_to_smoltcp));
-        socket.set_ports(config.server_port, config.client_port);
-        socket.set_retry_config(config.retry_config);
-    }
-
-    #[cfg(feature = "dhcpv4")]
-    fn unapply_config_v4(&mut self, s: &mut SocketStack) {
-        #[cfg(feature = "medium-ethernet")]
-        let medium = self.device.capabilities().medium;
-        debug!("Lost IP configuration");
-        s.iface.update_ip_addrs(|ip_addrs| {
-            #[cfg(feature = "proto-ipv4")]
-            if let Some((index, _)) = ip_addrs
-                .iter()
-                .enumerate()
-                .find(|(_, &addr)| matches!(addr, IpCidr::Ipv4(_)))
-            {
-                ip_addrs.remove(index);
-            }
-        });
-        #[cfg(feature = "medium-ethernet")]
-        if medium == Medium::Ethernet {
-            #[cfg(feature = "proto-ipv4")]
-            {
-                s.iface.routes_mut().remove_default_ipv4_route();
-            }
-        }
-        #[cfg(feature = "proto-ipv4")]
-        {
-            self.static_v4 = None
-        }
     }
 
     fn poll(&mut self, cx: &mut Context<'_>, s: &mut SocketStack) {
         s.waker.register(cx.waker());
 
         #[cfg(any(feature = "medium-ethernet", feature = "medium-ieee802154"))]
-        if self.device.capabilities().medium == Medium::Ethernet
+        if self.device.capabilities().medium == embassy_net_driver::Medium::Ethernet
-            || self.device.capabilities().medium == Medium::Ieee802154
+            || self.device.capabilities().medium == embassy_net_driver::Medium::Ieee802154
         {
             s.iface
                 .set_hardware_addr(to_smoltcp_hardware_address(self.device.hardware_address()));
@@ -763,6 +735,9 @@ impl<D: Driver + 'static> Inner<D> {
             info!("link_up = {:?}", self.link_up);
         }
 
+        #[allow(unused_mut)]
+        let mut apply_config = false;
+
         #[cfg(feature = "dhcpv4")]
         if let Some(dhcp_handle) = self.dhcp_socket {
             let socket = s.sockets.get_mut::<dhcpv4::Socket>(dhcp_handle);
@@ -770,25 +745,29 @@ impl<D: Driver + 'static> Inner<D> {
             if self.link_up {
                 match socket.poll() {
                     None => {}
-                    Some(dhcpv4::Event::Deconfigured) => self.unapply_config_v4(s),
+                    Some(dhcpv4::Event::Deconfigured) => {
+                        self.static_v4 = None;
+                        apply_config = true;
+                    }
                     Some(dhcpv4::Event::Configured(config)) => {
-                        let config = StaticConfigV4 {
+                        self.static_v4 = Some(StaticConfigV4 {
                             address: config.address,
                             gateway: config.router,
                             dns_servers: config.dns_servers,
-                        };
+                        });
-                        self.apply_config_v4(s, config)
+                        apply_config = true;
                     }
                 }
             } else if old_link_up {
                 socket.reset();
-                self.unapply_config_v4(s);
+                self.static_v4 = None;
+                apply_config = true;
             }
         }
-        //if old_link_up || self.link_up {
+
-        //    self.poll_configurator(timestamp)
+        if apply_config {
-        //}
+            self.apply_static_config(s);
-        //
+        }
 
         if let Some(poll_at) = s.iface.poll_at(timestamp, &mut s.sockets) {
             let t = Timer::at(instant_from_smoltcp(poll_at));

embassy-net/src/tcp.rs

@@ -82,6 +82,22 @@ impl<'a> TcpReader<'a> {
     pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
         self.io.read(buf).await
     }
+
+    /// Call `f` with the largest contiguous slice of octets in the receive buffer,
+    /// and dequeue the amount of elements returned by `f`.
+    ///
+    /// If no data is available, it waits until there is at least one byte available.
+    pub async fn read_with<F, R>(&mut self, f: F) -> Result<R, Error>
+    where
+        F: FnOnce(&mut [u8]) -> (usize, R),
+    {
+        self.io.read_with(f).await
+    }
+
+    /// Return the maximum number of bytes inside the transmit buffer.
+    pub fn recv_capacity(&self) -> usize {
+        self.io.recv_capacity()
+    }
 }
 
 impl<'a> TcpWriter<'a> {
@@ -100,6 +116,22 @@ impl<'a> TcpWriter<'a> {
     pub async fn flush(&mut self) -> Result<(), Error> {
         self.io.flush().await
     }
+
+    /// Call `f` with the largest contiguous slice of octets in the transmit buffer,
+    /// and enqueue the amount of elements returned by `f`.
+    ///
+    /// If the socket is not ready to accept data, it waits until it is.
+    pub async fn write_with<F, R>(&mut self, f: F) -> Result<R, Error>
+    where
+        F: FnOnce(&mut [u8]) -> (usize, R),
+    {
+        self.io.write_with(f).await
+    }
+
+    /// Return the maximum number of bytes inside the transmit buffer.
+    pub fn send_capacity(&self) -> usize {
+        self.io.send_capacity()
+    }
 }
 
 impl<'a> TcpSocket<'a> {
@@ -121,6 +153,38 @@ impl<'a> TcpSocket<'a> {
         }
     }
 
+    /// Return the maximum number of bytes inside the recv buffer.
+    pub fn recv_capacity(&self) -> usize {
+        self.io.recv_capacity()
+    }
+
+    /// Return the maximum number of bytes inside the transmit buffer.
+    pub fn send_capacity(&self) -> usize {
+        self.io.send_capacity()
+    }
+
+    /// Call `f` with the largest contiguous slice of octets in the transmit buffer,
+    /// and enqueue the amount of elements returned by `f`.
+    ///
+    /// If the socket is not ready to accept data, it waits until it is.
+    pub async fn write_with<F, R>(&mut self, f: F) -> Result<R, Error>
+    where
+        F: FnOnce(&mut [u8]) -> (usize, R),
+    {
+        self.io.write_with(f).await
+    }
+
+    /// Call `f` with the largest contiguous slice of octets in the receive buffer,
+    /// and dequeue the amount of elements returned by `f`.
+    ///
+    /// If no data is available, it waits until there is at least one byte available.
+    pub async fn read_with<F, R>(&mut self, f: F) -> Result<R, Error>
+    where
+        F: FnOnce(&mut [u8]) -> (usize, R),
+    {
+        self.io.read_with(f).await
+    }
+
     /// Split the socket into reader and a writer halves.
     pub fn split(&mut self) -> (TcpReader<'_>, TcpWriter<'_>) {
         (TcpReader { io: self.io }, TcpWriter { io: self.io })
@@ -359,6 +423,64 @@ impl<'d> TcpIo<'d> {
         .await
     }
 
+    async fn write_with<F, R>(&mut self, f: F) -> Result<R, Error>
+    where
+        F: FnOnce(&mut [u8]) -> (usize, R),
+    {
+        let mut f = Some(f);
+        poll_fn(move |cx| {
+            self.with_mut(|s, _| {
+                if !s.can_send() {
+                    if s.may_send() {
+                        // socket buffer is full wait until it has atleast one byte free
+                        s.register_send_waker(cx.waker());
+                        Poll::Pending
+                    } else {
+                        // if we can't transmit because the transmit half of the duplex connection is closed then return an error
+                        Poll::Ready(Err(Error::ConnectionReset))
+                    }
+                } else {
+                    Poll::Ready(match s.send(f.take().unwrap()) {
+                        // Connection reset. TODO: this can also be timeouts etc, investigate.
+                        Err(tcp::SendError::InvalidState) => Err(Error::ConnectionReset),
+                        Ok(r) => Ok(r),
+                    })
+                }
+            })
+        })
+        .await
+    }
+
+    async fn read_with<F, R>(&mut self, f: F) -> Result<R, Error>
+    where
+        F: FnOnce(&mut [u8]) -> (usize, R),
+    {
+        let mut f = Some(f);
+        poll_fn(move |cx| {
+            self.with_mut(|s, _| {
+                if !s.can_recv() {
+                    if s.may_recv() {
+                        // socket buffer is empty wait until it has atleast one byte has arrived
+                        s.register_recv_waker(cx.waker());
+                        Poll::Pending
+                    } else {
+                        // if we can't receive because the recieve half of the duplex connection is closed then return an error
+                        Poll::Ready(Err(Error::ConnectionReset))
+                    }
+                } else {
+                    Poll::Ready(match s.recv(f.take().unwrap()) {
+                        // Connection reset. TODO: this can also be timeouts etc, investigate.
+                        Err(tcp::RecvError::Finished) | Err(tcp::RecvError::InvalidState) => {
+                            Err(Error::ConnectionReset)
+                        }
+                        Ok(r) => Ok(r),
+                    })
+                }
+            })
+        })
+        .await
+    }
+
     async fn flush(&mut self) -> Result<(), Error> {
         poll_fn(move |cx| {
             self.with_mut(|s, _| {
@@ -376,6 +498,14 @@ impl<'d> TcpIo<'d> {
         })
         .await
     }
+
+    fn recv_capacity(&self) -> usize {
+        self.with(|s, _| s.recv_capacity())
+    }
+
+    fn send_capacity(&self) -> usize {
+        self.with(|s, _| s.send_capacity())
+    }
 }
 
 #[cfg(feature = "nightly")]
@@ -384,13 +514,20 @@ mod embedded_io_impls {
 
     impl embedded_io_async::Error for ConnectError {
         fn kind(&self) -> embedded_io_async::ErrorKind {
-            embedded_io_async::ErrorKind::Other
+            match self {
+                ConnectError::ConnectionReset => embedded_io_async::ErrorKind::ConnectionReset,
+                ConnectError::TimedOut => embedded_io_async::ErrorKind::TimedOut,
+                ConnectError::NoRoute => embedded_io_async::ErrorKind::NotConnected,
+                ConnectError::InvalidState => embedded_io_async::ErrorKind::Other,
+            }
         }
     }
 
     impl embedded_io_async::Error for Error {
         fn kind(&self) -> embedded_io_async::ErrorKind {
-            embedded_io_async::ErrorKind::Other
+            match self {
+                Error::ConnectionReset => embedded_io_async::ErrorKind::ConnectionReset,
+            }
         }
     }
 

embassy-net/src/udp.rs

@@ -184,6 +184,26 @@ impl<'a> UdpSocket<'a> {
     pub fn may_recv(&self) -> bool {
         self.with(|s, _| s.can_recv())
     }
+
+    /// Return the maximum number packets the socket can receive.
+    pub fn packet_recv_capacity(&self) -> usize {
+        self.with(|s, _| s.packet_recv_capacity())
+    }
+
+    /// Return the maximum number packets the socket can receive.
+    pub fn packet_send_capacity(&self) -> usize {
+        self.with(|s, _| s.packet_send_capacity())
+    }
+
+    /// Return the maximum number of bytes inside the recv buffer.
+    pub fn payload_recv_capacity(&self) -> usize {
+        self.with(|s, _| s.payload_recv_capacity())
+    }
+
+    /// Return the maximum number of bytes inside the transmit buffer.
+    pub fn payload_send_capacity(&self) -> usize {
+        self.with(|s, _| s.payload_send_capacity())
+    }
 }
 
 impl Drop for UdpSocket<'_> {

embassy-nrf/Cargo.toml

@@ -32,7 +32,7 @@ rt = [
 
 time = ["dep:embassy-time"]
 
-defmt = ["dep:defmt", "embassy-sync/defmt", "embassy-usb-driver?/defmt", "embassy-embedded-hal/defmt"]
+defmt = ["dep:defmt", "embassy-hal-internal/defmt", "embassy-sync/defmt", "embassy-usb-driver?/defmt", "embassy-embedded-hal/defmt"]
 
 # Enable nightly-only features
 nightly = ["embedded-hal-1", "embedded-hal-async", "dep:embassy-usb-driver", "embedded-storage-async", "dep:embedded-io-async", "embassy-embedded-hal/nightly"]
@@ -98,8 +98,8 @@ embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" }
 embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optional=true }
 
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
-embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.11", optional = true}
+embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1", optional = true}
-embedded-hal-async = { version = "=0.2.0-alpha.2", optional = true}
+embedded-hal-async = { version = "=1.0.0-rc.1", optional = true}
 embedded-io = { version = "0.5.0" }
 embedded-io-async = { version = "0.5.0", optional = true }
 

embassy-nrf/src/spim.rs

@@ -378,6 +378,9 @@ impl<'d, T: Instance> Drop for Spim<'d, T> {
         gpio::deconfigure_pin(r.psel.miso.read().bits());
         gpio::deconfigure_pin(r.psel.mosi.read().bits());
 
+        // Disable all events interrupts
+        T::Interrupt::disable();
+
         trace!("spim drop: done");
     }
 }

embassy-nrf/src/uarte.rs

@@ -949,51 +949,3 @@ mod eh02 {
         }
     }
 }
-
-#[cfg(feature = "unstable-traits")]
-mod eh1 {
-    use super::*;
-
-    impl embedded_hal_1::serial::Error for Error {
-        fn kind(&self) -> embedded_hal_1::serial::ErrorKind {
-            match *self {
-                Self::BufferTooLong => embedded_hal_1::serial::ErrorKind::Other,
-                Self::BufferNotInRAM => embedded_hal_1::serial::ErrorKind::Other,
-            }
-        }
-    }
-
-    // =====================
-
-    impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for Uarte<'d, T> {
-        type Error = Error;
-    }
-
-    impl<'d, T: Instance> embedded_hal_1::serial::Write for Uarte<'d, T> {
-        fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
-            self.blocking_write(buffer)
-        }
-
-        fn flush(&mut self) -> Result<(), Self::Error> {
-            Ok(())
-        }
-    }
-
-    impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for UarteTx<'d, T> {
-        type Error = Error;
-    }
-
-    impl<'d, T: Instance> embedded_hal_1::serial::Write for UarteTx<'d, T> {
-        fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
-            self.blocking_write(buffer)
-        }
-
-        fn flush(&mut self) -> Result<(), Self::Error> {
-            Ok(())
-        }
-    }
-
-    impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for UarteRx<'d, T> {
-        type Error = Error;
-    }
-}

embassy-rp/Cargo.toml

@@ -85,9 +85,9 @@ fixed = "1.23.1"
 rp-pac = { version = "6" }
 
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
-embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.11", optional = true}
+embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1", optional = true}
-embedded-hal-async = { version = "=0.2.0-alpha.2", optional = true}
+embedded-hal-async = { version = "=1.0.0-rc.1", optional = true}
-embedded-hal-nb = { version = "=1.0.0-alpha.3", optional = true}
+embedded-hal-nb = { version = "=1.0.0-rc.1", optional = true}
 
 paste = "1.0"
 pio-proc = {version= "0.2" }
@@ -95,5 +95,5 @@ pio = {version= "0.2.1" }
 rp2040-boot2 = "0.3"
 
 [dev-dependencies]
-embassy-executor = { version = "0.2.0", path = "../embassy-executor", features = ["nightly", "arch-std", "executor-thread"] }
+embassy-executor = { version = "0.3.0", path = "../embassy-executor", features = ["nightly", "arch-std", "executor-thread"] }
 static_cell = "1.1"

embassy-rp/src/dma.rs

@@ -76,7 +76,8 @@ pub unsafe fn write<'a, C: Channel, W: Word>(
     )
 }
 
-static DUMMY: u32 = 0;
+// static mut so that this is allocated in RAM.
+static mut DUMMY: u32 = 0;
 
 pub unsafe fn write_repeated<'a, C: Channel, W: Word>(
     ch: impl Peripheral<P = C> + 'a,
@@ -86,7 +87,7 @@ pub unsafe fn write_repeated<'a, C: Channel, W: Word>(
 ) -> Transfer<'a, C> {
     copy_inner(
         ch,
-        &DUMMY as *const u32,
+        &mut DUMMY as *const u32,
         to as *mut u32,
         len,
         W::size(),

embassy-rp/src/flash.rs

@@ -102,7 +102,7 @@ pub struct Flash<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> {
 }
 
 impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> Flash<'d, T, M, FLASH_SIZE> {
-    pub fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
+    pub fn blocking_read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
         trace!(
             "Reading from 0x{:x} to 0x{:x}",
             FLASH_BASE as u32 + offset,
@@ -120,7 +120,7 @@ impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> Flash<'d, T, M, FLASH_SI
         FLASH_SIZE
     }
 
-    pub fn erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
+    pub fn blocking_erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
         check_erase(self, from, to)?;
 
         trace!(
@@ -136,7 +136,7 @@ impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> Flash<'d, T, M, FLASH_SI
         Ok(())
     }
 
-    pub fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Error> {
+    pub fn blocking_write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Error> {
         check_write(self, offset, bytes.len())?;
 
         trace!("Writing {:?} bytes to 0x{:x}", bytes.len(), FLASH_BASE as u32 + offset);
@@ -233,13 +233,13 @@ impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> Flash<'d, T, M, FLASH_SI
     }
 
     /// Read SPI flash unique ID
-    pub fn unique_id(&mut self, uid: &mut [u8]) -> Result<(), Error> {
+    pub fn blocking_unique_id(&mut self, uid: &mut [u8]) -> Result<(), Error> {
         unsafe { self.in_ram(|| ram_helpers::flash_unique_id(uid))? };
         Ok(())
     }
 
     /// Read SPI flash JEDEC ID
-    pub fn jedec_id(&mut self) -> Result<u32, Error> {
+    pub fn blocking_jedec_id(&mut self) -> Result<u32, Error> {
         let mut jedec = None;
         unsafe {
             self.in_ram(|| {
@@ -251,7 +251,7 @@ impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> Flash<'d, T, M, FLASH_SI
 }
 
 impl<'d, T: Instance, const FLASH_SIZE: usize> Flash<'d, T, Blocking, FLASH_SIZE> {
-    pub fn new(_flash: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new_blocking(_flash: impl Peripheral<P = T> + 'd) -> Self {
         Self {
             dma: None,
             phantom: PhantomData,
@@ -310,47 +310,8 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> Flash<'d, T, Async, FLASH_SIZE> {
             transfer,
         })
     }
-}
 
-impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> ErrorType for Flash<'d, T, M, FLASH_SIZE> {
+    pub async fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
-    type Error = Error;
-}
-
-impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> ReadNorFlash for Flash<'d, T, M, FLASH_SIZE> {
-    const READ_SIZE: usize = READ_SIZE;
-
-    fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
-        self.read(offset, bytes)
-    }
-
-    fn capacity(&self) -> usize {
-        self.capacity()
-    }
-}
-
-impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> MultiwriteNorFlash for Flash<'d, T, M, FLASH_SIZE> {}
-
-impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> NorFlash for Flash<'d, T, M, FLASH_SIZE> {
-    const WRITE_SIZE: usize = WRITE_SIZE;
-
-    const ERASE_SIZE: usize = ERASE_SIZE;
-
-    fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
-        self.erase(from, to)
-    }
-
-    fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
-        self.write(offset, bytes)
-    }
-}
-
-#[cfg(feature = "nightly")]
-impl<'d, T: Instance, const FLASH_SIZE: usize> embedded_storage_async::nor_flash::ReadNorFlash
-    for Flash<'d, T, Async, FLASH_SIZE>
-{
-    const READ_SIZE: usize = ASYNC_READ_SIZE;
-
-    async fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
         use core::mem::MaybeUninit;
 
         // Checked early to simplify address validity checks
@@ -389,6 +350,49 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> embedded_storage_async::nor_flash
 
         Ok(())
     }
+}
+
+impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> ErrorType for Flash<'d, T, M, FLASH_SIZE> {
+    type Error = Error;
+}
+
+impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> ReadNorFlash for Flash<'d, T, M, FLASH_SIZE> {
+    const READ_SIZE: usize = READ_SIZE;
+
+    fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
+        self.blocking_read(offset, bytes)
+    }
+
+    fn capacity(&self) -> usize {
+        self.capacity()
+    }
+}
+
+impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> MultiwriteNorFlash for Flash<'d, T, M, FLASH_SIZE> {}
+
+impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> NorFlash for Flash<'d, T, M, FLASH_SIZE> {
+    const WRITE_SIZE: usize = WRITE_SIZE;
+
+    const ERASE_SIZE: usize = ERASE_SIZE;
+
+    fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
+        self.blocking_erase(from, to)
+    }
+
+    fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_write(offset, bytes)
+    }
+}
+
+#[cfg(feature = "nightly")]
+impl<'d, T: Instance, const FLASH_SIZE: usize> embedded_storage_async::nor_flash::ReadNorFlash
+    for Flash<'d, T, Async, FLASH_SIZE>
+{
+    const READ_SIZE: usize = ASYNC_READ_SIZE;
+
+    async fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
+        self.read(offset, bytes).await
+    }
 
     fn capacity(&self) -> usize {
         self.capacity()
@@ -404,11 +408,11 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> embedded_storage_async::nor_flash
     const ERASE_SIZE: usize = ERASE_SIZE;
 
     async fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
-        self.erase(from, to)
+        self.blocking_erase(from, to)
     }
 
     async fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
-        self.write(offset, bytes)
+        self.blocking_write(offset, bytes)
     }
 }
 

embassy-rp/src/uart/buffered.rs

@@ -749,15 +749,15 @@ mod eh02 {
 mod eh1 {
     use super::*;
 
-    impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for BufferedUart<'d, T> {
+    impl<'d, T: Instance> embedded_hal_nb::serial::ErrorType for BufferedUartRx<'d, T> {
         type Error = Error;
     }
 
-    impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for BufferedUartTx<'d, T> {
+    impl<'d, T: Instance> embedded_hal_nb::serial::ErrorType for BufferedUartTx<'d, T> {
         type Error = Error;
     }
 
-    impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for BufferedUartRx<'d, T> {
+    impl<'d, T: Instance> embedded_hal_nb::serial::ErrorType for BufferedUart<'d, T> {
         type Error = Error;
     }
 
@@ -767,16 +767,6 @@ mod eh1 {
         }
     }
 
-    impl<'d, T: Instance> embedded_hal_1::serial::Write for BufferedUartTx<'d, T> {
-        fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
-            self.blocking_write(buffer).map(drop)
-        }
-
-        fn flush(&mut self) -> Result<(), Self::Error> {
-            self.blocking_flush()
-        }
-    }
-
     impl<'d, T: Instance> embedded_hal_nb::serial::Write for BufferedUartTx<'d, T> {
         fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
             self.blocking_write(&[char]).map(drop).map_err(nb::Error::Other)
@@ -793,16 +783,6 @@ mod eh1 {
         }
     }
 
-    impl<'d, T: Instance> embedded_hal_1::serial::Write for BufferedUart<'d, T> {
-        fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
-            self.blocking_write(buffer).map(drop)
-        }
-
-        fn flush(&mut self) -> Result<(), Self::Error> {
-            self.blocking_flush()
-        }
-    }
-
     impl<'d, T: Instance> embedded_hal_nb::serial::Write for BufferedUart<'d, T> {
         fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
             self.blocking_write(&[char]).map(drop).map_err(nb::Error::Other)

embassy-rp/src/uart/mod.rs

@@ -807,26 +807,26 @@ mod eh02 {
 mod eh1 {
     use super::*;
 
-    impl embedded_hal_1::serial::Error for Error {
+    impl embedded_hal_nb::serial::Error for Error {
-        fn kind(&self) -> embedded_hal_1::serial::ErrorKind {
+        fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
             match *self {
-                Self::Framing => embedded_hal_1::serial::ErrorKind::FrameFormat,
+                Self::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat,
-                Self::Break => embedded_hal_1::serial::ErrorKind::Other,
+                Self::Break => embedded_hal_nb::serial::ErrorKind::Other,
-                Self::Overrun => embedded_hal_1::serial::ErrorKind::Overrun,
+                Self::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun,
-                Self::Parity => embedded_hal_1::serial::ErrorKind::Parity,
+                Self::Parity => embedded_hal_nb::serial::ErrorKind::Parity,
             }
         }
     }
 
-    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::ErrorType for Uart<'d, T, M> {
+    impl<'d, T: Instance, M: Mode> embedded_hal_nb::serial::ErrorType for UartRx<'d, T, M> {
         type Error = Error;
     }
 
-    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::ErrorType for UartTx<'d, T, M> {
+    impl<'d, T: Instance, M: Mode> embedded_hal_nb::serial::ErrorType for UartTx<'d, T, M> {
         type Error = Error;
     }
 
-    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::ErrorType for UartRx<'d, T, M> {
+    impl<'d, T: Instance, M: Mode> embedded_hal_nb::serial::ErrorType for Uart<'d, T, M> {
         type Error = Error;
     }
 
@@ -851,16 +851,6 @@ mod eh1 {
         }
     }
 
-    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::Write for UartTx<'d, T, M> {
-        fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
-            self.blocking_write(buffer)
-        }
-
-        fn flush(&mut self) -> Result<(), Self::Error> {
-            self.blocking_flush()
-        }
-    }
-
     impl<'d, T: Instance, M: Mode> embedded_hal_nb::serial::Write for UartTx<'d, T, M> {
         fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
             self.blocking_write(&[char]).map_err(nb::Error::Other)
@@ -877,16 +867,6 @@ mod eh1 {
         }
     }
 
-    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::Write for Uart<'d, T, M> {
-        fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
-            self.blocking_write(buffer)
-        }
-
-        fn flush(&mut self) -> Result<(), Self::Error> {
-            self.blocking_flush()
-        }
-    }
-
     impl<'d, T: Instance, M: Mode> embedded_hal_nb::serial::Write for Uart<'d, T, M> {
         fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
             self.blocking_write(&[char]).map_err(nb::Error::Other)

embassy-stm32-wpan/src/mac/driver.rs

@@ -28,7 +28,9 @@ impl<'d> embassy_net_driver::Driver for Driver<'d> {
     type TxToken<'a> = TxToken<'d> where Self: 'a;
 
     fn receive(&mut self, cx: &mut Context) -> Option<(Self::RxToken<'_>, Self::TxToken<'_>)> {
-        if self.runner.rx_channel.poll_ready_to_receive(cx) && self.runner.tx_buf_channel.poll_ready_to_receive(cx) {
+        if self.runner.rx_channel.poll_ready_to_receive(cx).is_ready()
+            && self.runner.tx_buf_channel.poll_ready_to_receive(cx).is_ready()
+        {
             Some((
                 RxToken {
                     rx: &self.runner.rx_channel,
@@ -44,7 +46,7 @@ impl<'d> embassy_net_driver::Driver for Driver<'d> {
     }
 
     fn transmit(&mut self, cx: &mut Context) -> Option<Self::TxToken<'_>> {
-        if self.runner.tx_buf_channel.poll_ready_to_receive(cx) {
+        if self.runner.tx_buf_channel.poll_ready_to_receive(cx).is_ready() {
             Some(TxToken {
                 tx: &self.runner.tx_channel,
                 tx_buf: &self.runner.tx_buf_channel,
@@ -91,7 +93,7 @@ impl<'d> embassy_net_driver::RxToken for RxToken<'d> {
     {
         // Only valid data events should be put into the queue
 
-        let data_event = match self.rx.try_recv().unwrap() {
+        let data_event = match self.rx.try_receive().unwrap() {
             MacEvent::McpsDataInd(data_event) => data_event,
             _ => unreachable!(),
         };
@@ -111,7 +113,7 @@ impl<'d> embassy_net_driver::TxToken for TxToken<'d> {
         F: FnOnce(&mut [u8]) -> R,
     {
         // Only valid tx buffers should be put into the queue
-        let buf = self.tx_buf.try_recv().unwrap();
+        let buf = self.tx_buf.try_receive().unwrap();
         let r = f(&mut buf[..len]);
 
         // The tx channel should always be of equal capacity to the tx_buf channel

embassy-stm32-wpan/src/mac/runner.rs

@@ -73,7 +73,7 @@ impl<'a> Runner<'a> {
                 let mut msdu_handle = 0x02;
 
                 loop {
-                    let (buf, len) = self.tx_channel.recv().await;
+                    let (buf, len) = self.tx_channel.receive().await;
                     let _wm = self.write_mutex.lock().await;
 
                     // The mutex should be dropped on the next loop iteration

embassy-stm32/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 src_base = "https://github.com/embassy-rs/embassy/blob/embassy-stm32-v$VERSION/embassy-stm32/src/"
 src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-stm32/src/"
 
-features = ["nightly", "defmt", "unstable-pac", "unstable-traits", "exti", "time-driver-any", "time"]
+features = ["nightly", "defmt", "unstable-pac", "unstable-traits", "exti", "time-driver-any", "time", "low-power"]
 flavors = [
     { regex_feature = "stm32f0.*", target = "thumbv6m-none-eabi" },
     { regex_feature = "stm32f1.*", target = "thumbv7m-none-eabi" },
@@ -38,11 +38,12 @@ embassy-hal-internal = {version = "0.1.0", path = "../embassy-hal-internal", fea
 embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" }
 embassy-net-driver = { version = "0.1.0", path = "../embassy-net-driver" }
 embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optional = true }
+embassy-executor = { version = "0.3.0", path = "../embassy-executor", optional = true }
 
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
-embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.11", optional = true}
+embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1", optional = true}
-embedded-hal-async = { version = "=0.2.0-alpha.2", optional = true}
+embedded-hal-async = { version = "=1.0.0-rc.1", optional = true}
-embedded-hal-nb = { version = "=1.0.0-alpha.3", optional = true}
+embedded-hal-nb = { version = "=1.0.0-rc.1", optional = true}
 
 embedded-storage = "0.3.0"
 embedded-storage-async = { version = "0.4.0", optional = true }
@@ -57,7 +58,7 @@ sdio-host = "0.5.0"
 embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
 critical-section = "1.1"
 atomic-polyfill = "1.0.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7eddb78e705905af4c1dd2359900db3e78a3c500" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2b87e34c661e19ff6dc603fabfe7fe99ab7261f7" }
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -76,7 +77,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7eddb78e705905af4c1dd2359900db3e78a3c500", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2b87e34c661e19ff6dc603fabfe7fe99ab7261f7", default-features = false, features = ["metadata"]}
 
 [features]
 default = ["rt"]
@@ -88,6 +89,8 @@ rt = ["stm32-metapac/rt"]
 defmt = ["dep:defmt", "bxcan/unstable-defmt", "embassy-sync/defmt", "embassy-embedded-hal/defmt", "embassy-hal-internal/defmt", "embedded-io-async?/defmt-03", "embassy-usb-driver?/defmt", "embassy-net-driver/defmt", "embassy-time?/defmt"]
 
 exti = []
+low-power = [ "dep:embassy-executor", "embassy-executor/arch-cortex-m" ]
+embassy-executor = []
 
 ## Automatically generate `memory.x` file using [`stm32-metapac`](https://docs.rs/stm32-metapac/)
 memory-x = ["stm32-metapac/memory-x"]

embassy-stm32/build.rs

@@ -356,6 +356,8 @@ fn main() {
                     }
                     fn enable() {
                         critical_section::with(|_| {
+                            #[cfg(feature = "low-power")]
+                            crate::rcc::clock_refcount_add();
                             crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(true));
                             #after_enable
                         })
@@ -363,6 +365,8 @@ fn main() {
                     fn disable() {
                         critical_section::with(|_| {
                             crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(false));
+                            #[cfg(feature = "low-power")]
+                            crate::rcc::clock_refcount_sub();
                         })
                     }
                     fn reset() {

embassy-stm32/src/adc/mod.rs

@@ -1,6 +1,6 @@
 #![macro_use]
 
-#[cfg(not(adc_f3))]
+#[cfg(not(any(adc_f3, adc_f3_v2)))]
 #[cfg_attr(adc_f1, path = "f1.rs")]
 #[cfg_attr(adc_v1, path = "v1.rs")]
 #[cfg_attr(adc_v2, path = "v2.rs")]
@@ -8,16 +8,16 @@
 #[cfg_attr(adc_v4, path = "v4.rs")]
 mod _version;
 
-#[cfg(not(any(adc_f1, adc_f3)))]
+#[cfg(not(any(adc_f1, adc_f3, adc_f3_v2)))]
 mod resolution;
 mod sample_time;
 
-#[cfg(not(adc_f3))]
+#[cfg(not(any(adc_f3, adc_f3_v2)))]
 #[allow(unused)]
 pub use _version::*;
-#[cfg(not(any(adc_f1, adc_f3)))]
+#[cfg(not(any(adc_f1, adc_f3, adc_f3_v2)))]
 pub use resolution::Resolution;
-#[cfg(not(adc_f3))]
+#[cfg(not(any(adc_f3, adc_f3_v2)))]
 pub use sample_time::SampleTime;
 
 use crate::peripherals;
@@ -25,14 +25,14 @@ use crate::peripherals;
 pub struct Adc<'d, T: Instance> {
     #[allow(unused)]
     adc: crate::PeripheralRef<'d, T>,
-    #[cfg(not(adc_f3))]
+    #[cfg(not(any(adc_f3, adc_f3_v2)))]
     sample_time: SampleTime,
 }
 
 pub(crate) mod sealed {
     pub trait Instance {
         fn regs() -> crate::pac::adc::Adc;
-        #[cfg(not(any(adc_f1, adc_v1, adc_f3)))]
+        #[cfg(not(any(adc_f1, adc_v1, adc_f3, adc_f3_v2)))]
         fn common_regs() -> crate::pac::adccommon::AdcCommon;
     }
 
@@ -60,7 +60,7 @@ foreach_peripheral!(
             fn regs() -> crate::pac::adc::Adc {
                 crate::pac::$inst
             }
-            #[cfg(not(any(adc_f1, adc_v1, adc_f3)))]
+            #[cfg(not(any(adc_f1, adc_v1, adc_f3, adc_f3_v2)))]
             fn common_regs() -> crate::pac::adccommon::AdcCommon {
                 foreach_peripheral!{
                     (adccommon, $common_inst:ident) => {

embassy-stm32/src/adc/sample_time.rs

@@ -1,4 +1,4 @@
-#[cfg(not(adc_f3))]
+#[cfg(not(any(adc_f3, adc_f3_v2)))]
 macro_rules! impl_sample_time {
     ($default_doc:expr, $default:ident, ($(($doc:expr, $variant:ident, $pac_variant:ident)),*)) => {
         #[doc = concat!("ADC sample time\n\nThe default setting is ", $default_doc, " ADC clock cycles.")]

embassy-stm32/src/can/bxcan.rs

@@ -478,7 +478,7 @@ impl<'c, 'd, T: Instance> CanRx<'c, 'd, T> {
     pub async fn read(&mut self) -> Result<Envelope, BusError> {
         poll_fn(|cx| {
             T::state().err_waker.register(cx.waker());
-            if let Poll::Ready(envelope) = T::state().rx_queue.recv().poll_unpin(cx) {
+            if let Poll::Ready(envelope) = T::state().rx_queue.receive().poll_unpin(cx) {
                 return Poll::Ready(Ok(envelope));
             } else if let Some(err) = self.curr_error() {
                 return Poll::Ready(Err(err));
@@ -493,7 +493,7 @@ impl<'c, 'd, T: Instance> CanRx<'c, 'd, T> {
     ///
     /// Returns [Err(TryReadError::Empty)] if there are no frames in the rx queue.
     pub fn try_read(&mut self) -> Result<Envelope, TryReadError> {
-        if let Ok(envelope) = T::state().rx_queue.try_recv() {
+        if let Ok(envelope) = T::state().rx_queue.try_receive() {
             return Ok(envelope);
         }
 
@@ -506,14 +506,7 @@ impl<'c, 'd, T: Instance> CanRx<'c, 'd, T> {
 
     /// Waits while receive queue is empty.
     pub async fn wait_not_empty(&mut self) {
-        poll_fn(|cx| {
+        poll_fn(|cx| T::state().rx_queue.poll_ready_to_receive(cx)).await
-            if T::state().rx_queue.poll_ready_to_receive(cx) {
-                Poll::Ready(())
-            } else {
-                Poll::Pending
-            }
-        })
-        .await
     }
 
     fn curr_error(&self) -> Option<BusError> {

embassy-stm32/src/flash/h7.rs

@@ -11,7 +11,7 @@ pub const fn is_default_layout() -> bool {
 }
 
 const fn is_dual_bank() -> bool {
-    FLASH_REGIONS.len() == 2
+    FLASH_REGIONS.len() >= 2
 }
 
 pub fn get_flash_regions() -> &'static [&'static FlashRegion] {
@@ -49,6 +49,7 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
     };
     bank.cr().write(|w| {
         w.set_pg(true);
+        #[cfg(flash_h7)]
         w.set_psize(2); // 32 bits at once
     });
     cortex_m::asm::isb();
@@ -85,7 +86,10 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
     let bank = pac::FLASH.bank(sector.bank as usize);
     bank.cr().modify(|w| {
         w.set_ser(true);
-        w.set_snb(sector.index_in_bank)
+        #[cfg(flash_h7)]
+        w.set_snb(sector.index_in_bank);
+        #[cfg(flash_h7ab)]
+        w.set_ssn(sector.index_in_bank);
     });
 
     bank.cr().modify(|w| {
@@ -126,6 +130,10 @@ unsafe fn blocking_wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
                 error!("incerr");
                 return Err(Error::Seq);
             }
+            if sr.crcrderr() {
+                error!("crcrderr");
+                return Err(Error::Seq);
+            }
             if sr.operr() {
                 return Err(Error::Prog);
             }

embassy-stm32/src/flash/mod.rs

@@ -65,9 +65,11 @@ impl FlashRegion {
 #[cfg_attr(flash_f7, path = "f7.rs")]
 #[cfg_attr(flash_g0, path = "g0.rs")]
 #[cfg_attr(flash_h7, path = "h7.rs")]
+#[cfg_attr(flash_h7ab, path = "h7.rs")]
 #[cfg_attr(
     not(any(
-        flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f3, flash_f4, flash_f7, flash_g0, flash_h7
+        flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f3, flash_f4, flash_f7, flash_g0, flash_h7,
+        flash_h7ab
     )),
     path = "other.rs"
 )]

embassy-stm32/src/lib.rs

@@ -47,6 +47,8 @@ pub mod i2c;
 pub mod i2s;
 #[cfg(stm32wb)]
 pub mod ipcc;
+#[cfg(feature = "low-power")]
+pub mod low_power;
 #[cfg(quadspi)]
 pub mod qspi;
 #[cfg(rng)]

embassy-stm32/src/low_power.rs

@@ -0,0 +1,139 @@
+use core::arch::asm;
+use core::marker::PhantomData;
+
+use cortex_m::peripheral::SCB;
+use embassy_executor::*;
+use embassy_time::Duration;
+
+use crate::interrupt;
+use crate::interrupt::typelevel::Interrupt;
+use crate::pac::EXTI;
+use crate::rcc::low_power_ready;
+
+const THREAD_PENDER: usize = usize::MAX;
+const THRESHOLD: Duration = Duration::from_millis(500);
+
+use crate::rtc::{Rtc, RtcInstant};
+
+static mut RTC: Option<&'static Rtc> = None;
+
+foreach_interrupt! {
+    (RTC, rtc, $block:ident, WKUP, $irq:ident) => {
+        #[interrupt]
+        unsafe fn $irq() {
+            Executor::on_wakeup_irq();
+        }
+    };
+}
+
+pub fn stop_with_rtc(rtc: &'static Rtc) {
+    crate::interrupt::typelevel::RTC_WKUP::unpend();
+    unsafe { crate::interrupt::typelevel::RTC_WKUP::enable() };
+
+    EXTI.rtsr(0).modify(|w| w.set_line(22, true));
+    EXTI.imr(0).modify(|w| w.set_line(22, true));
+
+    unsafe { RTC = Some(rtc) };
+}
+
+pub fn start_wakeup_alarm(requested_duration: embassy_time::Duration) -> RtcInstant {
+    unsafe { RTC }.unwrap().start_wakeup_alarm(requested_duration)
+}
+
+pub fn stop_wakeup_alarm() -> RtcInstant {
+    unsafe { RTC }.unwrap().stop_wakeup_alarm()
+}
+
+/// Thread mode executor, using WFE/SEV.
+///
+/// This is the simplest and most common kind of executor. It runs on
+/// thread mode (at the lowest priority level), and uses the `WFE` ARM instruction
+/// to sleep when it has no more work to do. When a task is woken, a `SEV` instruction
+/// is executed, to make the `WFE` exit from sleep and poll the task.
+///
+/// This executor allows for ultra low power consumption for chips where `WFE`
+/// triggers low-power sleep without extra steps. If your chip requires extra steps,
+/// you may use [`raw::Executor`] directly to program custom behavior.
+pub struct Executor {
+    inner: raw::Executor,
+    not_send: PhantomData<*mut ()>,
+}
+
+impl Executor {
+    /// Create a new Executor.
+    pub fn new() -> Self {
+        Self {
+            inner: raw::Executor::new(THREAD_PENDER as *mut ()),
+            not_send: PhantomData,
+        }
+    }
+
+    unsafe fn on_wakeup_irq() {
+        info!("on wakeup irq");
+
+        cortex_m::asm::bkpt();
+    }
+
+    fn time_until_next_alarm(&self) -> Duration {
+        Duration::from_secs(3)
+    }
+
+    fn get_scb() -> SCB {
+        unsafe { cortex_m::Peripherals::steal() }.SCB
+    }
+
+    fn configure_pwr(&self) {
+        trace!("configure_pwr");
+
+        if !low_power_ready() {
+            return;
+        }
+
+        let time_until_next_alarm = self.time_until_next_alarm();
+        if time_until_next_alarm < THRESHOLD {
+            return;
+        }
+
+        trace!("low power stop required");
+
+        critical_section::with(|_| {
+            trace!("executor: set wakeup alarm...");
+
+            start_wakeup_alarm(time_until_next_alarm);
+
+            trace!("low power wait for rtc ready...");
+
+            Self::get_scb().set_sleepdeep();
+        });
+    }
+
+    /// Run the executor.
+    ///
+    /// The `init` closure is called with a [`Spawner`] that spawns tasks on
+    /// this executor. Use it to spawn the initial task(s). After `init` returns,
+    /// the executor starts running the tasks.
+    ///
+    /// To spawn more tasks later, you may keep copies of the [`Spawner`] (it is `Copy`),
+    /// for example by passing it as an argument to the initial tasks.
+    ///
+    /// This function requires `&'static mut self`. This means you have to store the
+    /// Executor instance in a place where it'll live forever and grants you mutable
+    /// access. There's a few ways to do this:
+    ///
+    /// - a [StaticCell](https://docs.rs/static_cell/latest/static_cell/) (safe)
+    /// - a `static mut` (unsafe)
+    /// - a local variable in a function you know never returns (like `fn main() -> !`), upgrading its lifetime with `transmute`. (unsafe)
+    ///
+    /// This function never returns.
+    pub fn run(&'static mut self, init: impl FnOnce(Spawner)) -> ! {
+        init(self.inner.spawner());
+
+        loop {
+            unsafe {
+                self.inner.poll();
+                self.configure_pwr();
+                asm!("wfe");
+            };
+        }
+    }
+}

embassy-stm32/src/rcc/f2.rs

@@ -378,22 +378,6 @@ pub(crate) unsafe fn init(config: Config) {
     // Reference: STM32F215xx/217xx datasheet Table 13. General operating conditions
     assert!(ahb_freq <= Hertz(120_000_000));
 
-    let flash_ws = unwrap!(config.voltage.wait_states(ahb_freq));
-    FLASH.acr().modify(|w| w.set_latency(flash_ws));
-
-    RCC.cfgr().modify(|w| {
-        w.set_sw(sw.into());
-        w.set_hpre(config.ahb_pre.into());
-        w.set_ppre1(config.apb1_pre.into());
-        w.set_ppre2(config.apb2_pre.into());
-    });
-    while RCC.cfgr().read().sws().to_bits() != sw.to_bits() {}
-
-    // Turn off HSI to save power if we don't need it
-    if !config.hsi {
-        RCC.cr().modify(|w| w.set_hsion(false));
-    }
-
     let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
         APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
         pre => {
@@ -414,6 +398,22 @@ pub(crate) unsafe fn init(config: Config) {
     // Reference: STM32F215xx/217xx datasheet Table 13. General operating conditions
     assert!(apb2_freq <= Hertz(60_000_000));
 
+    let flash_ws = unwrap!(config.voltage.wait_states(ahb_freq));
+    FLASH.acr().modify(|w| w.set_latency(flash_ws));
+
+    RCC.cfgr().modify(|w| {
+        w.set_sw(sw.into());
+        w.set_hpre(config.ahb_pre.into());
+        w.set_ppre1(config.apb1_pre.into());
+        w.set_ppre2(config.apb2_pre.into());
+    });
+    while RCC.cfgr().read().sws().to_bits() != sw.to_bits() {}
+
+    // Turn off HSI to save power if we don't need it
+    if !config.hsi {
+        RCC.cr().modify(|w| w.set_hsion(false));
+    }
+
     set_freqs(Clocks {
         sys: sys_clk,
         ahb1: ahb_freq,

embassy-stm32/src/rcc/f4.rs

@@ -473,6 +473,11 @@ pub(crate) unsafe fn init(config: Config) {
         Rtc::set_clock_source(clock_source);
     });
 
+    let rtc = match config.rtc {
+        Some(RtcClockSource::LSI) => Some(LSI_FREQ),
+        _ => None,
+    };
+
     set_freqs(Clocks {
         sys: Hertz(sysclk),
         apb1: Hertz(pclk1),
@@ -492,6 +497,8 @@ pub(crate) unsafe fn init(config: Config) {
 
         #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
         pllsai: None,
+
+        rtc: rtc,
     });
 }
 

embassy-stm32/src/rcc/h7.rs

@@ -200,6 +200,7 @@ fn flash_setup(rcc_aclk: u32, vos: VoltageScale) {
 
     // See RM0433 Rev 7 Table 17. FLASH recommended number of wait
     // states and programming delay
+    #[cfg(flash_h7)]
     let (wait_states, progr_delay) = match vos {
         // VOS 0 range VCORE 1.26V - 1.40V
         VoltageScale::Scale0 => match rcc_aclk_mhz {
@@ -239,6 +240,50 @@ fn flash_setup(rcc_aclk: u32, vos: VoltageScale) {
         },
     };
 
+    // See RM0455 Rev 10 Table 16. FLASH recommended number of wait
+    // states and programming delay
+    #[cfg(flash_h7ab)]
+    let (wait_states, progr_delay) = match vos {
+        // VOS 0 range VCORE 1.25V - 1.35V
+        VoltageScale::Scale0 => match rcc_aclk_mhz {
+            0..=42 => (0, 0),
+            43..=84 => (1, 0),
+            85..=126 => (2, 1),
+            127..=168 => (3, 1),
+            169..=210 => (4, 2),
+            211..=252 => (5, 2),
+            253..=280 => (6, 3),
+            _ => (7, 3),
+        },
+        // VOS 1 range VCORE 1.15V - 1.25V
+        VoltageScale::Scale1 => match rcc_aclk_mhz {
+            0..=38 => (0, 0),
+            39..=76 => (1, 0),
+            77..=114 => (2, 1),
+            115..=152 => (3, 1),
+            153..=190 => (4, 2),
+            191..=225 => (5, 2),
+            _ => (7, 3),
+        },
+        // VOS 2 range VCORE 1.05V - 1.15V
+        VoltageScale::Scale2 => match rcc_aclk_mhz {
+            0..=34 => (0, 0),
+            35..=68 => (1, 0),
+            69..=102 => (2, 1),
+            103..=136 => (3, 1),
+            137..=160 => (4, 2),
+            _ => (7, 3),
+        },
+        // VOS 3 range VCORE 0.95V - 1.05V
+        VoltageScale::Scale3 => match rcc_aclk_mhz {
+            0..=22 => (0, 0),
+            23..=44 => (1, 0),
+            45..=66 => (2, 1),
+            67..=88 => (3, 1),
+            _ => (7, 3),
+        },
+    };
+
     FLASH.acr().write(|w| {
         w.set_wrhighfreq(progr_delay);
         w.set_latency(wait_states)
@@ -538,8 +583,6 @@ pub(crate) unsafe fn init(mut config: Config) {
     let requested_pclk4 = config.pclk4.map(|v| v.0).unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
     let (rcc_pclk4, ppre4_bits, ppre4, _) = ppre_calculate(requested_pclk4, rcc_hclk, pclk_max, None);
 
-    flash_setup(rcc_aclk, pwr_vos);
-
     // Start switching clocks -------------------
 
     // Ensure CSI is on and stable
@@ -595,6 +638,8 @@ pub(crate) unsafe fn init(mut config: Config) {
     // core voltage
     while RCC.d1cfgr().read().d1cpre().to_bits() != d1cpre_bits {}
 
+    flash_setup(rcc_aclk, pwr_vos);
+
     // APB1 / APB2 Prescaler
     RCC.d2cfgr().modify(|w| {
         w.set_d2ppre1(Dppre::from_bits(ppre1_bits));

embassy-stm32/src/rcc/l4.rs

@@ -410,10 +410,11 @@ pub(crate) unsafe fn init(config: Config) {
         while RCC.cfgr().read().sws() != Sw::MSI {}
     }
 
+    RCC.apb1enr1().modify(|w| w.set_pwren(true));
+
     match config.rtc_mux {
         RtcClockSource::LSE32 => {
             // 1. Unlock the backup domain
-            RCC.apb1enr1().modify(|w| w.set_pwren(true));
             PWR.cr1().modify(|w| w.set_dbp(true));
 
             // 2. Setup the LSE

embassy-stm32/src/rcc/mod.rs

@@ -9,7 +9,7 @@ use crate::time::Hertz;
 #[cfg_attr(rcc_f0, path = "f0.rs")]
 #[cfg_attr(any(rcc_f1, rcc_f100, rcc_f1cl), path = "f1.rs")]
 #[cfg_attr(rcc_f2, path = "f2.rs")]
-#[cfg_attr(rcc_f3, path = "f3.rs")]
+#[cfg_attr(any(rcc_f3, rcc_f3_v2), path = "f3.rs")]
 #[cfg_attr(any(rcc_f4, rcc_f410), path = "f4.rs")]
 #[cfg_attr(rcc_f7, path = "f7.rs")]
 #[cfg_attr(rcc_c0, path = "c0.rs")]
@@ -26,6 +26,8 @@ use crate::time::Hertz;
 #[cfg_attr(any(rcc_h5, rcc_h50), path = "h5.rs")]
 mod _version;
 pub use _version::*;
+#[cfg(feature = "low-power")]
+use atomic_polyfill::{AtomicU32, Ordering};
 
 #[derive(Clone, Copy, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -74,11 +76,30 @@ pub struct Clocks {
     #[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab))]
     pub adc: Option<Hertz>,
 
-    #[cfg(rcc_wb)]
+    #[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
     /// Set only if the lsi or lse is configured
     pub rtc: Option<Hertz>,
 }
 
+#[cfg(feature = "low-power")]
+static CLOCK_REFCOUNT: AtomicU32 = AtomicU32::new(0);
+
+#[cfg(feature = "low-power")]
+pub fn low_power_ready() -> bool {
+    CLOCK_REFCOUNT.load(Ordering::SeqCst) == 0
+}
+
+#[cfg(feature = "low-power")]
+pub(crate) fn clock_refcount_add() {
+    // We don't check for overflow because constructing more than u32 peripherals is unlikely
+    CLOCK_REFCOUNT.fetch_add(1, Ordering::Relaxed);
+}
+
+#[cfg(feature = "low-power")]
+pub(crate) fn clock_refcount_sub() {
+    assert!(CLOCK_REFCOUNT.fetch_sub(1, Ordering::Relaxed) != 0);
+}
+
 /// Frozen clock frequencies
 ///
 /// The existence of this value indicates that the clock configuration can no longer be changed

embassy-stm32/src/rcc/wl.rs

@@ -2,6 +2,7 @@ pub use super::common::{AHBPrescaler, APBPrescaler, VoltageScale};
 use crate::pac::pwr::vals::Dbp;
 use crate::pac::{FLASH, PWR, RCC};
 use crate::rcc::{set_freqs, Clocks};
+use crate::rtc::{Rtc, RtcClockSource as RCS};
 use crate::time::Hertz;
 
 /// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
@@ -229,6 +230,8 @@ pub(crate) unsafe fn init(config: Config) {
 
             // Wait until LSE is running
             while !RCC.bdcr().read().lserdy() {}
+
+            Rtc::set_clock_source(RCS::LSE);
         }
         RtcClockSource::LSI32 => {
             // Turn on the internal 32 kHz LSI oscillator
@@ -236,6 +239,8 @@ pub(crate) unsafe fn init(config: Config) {
 
             // Wait until LSI is running
             while !RCC.csr().read().lsirdy() {}
+
+            Rtc::set_clock_source(RCS::LSI);
         }
     }
 

embassy-stm32/src/rtc/mod.rs

@@ -13,6 +13,7 @@ pub use self::datetime::{DateTime, DayOfWeek, Error as DateTimeError};
 )]
 #[cfg_attr(any(rtc_v3, rtc_v3u5), path = "v3.rs")]
 mod _version;
+#[allow(unused_imports)]
 pub use _version::*;
 use embassy_hal_internal::Peripheral;
 

embassy-stm32/src/rtc/v2.rs

@@ -5,6 +5,128 @@ use crate::pac::rtc::Rtc;
 use crate::peripherals::RTC;
 use crate::rtc::sealed::Instance;
 
+#[cfg(all(feature = "time", any(stm32wb, stm32f4)))]
+pub struct RtcInstant {
+    ssr: u16,
+    st: u8,
+}
+
+#[cfg(all(feature = "time", any(stm32wb, stm32f4)))]
+impl RtcInstant {
+    pub fn now() -> Self {
+        // TODO: read value twice
+        use crate::rtc::bcd2_to_byte;
+
+        let tr = RTC::regs().tr().read();
+        let tr2 = RTC::regs().tr().read();
+        let ssr = RTC::regs().ssr().read().ss();
+        let ssr2 = RTC::regs().ssr().read().ss();
+
+        let st = bcd2_to_byte((tr.st(), tr.su()));
+        let st2 = bcd2_to_byte((tr2.st(), tr2.su()));
+
+        assert!(st == st2);
+        assert!(ssr == ssr2);
+
+        let _ = RTC::regs().dr().read();
+
+        trace!("ssr: {}", ssr);
+        trace!("st: {}", st);
+
+        Self { ssr, st }
+    }
+}
+
+#[cfg(all(feature = "time", any(stm32wb, stm32f4)))]
+impl core::ops::Sub for RtcInstant {
+    type Output = embassy_time::Duration;
+
+    fn sub(self, rhs: Self) -> Self::Output {
+        use embassy_time::{Duration, TICK_HZ};
+
+        let st = if self.st < rhs.st { self.st + 60 } else { self.st };
+
+        // TODO: read prescaler
+
+        let self_ticks = st as u32 * 256 + (255 - self.ssr as u32);
+        let other_ticks = rhs.st as u32 * 256 + (255 - rhs.ssr as u32);
+        let rtc_ticks = self_ticks - other_ticks;
+
+        trace!("self, other, rtc ticks: {}, {}, {}", self_ticks, other_ticks, rtc_ticks);
+
+        Duration::from_ticks(
+            ((((st as u32 * 256 + (255u32 - self.ssr as u32)) - (rhs.st as u32 * 256 + (255u32 - rhs.ssr as u32)))
+                * TICK_HZ as u32) as u32
+                / 256u32) as u64,
+        )
+    }
+}
+
+#[allow(dead_code)]
+#[derive(Clone, Copy, Debug)]
+pub(crate) enum WakeupPrescaler {
+    Div2,
+    Div4,
+    Div8,
+    Div16,
+}
+
+#[cfg(any(stm32wb, stm32f4))]
+impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
+    fn from(val: WakeupPrescaler) -> Self {
+        use crate::pac::rtc::vals::Wucksel;
+
+        match val {
+            WakeupPrescaler::Div2 => Wucksel::DIV2,
+            WakeupPrescaler::Div4 => Wucksel::DIV4,
+            WakeupPrescaler::Div8 => Wucksel::DIV8,
+            WakeupPrescaler::Div16 => Wucksel::DIV16,
+        }
+    }
+}
+
+#[cfg(any(stm32wb, stm32f4))]
+impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
+    fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
+        use crate::pac::rtc::vals::Wucksel;
+
+        match val {
+            Wucksel::DIV2 => WakeupPrescaler::Div2,
+            Wucksel::DIV4 => WakeupPrescaler::Div4,
+            Wucksel::DIV8 => WakeupPrescaler::Div8,
+            Wucksel::DIV16 => WakeupPrescaler::Div16,
+            _ => unreachable!(),
+        }
+    }
+}
+
+impl From<WakeupPrescaler> for u32 {
+    fn from(val: WakeupPrescaler) -> Self {
+        match val {
+            WakeupPrescaler::Div2 => 2,
+            WakeupPrescaler::Div4 => 4,
+            WakeupPrescaler::Div8 => 8,
+            WakeupPrescaler::Div16 => 16,
+        }
+    }
+}
+
+#[allow(dead_code)]
+impl WakeupPrescaler {
+    pub fn compute_min(val: u32) -> Self {
+        *[
+            WakeupPrescaler::Div2,
+            WakeupPrescaler::Div4,
+            WakeupPrescaler::Div8,
+            WakeupPrescaler::Div16,
+        ]
+        .iter()
+        .skip_while(|psc| <WakeupPrescaler as Into<u32>>::into(**psc) <= val)
+        .next()
+        .unwrap_or(&WakeupPrescaler::Div16)
+    }
+}
+
 impl super::Rtc {
     fn unlock_registers() {
         #[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
@@ -22,6 +144,69 @@ impl super::Rtc {
         }
     }
 
+    #[allow(dead_code)]
+    #[cfg(all(feature = "time", any(stm32wb, stm32f4)))]
+    /// start the wakeup alarm and return the actual duration of the alarm
+    /// the actual duration will be the closest value possible that is less
+    /// than the requested duration.
+    ///
+    /// note: this api is exposed for testing purposes until low power is implemented.
+    /// it is not intended to be public
+    pub(crate) fn start_wakeup_alarm(&self, requested_duration: embassy_time::Duration) -> RtcInstant {
+        use embassy_time::{Duration, TICK_HZ};
+
+        use crate::rcc::get_freqs;
+
+        let rtc_hz = unsafe { get_freqs() }.rtc.unwrap().0 as u64;
+
+        let rtc_ticks = requested_duration.as_ticks() * rtc_hz / TICK_HZ;
+        let prescaler = WakeupPrescaler::compute_min((rtc_ticks / u16::MAX as u64) as u32);
+
+        // adjust the rtc ticks to the prescaler
+        let rtc_ticks = rtc_ticks / (<WakeupPrescaler as Into<u32>>::into(prescaler) as u64);
+        let rtc_ticks = if rtc_ticks >= u16::MAX as u64 {
+            u16::MAX - 1
+        } else {
+            rtc_ticks as u16
+        };
+
+        let duration = Duration::from_ticks(
+            rtc_ticks as u64 * TICK_HZ * (<WakeupPrescaler as Into<u32>>::into(prescaler) as u64) / rtc_hz,
+        );
+
+        trace!("set wakeup timer for {} ms", duration.as_millis());
+
+        self.write(false, |regs| {
+            regs.cr().modify(|w| w.set_wutie(true));
+
+            regs.cr().modify(|w| w.set_wute(false));
+            regs.isr().modify(|w| w.set_wutf(false));
+            while !regs.isr().read().wutwf() {}
+
+            regs.cr().modify(|w| w.set_wucksel(prescaler.into()));
+            regs.cr().modify(|w| w.set_wute(true));
+        });
+
+        RtcInstant::now()
+    }
+
+    #[allow(dead_code)]
+    #[cfg(all(feature = "time", any(stm32wb, stm32f4)))]
+    /// stop the wakeup alarm and return the time remaining
+    ///
+    /// note: this api is exposed for testing purposes until low power is implemented.
+    /// it is not intended to be public
+    pub(crate) fn stop_wakeup_alarm(&self) -> RtcInstant {
+        trace!("disable wakeup timer...");
+
+        self.write(false, |regs| {
+            regs.cr().modify(|w| w.set_wute(false));
+            regs.isr().modify(|w| w.set_wutf(false));
+        });
+
+        RtcInstant::now()
+    }
+
     #[allow(dead_code)]
     pub(crate) fn set_clock_source(clock_source: RtcClockSource) {
         #[cfg(not(rtc_v2wb))]
@@ -170,7 +355,7 @@ impl super::Rtc {
         })
     }
 
-    pub(super) fn write<F, R>(&mut self, init_mode: bool, f: F) -> R
+    pub(super) fn write<F, R>(&self, init_mode: bool, f: F) -> R
     where
         F: FnOnce(&crate::pac::rtc::Rtc) -> R,
     {

embassy-stm32/src/timer/complementary_pwm.rs

@@ -100,14 +100,19 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
     }
 
     pub fn get_max_duty(&self) -> u16 {
-        self.inner.get_max_compare_value()
+        self.inner.get_max_compare_value() + 1
     }
 
     pub fn set_duty(&mut self, channel: Channel, duty: u16) {
-        assert!(duty < self.get_max_duty());
+        assert!(duty <= self.get_max_duty());
         self.inner.set_compare_value(channel, duty)
     }
 
+    pub fn set_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+        self.inner.set_output_polarity(channel, polarity);
+        self.inner.set_complementary_output_polarity(channel, polarity);
+    }
+
     /// Set the dead time as a proportion of max_duty
     pub fn set_dead_time(&mut self, value: u16) {
         let (ckd, value) = compute_dead_time_value(value);

embassy-stm32/src/timer/mod.rs

@@ -53,6 +53,8 @@ pub(crate) mod sealed {
 
         fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode);
 
+        fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity);
+
         fn enable_channel(&mut self, channel: Channel, enable: bool);
 
         fn set_compare_value(&mut self, channel: Channel, value: u16);
@@ -61,6 +63,8 @@ pub(crate) mod sealed {
     }
 
     pub trait ComplementaryCaptureCompare16bitInstance: CaptureCompare16bitInstance {
+        fn set_complementary_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity);
+
         fn set_dead_time_clock_division(&mut self, value: vals::Ckd);
 
         fn set_dead_time_value(&mut self, value: u8);
@@ -71,6 +75,8 @@ pub(crate) mod sealed {
     pub trait CaptureCompare32bitInstance: GeneralPurpose32bitInstance {
         fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode);
 
+        fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity);
+
         fn enable_channel(&mut self, channel: Channel, enable: bool);
 
         fn set_compare_value(&mut self, channel: Channel, value: u32);
@@ -125,6 +131,21 @@ impl From<OutputCompareMode> for stm32_metapac::timer::vals::Ocm {
     }
 }
 
+#[derive(Clone, Copy)]
+pub enum OutputPolarity {
+    ActiveHigh,
+    ActiveLow,
+}
+
+impl From<OutputPolarity> for bool {
+    fn from(mode: OutputPolarity) -> Self {
+        match mode {
+            OutputPolarity::ActiveHigh => false,
+            OutputPolarity::ActiveLow => true,
+        }
+    }
+}
+
 pub trait Basic16bitInstance: sealed::Basic16bitInstance + 'static {}
 
 pub trait GeneralPurpose16bitInstance: sealed::GeneralPurpose16bitInstance + 'static {}
@@ -265,6 +286,13 @@ macro_rules! impl_compare_capable_16bit {
                     .modify(|w| w.set_ocm(raw_channel % 2, mode.into()));
             }
 
+            fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+                use sealed::GeneralPurpose16bitInstance;
+                Self::regs_gp16()
+                    .ccer()
+                    .modify(|w| w.set_ccp(channel.raw(), polarity.into()));
+            }
+
             fn enable_channel(&mut self, channel: Channel, enable: bool) {
                 use sealed::GeneralPurpose16bitInstance;
                 Self::regs_gp16()
@@ -325,6 +353,13 @@ foreach_interrupt! {
                 Self::regs_gp32().ccmr_output(raw_channel / 2).modify(|w| w.set_ocm(raw_channel % 2, mode.into()));
             }
 
+            fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+                use crate::timer::sealed::GeneralPurpose32bitInstance;
+                Self::regs_gp32()
+                    .ccer()
+                    .modify(|w| w.set_ccp(channel.raw(), polarity.into()));
+            }
+
             fn enable_channel(&mut self, channel: Channel, enable: bool) {
                 use crate::timer::sealed::GeneralPurpose32bitInstance;
                 Self::regs_gp32().ccer().modify(|w| w.set_cce(channel.raw(), enable));
@@ -388,6 +423,13 @@ foreach_interrupt! {
                     .modify(|w| w.set_ocm(raw_channel % 2, mode.into()));
             }
 
+            fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+                use crate::timer::sealed::AdvancedControlInstance;
+                Self::regs_advanced()
+                    .ccer()
+                    .modify(|w| w.set_ccp(channel.raw(), polarity.into()));
+            }
+
             fn enable_channel(&mut self, channel: Channel, enable: bool) {
                 use crate::timer::sealed::AdvancedControlInstance;
                 Self::regs_advanced()
@@ -409,6 +451,13 @@ foreach_interrupt! {
         }
 
         impl sealed::ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {
+            fn set_complementary_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+                use crate::timer::sealed::AdvancedControlInstance;
+                Self::regs_advanced()
+                    .ccer()
+                    .modify(|w| w.set_ccnp(channel.raw(), polarity.into()));
+            }
+
             fn set_dead_time_clock_division(&mut self, value: vals::Ckd) {
                 use crate::timer::sealed::AdvancedControlInstance;
                 Self::regs_advanced().cr1().modify(|w| w.set_ckd(value));

embassy-stm32/src/timer/simple_pwm.rs

@@ -97,11 +97,15 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
     }
 
     pub fn get_max_duty(&self) -> u16 {
-        self.inner.get_max_compare_value()
+        self.inner.get_max_compare_value() + 1
     }
 
     pub fn set_duty(&mut self, channel: Channel, duty: u16) {
-        assert!(duty < self.get_max_duty());
+        assert!(duty <= self.get_max_duty());
         self.inner.set_compare_value(channel, duty)
     }
+
+    pub fn set_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+        self.inner.set_output_polarity(channel, polarity);
+    }
 }