stm32/rcc: LSE xtal is 32768hz, not 32000hz.

Fixes #2043

ci.sh

@@ -1,9 +1,12 @@
 #!/bin/bash
 
-set -euo pipefail
+set -eo pipefail
 
 export RUSTFLAGS=-Dwarnings
 export DEFMT_LOG=trace,embassy_hal_internal=debug,embassy_net_esp_hosted=debug,cyw43=info,cyw43_pio=info,smoltcp=info
+if [[ -z "${CARGO_TARGET_DIR}" ]]; then
+    export CARGO_TARGET_DIR=target_ci
+fi
 
 TARGET=$(rustc -vV | sed -n 's|host: ||p')
 
@@ -36,7 +39,7 @@ cargo batch  \
     --- build --release --manifest-path embassy-time/Cargo.toml --target thumbv6m-none-eabi --features nightly,defmt,defmt-timestamp-uptime,tick-hz-32_768,generic-queue-8 \
     --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv4,medium-ethernet \
     --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,dhcpv4,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,dhcpv4,medium-ethernet,nightly \
+    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,dhcpv4,medium-ethernet,nightly,dhcpv4-hostname \
     --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv6,medium-ethernet \
     --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv6,medium-ieee802154 \
     --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv6,medium-ethernet,medium-ieee802154 \
@@ -203,7 +206,7 @@ cargo batch  \
 
 rm out/tests/stm32wb55rg/wpan_mac
 rm out/tests/stm32wb55rg/wpan_ble
-
+rm out/tests/stm32f207zg/eth
 
 if [[ -z "${TELEPROBE_TOKEN-}" ]]; then
     echo No teleprobe token found, skipping running HIL tests

embassy-embedded-hal/src/flash/partition/mod.rs

@@ -11,7 +11,7 @@ pub use asynch::Partition;
 pub use blocking::BlockingPartition;
 
 /// Partition error
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error<T> {
     /// The requested flash area is outside the partition

embassy-net-ppp/Cargo.toml

@@ -15,7 +15,7 @@ log = ["dep:log", "ppproto/log"]
 defmt = { version = "0.3", optional = true }
 log = { version = "0.4.14", optional = true }
 
-embedded-io-async = { version = "0.5.0" }
+embedded-io-async = { version = "0.6.0" }
 embassy-net-driver-channel = { version = "0.1.0", path = "../embassy-net-driver-channel" }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
 ppproto = { version = "0.1.2"}

embassy-net-ppp/src/lib.rs

@@ -11,7 +11,7 @@ use core::mem::MaybeUninit;
 use embassy_futures::select::{select, Either};
 use embassy_net_driver_channel as ch;
 use embassy_net_driver_channel::driver::LinkState;
-use embedded_io_async::{BufRead, Write, WriteAllError};
+use embedded_io_async::{BufRead, Write};
 use ppproto::pppos::{BufferFullError, PPPoS, PPPoSAction};
 pub use ppproto::{Config, Ipv4Status};
 
@@ -49,23 +49,12 @@ pub enum RunError<E> {
     Read(E),
     /// Writing to the serial port failed.
     Write(E),
-    /// Writing to the serial port wrote zero bytes, indicating it can't accept more data.
-    WriteZero,
     /// Writing to the serial got EOF.
     Eof,
     /// PPP protocol was terminated by the peer
     Terminated,
 }
 
-impl<E> From<WriteAllError<E>> for RunError<E> {
-    fn from(value: WriteAllError<E>) -> Self {
-        match value {
-            WriteAllError::Other(e) => Self::Write(e),
-            WriteAllError::WriteZero => Self::WriteZero,
-        }
-    }
-}
-
 impl<'d> Runner<'d> {
     /// You must call this in a background task for the driver to operate.
     ///
@@ -125,7 +114,7 @@ impl<'d> Runner<'d> {
                             buf[..pkt.len()].copy_from_slice(pkt);
                             rx_chan.rx_done(pkt.len());
                         }
-                        PPPoSAction::Transmit(n) => rw.write_all(&tx_buf[..n]).await?,
+                        PPPoSAction::Transmit(n) => rw.write_all(&tx_buf[..n]).await.map_err(RunError::Write)?,
                     }
 
                     let status = ppp.status();
@@ -148,7 +137,7 @@ impl<'d> Runner<'d> {
                 }
                 Either::Second(pkt) => {
                     match ppp.send(pkt, &mut tx_buf) {
-                        Ok(n) => rw.write_all(&tx_buf[..n]).await?,
+                        Ok(n) => rw.write_all(&tx_buf[..n]).await.map_err(RunError::Write)?,
                         Err(BufferFullError) => unreachable!(),
                     }
                     tx_chan.tx_done();

embassy-net/Cargo.toml

@@ -33,6 +33,7 @@ udp = ["smoltcp/socket-udp"]
 tcp = ["smoltcp/socket-tcp"]
 dns = ["smoltcp/socket-dns", "smoltcp/proto-dns"]
 dhcpv4 = ["proto-ipv4", "medium-ethernet", "smoltcp/socket-dhcpv4"]
+dhcpv4-hostname = ["dhcpv4"]
 proto-ipv4 = ["smoltcp/proto-ipv4"]
 proto-ipv6 = ["smoltcp/proto-ipv6"]
 medium-ethernet = ["smoltcp/medium-ethernet"]
@@ -53,7 +54,7 @@ smoltcp = { version = "0.10.0", default-features = false, features = [
 embassy-net-driver = { version = "0.1.0", path = "../embassy-net-driver" }
 embassy-time = { version = "0.1.3", path = "../embassy-time" }
 embassy-sync = { version = "0.3.0", path = "../embassy-sync" }
-embedded-io-async = { version = "0.5.0", optional = true }
+embedded-io-async = { version = "0.6.0", optional = true }
 
 managed = { version = "0.8.0", default-features = false, features = [ "map" ] }
 heapless = { version = "0.7.5", default-features = false }
@@ -62,5 +63,5 @@ generic-array = { version = "0.14.4", default-features = false }
 stable_deref_trait = { version = "1.2.0", default-features = false }
 futures = { version = "0.3.17", default-features = false, features = [ "async-await" ] }
 atomic-pool = "1.0"
-embedded-nal-async = { version = "0.5.0", optional = true }
+embedded-nal-async = { version = "0.6.0", optional = true }
 atomic-polyfill = { version = "1.0" }

embassy-net/src/lib.rs

@@ -39,7 +39,7 @@ use smoltcp::socket::dhcpv4::{self, RetryConfig};
 pub use smoltcp::wire::EthernetAddress;
 #[cfg(any(feature = "medium-ethernet", feature = "medium-ieee802154", feature = "medium-ip"))]
 pub use smoltcp::wire::HardwareAddress;
-#[cfg(feature = "udp")]
+#[cfg(any(feature = "udp", feature = "tcp"))]
 pub use smoltcp::wire::IpListenEndpoint;
 #[cfg(feature = "medium-ieee802154")]
 pub use smoltcp::wire::{Ieee802154Address, Ieee802154Frame};
@@ -56,12 +56,22 @@ const LOCAL_PORT_MIN: u16 = 1025;
 const LOCAL_PORT_MAX: u16 = 65535;
 #[cfg(feature = "dns")]
 const MAX_QUERIES: usize = 4;
+#[cfg(feature = "dhcpv4-hostname")]
+const MAX_HOSTNAME_LEN: usize = 32;
 
 /// Memory resources needed for a network stack.
 pub struct StackResources<const SOCK: usize> {
     sockets: [SocketStorage<'static>; SOCK],
     #[cfg(feature = "dns")]
     queries: [Option<dns::DnsQuery>; MAX_QUERIES],
+    #[cfg(feature = "dhcpv4-hostname")]
+    hostname: core::cell::UnsafeCell<HostnameResources>,
+}
+
+#[cfg(feature = "dhcpv4-hostname")]
+struct HostnameResources {
+    option: smoltcp::wire::DhcpOption<'static>,
+    data: [u8; MAX_HOSTNAME_LEN],
 }
 
 impl<const SOCK: usize> StackResources<SOCK> {
@@ -73,6 +83,11 @@ impl<const SOCK: usize> StackResources<SOCK> {
             sockets: [SocketStorage::EMPTY; SOCK],
             #[cfg(feature = "dns")]
             queries: [INIT; MAX_QUERIES],
+            #[cfg(feature = "dhcpv4-hostname")]
+            hostname: core::cell::UnsafeCell::new(HostnameResources {
+                option: smoltcp::wire::DhcpOption { kind: 0, data: &[] },
+                data: [0; MAX_HOSTNAME_LEN],
+            }),
         }
     }
 }
@@ -104,6 +119,7 @@ pub struct StaticConfigV6 {
 /// DHCP configuration.
 #[cfg(feature = "dhcpv4")]
 #[derive(Debug, Clone, PartialEq, Eq)]
+#[non_exhaustive]
 pub struct DhcpConfig {
     /// Maximum lease duration.
     ///
@@ -120,6 +136,9 @@ pub struct DhcpConfig {
     pub server_port: u16,
     /// Client port. This is almost always 68. Do not change unless you know what you're doing.
     pub client_port: u16,
+    /// Our hostname. This will be sent to the DHCP server as Option 12.
+    #[cfg(feature = "dhcpv4-hostname")]
+    pub hostname: Option<heapless::String<MAX_HOSTNAME_LEN>>,
 }
 
 #[cfg(feature = "dhcpv4")]
@@ -131,6 +150,8 @@ impl Default for DhcpConfig {
             ignore_naks: Default::default(),
             server_port: smoltcp::wire::DHCP_SERVER_PORT,
             client_port: smoltcp::wire::DHCP_CLIENT_PORT,
+            #[cfg(feature = "dhcpv4-hostname")]
+            hostname: None,
         }
     }
 }
@@ -232,6 +253,8 @@ struct Inner<D: Driver> {
     dns_socket: SocketHandle,
     #[cfg(feature = "dns")]
     dns_waker: WakerRegistration,
+    #[cfg(feature = "dhcpv4-hostname")]
+    hostname: &'static mut core::cell::UnsafeCell<HostnameResources>,
 }
 
 pub(crate) struct SocketStack {
@@ -307,6 +330,8 @@ impl<D: Driver> Stack<D> {
             )),
             #[cfg(feature = "dns")]
             dns_waker: WakerRegistration::new(),
+            #[cfg(feature = "dhcpv4-hostname")]
+            hostname: &mut resources.hostname,
         };
 
         #[cfg(feature = "proto-ipv4")]
@@ -673,6 +698,25 @@ impl<D: Driver> Inner<D> {
                 socket.set_max_lease_duration(c.max_lease_duration.map(crate::time::duration_to_smoltcp));
                 socket.set_ports(c.server_port, c.client_port);
                 socket.set_retry_config(c.retry_config);
+
+                socket.set_outgoing_options(&[]);
+                #[cfg(feature = "dhcpv4-hostname")]
+                if let Some(h) = c.hostname {
+                    // safety: we just did set_outgoing_options([]) so we know the socket is no longer holding a reference.
+                    let hostname = unsafe { &mut *self.hostname.get() };
+
+                    // create data
+                    // safety: we know the buffer lives forever, new borrows the StackResources for 'static.
+                    // also we won't modify it until next call to this function.
+                    hostname.data[..h.len()].copy_from_slice(h.as_bytes());
+                    let data: &[u8] = &hostname.data[..h.len()];
+                    let data: &'static [u8] = unsafe { core::mem::transmute(data) };
+
+                    // set the option.
+                    hostname.option = smoltcp::wire::DhcpOption { data, kind: 12 };
+                    socket.set_outgoing_options(core::slice::from_ref(&hostname.option));
+                }
+
                 socket.reset();
             }
             _ => {

embassy-nrf/Cargo.toml

@@ -103,8 +103,8 @@ embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optiona
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
 embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1", optional = true}
 embedded-hal-async = { version = "=1.0.0-rc.1", optional = true}
-embedded-io = { version = "0.5.0" }
+embedded-io = { version = "0.6.0" }
-embedded-io-async = { version = "0.5.0", optional = true }
+embedded-io-async = { version = "0.6.0", optional = true }
 
 defmt = { version = "0.3", optional = true }
 log = { version = "0.4.14", optional = true }

embassy-rp/Cargo.toml

@@ -75,8 +75,8 @@ cortex-m = "0.7.6"
 critical-section = "1.1"
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
 chrono = { version = "0.4", default-features = false, optional = true }
-embedded-io = { version = "0.5.0" }
+embedded-io = { version = "0.6.0" }
-embedded-io-async = { version = "0.5.0", optional = true }
+embedded-io-async = { version = "0.6.0", optional = true }
 embedded-storage = { version = "0.3" }
 embedded-storage-async = { version = "0.4.0", optional = true }
 rand_core = "0.6.4"

embassy-rp/src/bootsel.rs

@@ -0,0 +1,83 @@
+//! Boot Select button
+//!
+//! The RP2040 rom supports a BOOTSEL button that is used to enter the USB bootloader
+//! if held during reset. To avoid wasting GPIO pins, the button is multiplexed onto
+//! the CS pin of the QSPI flash, but that makes it somewhat expensive and complicated
+//! to utilize outside of the rom's bootloader.
+//!
+//! This module provides functionality to poll BOOTSEL from an embassy application.
+
+use crate::flash::in_ram;
+
+impl crate::peripherals::BOOTSEL {
+    /// Polls the BOOTSEL button. Returns true if the button is pressed.
+    ///
+    /// Polling isn't cheap, as this function waits for core 1 to finish it's current
+    /// task and for any DMAs from flash to complete
+    pub fn is_pressed(&mut self) -> bool {
+        let mut cs_status = Default::default();
+
+        unsafe { in_ram(|| cs_status = ram_helpers::read_cs_status()) }.expect("Must be called from Core 0");
+
+        // bootsel is active low, so invert
+        !cs_status.infrompad()
+    }
+}
+
+mod ram_helpers {
+    use rp_pac::io::regs::GpioStatus;
+
+    /// Temporally reconfigures the CS gpio and returns the GpioStatus.
+
+    /// This function runs from RAM so it can disable flash XIP.
+    ///
+    /// # Safety
+    ///
+    /// The caller must ensure flash is idle and will remain idle.
+    /// This function must live in ram. It uses inline asm to avoid any
+    /// potential calls to ABI functions that might be in flash.
+    #[inline(never)]
+    #[link_section = ".data.ram_func"]
+    #[cfg(target_arch = "arm")]
+    pub unsafe fn read_cs_status() -> GpioStatus {
+        let result: u32;
+
+        // Magic value, used as both OEOVER::DISABLE and delay loop counter
+        let magic = 0x2000;
+
+        core::arch::asm!(
+            ".equiv GPIO_STATUS, 0x0",
+            ".equiv GPIO_CTRL,   0x4",
+
+            "ldr {orig_ctrl}, [{cs_gpio}, $GPIO_CTRL]",
+
+            // The BOOTSEL pulls the flash's CS line low though a 1K resistor.
+            // this is weak enough to avoid disrupting normal operation.
+            // But, if we disable CS's output drive and allow it to float...
+            "str {val}, [{cs_gpio}, $GPIO_CTRL]",
+
+            // ...then wait for the state to settle...
+            "1:", // ~4000 cycle delay loop
+            "subs {val}, #8",
+            "bne 1b",
+
+            // ...we can read the current state of bootsel
+            "ldr {val}, [{cs_gpio}, $GPIO_STATUS]",
+
+            // Finally, restore CS to normal operation so XIP can continue
+            "str {orig_ctrl}, [{cs_gpio}, $GPIO_CTRL]",
+
+            cs_gpio = in(reg) rp_pac::IO_QSPI.gpio(1).as_ptr(),
+            orig_ctrl = out(reg) _,
+            val = inout(reg) magic => result,
+            options(nostack),
+        );
+
+        core::mem::transmute(result)
+    }
+
+    #[cfg(not(target_arch = "arm"))]
+    pub unsafe fn read_cs_status() -> GpioStatus {
+        unimplemented!()
+    }
+}

embassy-rp/src/flash.rs

@@ -131,7 +131,7 @@ impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> Flash<'d, T, M, FLASH_SI
 
         let len = to - from;
 
-        unsafe { self.in_ram(|| ram_helpers::flash_range_erase(from, len))? };
+        unsafe { in_ram(|| ram_helpers::flash_range_erase(from, len))? };
 
         Ok(())
     }
@@ -156,7 +156,7 @@ impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> Flash<'d, T, M, FLASH_SI
 
             let unaligned_offset = offset as usize - start;
 
-            unsafe { self.in_ram(|| ram_helpers::flash_range_program(unaligned_offset as u32, &pad_buf))? }
+            unsafe { in_ram(|| ram_helpers::flash_range_program(unaligned_offset as u32, &pad_buf))? }
         }
 
         let remaining_len = bytes.len() - start_padding;
@@ -174,12 +174,12 @@ impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> Flash<'d, T, M, FLASH_SI
             if bytes.as_ptr() as usize >= 0x2000_0000 {
                 let aligned_data = &bytes[start_padding..end_padding];
 
-                unsafe { self.in_ram(|| ram_helpers::flash_range_program(aligned_offset as u32, aligned_data))? }
+                unsafe { in_ram(|| ram_helpers::flash_range_program(aligned_offset as u32, aligned_data))? }
             } else {
                 for chunk in bytes[start_padding..end_padding].chunks_exact(PAGE_SIZE) {
                     let mut ram_buf = [0xFF_u8; PAGE_SIZE];
                     ram_buf.copy_from_slice(chunk);
-                    unsafe { self.in_ram(|| ram_helpers::flash_range_program(aligned_offset as u32, &ram_buf))? }
+                    unsafe { in_ram(|| ram_helpers::flash_range_program(aligned_offset as u32, &ram_buf))? }
                     aligned_offset += PAGE_SIZE;
                 }
             }
@@ -194,47 +194,15 @@ impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> Flash<'d, T, M, FLASH_SI
 
             let unaligned_offset = end_offset - (PAGE_SIZE - rem_offset);
 
-            unsafe { self.in_ram(|| ram_helpers::flash_range_program(unaligned_offset as u32, &pad_buf))? }
+            unsafe { in_ram(|| ram_helpers::flash_range_program(unaligned_offset as u32, &pad_buf))? }
         }
 
         Ok(())
     }
 
-    /// Make sure to uphold the contract points with rp2040-flash.
-    /// - interrupts must be disabled
-    /// - DMA must not access flash memory
-    unsafe fn in_ram(&mut self, operation: impl FnOnce()) -> Result<(), Error> {
-        // Make sure we're running on CORE0
-        let core_id: u32 = pac::SIO.cpuid().read();
-        if core_id != 0 {
-            return Err(Error::InvalidCore);
-        }
-
-        // Make sure CORE1 is paused during the entire duration of the RAM function
-        crate::multicore::pause_core1();
-
-        critical_section::with(|_| {
-            // Wait for all DMA channels in flash to finish before ram operation
-            const SRAM_LOWER: u32 = 0x2000_0000;
-            for n in 0..crate::dma::CHANNEL_COUNT {
-                let ch = crate::pac::DMA.ch(n);
-                while ch.read_addr().read() < SRAM_LOWER && ch.ctrl_trig().read().busy() {}
-            }
-            // Wait for completion of any background reads
-            while pac::XIP_CTRL.stream_ctr().read().0 > 0 {}
-
-            // Run our flash operation in RAM
-            operation();
-        });
-
-        // Resume CORE1 execution
-        crate::multicore::resume_core1();
-        Ok(())
-    }
-
     /// Read SPI flash unique ID
     pub fn blocking_unique_id(&mut self, uid: &mut [u8]) -> Result<(), Error> {
-        unsafe { self.in_ram(|| ram_helpers::flash_unique_id(uid))? };
+        unsafe { in_ram(|| ram_helpers::flash_unique_id(uid))? };
         Ok(())
     }
 
@@ -242,7 +210,7 @@ impl<'d, T: Instance, M: Mode, const FLASH_SIZE: usize> Flash<'d, T, M, FLASH_SI
     pub fn blocking_jedec_id(&mut self) -> Result<u32, Error> {
         let mut jedec = None;
         unsafe {
-            self.in_ram(|| {
+            in_ram(|| {
                 jedec.replace(ram_helpers::flash_jedec_id());
             })?;
         };
@@ -871,6 +839,38 @@ mod ram_helpers {
     }
 }
 
+/// Make sure to uphold the contract points with rp2040-flash.
+/// - interrupts must be disabled
+/// - DMA must not access flash memory
+pub(crate) unsafe fn in_ram(operation: impl FnOnce()) -> Result<(), Error> {
+    // Make sure we're running on CORE0
+    let core_id: u32 = pac::SIO.cpuid().read();
+    if core_id != 0 {
+        return Err(Error::InvalidCore);
+    }
+
+    // Make sure CORE1 is paused during the entire duration of the RAM function
+    crate::multicore::pause_core1();
+
+    critical_section::with(|_| {
+        // Wait for all DMA channels in flash to finish before ram operation
+        const SRAM_LOWER: u32 = 0x2000_0000;
+        for n in 0..crate::dma::CHANNEL_COUNT {
+            let ch = crate::pac::DMA.ch(n);
+            while ch.read_addr().read() < SRAM_LOWER && ch.ctrl_trig().read().busy() {}
+        }
+        // Wait for completion of any background reads
+        while pac::XIP_CTRL.stream_ctr().read().0 > 0 {}
+
+        // Run our flash operation in RAM
+        operation();
+    });
+
+    // Resume CORE1 execution
+    crate::multicore::resume_core1();
+    Ok(())
+}
+
 mod sealed {
     pub trait Instance {}
     pub trait Mode {}

embassy-rp/src/i2c.rs

@@ -6,13 +6,12 @@ use embassy_hal_internal::{into_ref, PeripheralRef};
 use embassy_sync::waitqueue::AtomicWaker;
 use pac::i2c;
 
-use crate::gpio::sealed::Pin;
 use crate::gpio::AnyPin;
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::{interrupt, pac, peripherals, Peripheral};
 
 /// I2C error abort reason
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum AbortReason {
     /// A bus operation was not acknowledged, e.g. due to the addressed device
@@ -27,7 +26,7 @@ pub enum AbortReason {
 }
 
 /// I2C error
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
     /// I2C abort with error
@@ -295,13 +294,24 @@ impl<'d, T: Instance> I2c<'d, T, Async> {
 
     pub async fn read_async(&mut self, addr: u16, buffer: &mut [u8]) -> Result<(), Error> {
         Self::setup(addr)?;
-        self.read_async_internal(buffer, false, true).await
+        self.read_async_internal(buffer, true, true).await
     }
 
     pub async fn write_async(&mut self, addr: u16, bytes: impl IntoIterator<Item = u8>) -> Result<(), Error> {
         Self::setup(addr)?;
         self.write_async_internal(bytes, true).await
     }
+
+    pub async fn write_read_async(
+        &mut self,
+        addr: u16,
+        bytes: impl IntoIterator<Item = u8>,
+        buffer: &mut [u8],
+    ) -> Result<(), Error> {
+        Self::setup(addr)?;
+        self.write_async_internal(bytes, false).await?;
+        self.read_async_internal(buffer, true, true).await
+    }
 }
 
 pub struct InterruptHandler<T: Instance> {
@@ -318,6 +328,22 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
     }
 }
 
+pub(crate) fn set_up_i2c_pin<'d, P, T>(pin: &P)
+where
+    P: core::ops::Deref<Target = T>,
+    T: crate::gpio::Pin,
+{
+    pin.gpio().ctrl().write(|w| w.set_funcsel(3));
+    pin.pad_ctrl().write(|w| {
+        w.set_schmitt(true);
+        w.set_slewfast(false);
+        w.set_ie(true);
+        w.set_od(false);
+        w.set_pue(true);
+        w.set_pde(false);
+    });
+}
+
 impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
     fn new_inner(
         _peri: impl Peripheral<P = T> + 'd,
@@ -355,23 +381,8 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
         p.ic_rx_tl().write(|w| w.set_rx_tl(0));
 
         // Configure SCL & SDA pins
-        scl.gpio().ctrl().write(|w| w.set_funcsel(3));
+        set_up_i2c_pin(&scl);
-        sda.gpio().ctrl().write(|w| w.set_funcsel(3));
+        set_up_i2c_pin(&sda);
-
-        scl.pad_ctrl().write(|w| {
-            w.set_schmitt(true);
-            w.set_ie(true);
-            w.set_od(false);
-            w.set_pue(true);
-            w.set_pde(false);
-        });
-        sda.pad_ctrl().write(|w| {
-            w.set_schmitt(true);
-            w.set_ie(true);
-            w.set_od(false);
-            w.set_pue(true);
-            w.set_pde(false);
-        });
 
         // Configure baudrate
 
@@ -713,7 +724,7 @@ mod nightly {
 
             Self::setup(addr)?;
             self.write_async_internal(write.iter().cloned(), false).await?;
-            self.read_async_internal(read, false, true).await
+            self.read_async_internal(read, true, true).await
         }
 
         async fn transaction(&mut self, address: A, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> {

embassy-rp/src/i2c_slave.rs

@@ -5,12 +5,14 @@ use core::task::Poll;
 use embassy_hal_internal::into_ref;
 use pac::i2c;
 
-use crate::i2c::{i2c_reserved_addr, AbortReason, Instance, InterruptHandler, SclPin, SdaPin, FIFO_SIZE};
+use crate::i2c::{
+    i2c_reserved_addr, set_up_i2c_pin, AbortReason, Instance, InterruptHandler, SclPin, SdaPin, FIFO_SIZE,
+};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::{pac, Peripheral};
 
 /// I2C error
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[non_exhaustive]
 pub enum Error {
@@ -100,23 +102,8 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
         p.ic_rx_tl().write(|w| w.set_rx_tl(0));
 
         // Configure SCL & SDA pins
-        scl.gpio().ctrl().write(|w| w.set_funcsel(3));
+        set_up_i2c_pin(&scl);
-        sda.gpio().ctrl().write(|w| w.set_funcsel(3));
+        set_up_i2c_pin(&sda);
-
-        scl.pad_ctrl().write(|w| {
-            w.set_schmitt(true);
-            w.set_ie(true);
-            w.set_od(false);
-            w.set_pue(true);
-            w.set_pde(false);
-        });
-        sda.pad_ctrl().write(|w| {
-            w.set_schmitt(true);
-            w.set_ie(true);
-            w.set_od(false);
-            w.set_pue(true);
-            w.set_pde(false);
-        });
 
         // Clear interrupts
         p.ic_clr_intr().read();

embassy-rp/src/lib.rs

@@ -10,6 +10,7 @@ mod critical_section_impl;
 mod intrinsics;
 
 pub mod adc;
+pub mod bootsel;
 pub mod clocks;
 pub mod dma;
 pub mod flash;
@@ -193,6 +194,7 @@ embassy_hal_internal::peripherals! {
     PIO1,
 
     WATCHDOG,
+    BOOTSEL,
 }
 
 macro_rules! select_bootloader {

embassy-stm32/Cargo.toml

@@ -59,15 +59,14 @@ sdio-host = "0.5.0"
 embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
 critical-section = "1.1"
 atomic-polyfill = "1.0.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-06d13dfd245cc9bf86fd88c35b401bdb84c079c4" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6bfa5a0dcec6a9bd42cea94ba11eeae1a17a7f2c" }
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
 stm32-fmc = "0.3.0"
-seq-macro = "0.3.0"
 cfg-if = "1.0.0"
-embedded-io = { version = "0.5.0" }
+embedded-io = { version = "0.6.0" }
-embedded-io-async = { version = "0.5.0", optional = true }
+embedded-io-async = { version = "0.6.0", optional = true }
 chrono = { version = "^0.4", default-features = false, optional = true}
 bit_field = "0.10.2"
 document-features = "0.2.7"
@@ -78,7 +77,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-06d13dfd245cc9bf86fd88c35b401bdb84c079c4", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6bfa5a0dcec6a9bd42cea94ba11eeae1a17a7f2c", default-features = false, features = ["metadata"]}
 
 
 [features]

embassy-stm32/build.rs

@@ -50,12 +50,14 @@ fn main() {
                 // We *shouldn't* have singletons for these, but the HAL currently requires
                 // singletons, for using with RccPeripheral to enable/disable clocks to them.
                 "rcc" => {
-                    if r.version.starts_with("h5") || r.version.starts_with("h7") || r.version.starts_with("f4") {
+                    for pin in p.pins {
-                        singletons.push("MCO1".to_string());
+                        if pin.signal.starts_with("MCO") {
-                        singletons.push("MCO2".to_string());
+                            let name = pin.signal.replace('_', "").to_string();
-                    }
+                            if !singletons.contains(&name) {
-                    if r.version.starts_with("l4") {
+                                println!("cargo:rustc-cfg={}", name.to_ascii_lowercase());
-                        singletons.push("MCO".to_string());
+                                singletons.push(name);
+                            }
+                        }
                     }
                     singletons.push(p.name.to_string());
                 }
@@ -751,25 +753,8 @@ fn main() {
                     let af = pin.af.unwrap_or(0);
 
                     // MCO is special
-                    if pin.signal.starts_with("MCO_") {
+                    if pin.signal.starts_with("MCO") {
-                        // Supported in H7 only for now
+                        peri = format_ident!("{}", pin.signal.replace('_', ""));
-                        if regs.version.starts_with("h5")
-                            || regs.version.starts_with("h7")
-                            || regs.version.starts_with("f4")
-                        {
-                            peri = format_ident!("{}", pin.signal.replace('_', ""));
-                        } else {
-                            continue;
-                        }
-                    }
-
-                    if pin.signal == "MCO" {
-                        // Supported in H7 only for now
-                        if regs.version.starts_with("l4") {
-                            peri = format_ident!("MCO");
-                        } else {
-                            continue;
-                        }
                     }
 
                     g.extend(quote! {
@@ -908,6 +893,105 @@ fn main() {
         }
     }
 
+    // ========
+    // Generate Div/Mul impls for RCC prescalers/dividers/multipliers.
+    let rcc_registers = METADATA
+        .peripherals
+        .iter()
+        .filter_map(|p| p.registers.as_ref())
+        .find(|r| r.kind == "rcc")
+        .unwrap()
+        .ir;
+
+    for e in rcc_registers.enums {
+        fn is_rcc_name(e: &str) -> bool {
+            match e {
+                "Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" => true,
+                "Timpre" | "Pllrclkpre" => false,
+                e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true,
+                _ => false,
+            }
+        }
+
+        #[derive(Copy, Clone, Debug)]
+        struct Frac {
+            num: u32,
+            denom: u32,
+        }
+
+        impl Frac {
+            fn simplify(self) -> Self {
+                let d = gcd(self.num, self.denom);
+                Self {
+                    num: self.num / d,
+                    denom: self.denom / d,
+                }
+            }
+        }
+
+        fn gcd(a: u32, b: u32) -> u32 {
+            if b == 0 {
+                return a;
+            }
+            gcd(b, a % b)
+        }
+
+        fn parse_num(n: &str) -> Result<Frac, ()> {
+            for prefix in ["DIV", "MUL"] {
+                if let Some(n) = n.strip_prefix(prefix) {
+                    let exponent = n.find('_').map(|e| n.len() - 1 - e).unwrap_or(0) as u32;
+                    let mantissa = n.replace('_', "").parse().map_err(|_| ())?;
+                    let f = Frac {
+                        num: mantissa,
+                        denom: 10u32.pow(exponent),
+                    };
+                    return Ok(f.simplify());
+                }
+            }
+            Err(())
+        }
+
+        if is_rcc_name(e.name) {
+            let enum_name = format_ident!("{}", e.name);
+            let mut muls = Vec::new();
+            let mut divs = Vec::new();
+            for v in e.variants {
+                let Ok(val) = parse_num(v.name) else {
+                    panic!("could not parse mul/div. enum={} variant={}", e.name, v.name)
+                };
+                let variant_name = format_ident!("{}", v.name);
+                let variant = quote!(crate::pac::rcc::vals::#enum_name::#variant_name);
+                let num = val.num;
+                let denom = val.denom;
+                muls.push(quote!(#variant => self * #num / #denom,));
+                divs.push(quote!(#variant => self * #denom / #num,));
+            }
+
+            g.extend(quote! {
+                impl core::ops::Div<crate::pac::rcc::vals::#enum_name> for crate::time::Hertz {
+                    type Output = crate::time::Hertz;
+                    fn div(self, rhs: crate::pac::rcc::vals::#enum_name) -> Self::Output {
+                        match rhs {
+                            #(#divs)*
+                            #[allow(unreachable_patterns)]
+                            _ => unreachable!(),
+                        }
+                    }
+                }
+                impl core::ops::Mul<crate::pac::rcc::vals::#enum_name> for crate::time::Hertz {
+                    type Output = crate::time::Hertz;
+                    fn mul(self, rhs: crate::pac::rcc::vals::#enum_name) -> Self::Output {
+                        match rhs {
+                            #(#muls)*
+                            #[allow(unreachable_patterns)]
+                            _ => unreachable!(),
+                        }
+                    }
+                }
+            });
+        }
+    }
+
     // ========
     // Write foreach_foo! macrotables
 

embassy-stm32/src/dac/mod.rs

@@ -11,7 +11,7 @@ use crate::{peripherals, Peripheral};
 
 #[derive(Debug, Copy, Clone, Eq, PartialEq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-/// Curstom Errors
+/// Custom Errors
 pub enum Error {
     UnconfiguredChannel,
     InvalidValue,
@@ -564,7 +564,7 @@ pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
 foreach_peripheral!(
     (dac, $inst:ident) => {
         // H7 uses single bit for both DAC1 and DAC2, this is a hack until a proper fix is implemented
-        #[cfg(rcc_h7)]
+        #[cfg(any(rcc_h7, rcc_h7rm0433))]
         impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
             fn frequency() -> crate::time::Hertz {
                 critical_section::with(|_| unsafe { crate::rcc::get_freqs().apb1 })
@@ -590,7 +590,7 @@ foreach_peripheral!(
             }
         }
 
-        #[cfg(rcc_h7)]
+        #[cfg(any(rcc_h7, rcc_h7rm0433))]
         impl crate::rcc::RccPeripheral for peripherals::$inst {}
 
         impl crate::dac::sealed::Instance for peripherals::$inst {

embassy-stm32/src/eth/generic_smi.rs

@@ -41,39 +41,40 @@ mod phy_consts {
 }
 use self::phy_consts::*;
 
-/// Generic SMI Ethernet PHY
+/// Generic SMI Ethernet PHY implementation
 pub struct GenericSMI {
+    phy_addr: u8,
     #[cfg(feature = "time")]
     poll_interval: Duration,
-    #[cfg(not(feature = "time"))]
-    _private: (),
 }
 
 impl GenericSMI {
-    pub fn new() -> Self {
+    /// Construct the PHY. It assumes the address `phy_addr` in the SMI communication
+    pub fn new(phy_addr: u8) -> Self {
         Self {
+            phy_addr,
             #[cfg(feature = "time")]
             poll_interval: Duration::from_millis(500),
-            #[cfg(not(feature = "time"))]
-            _private: (),
         }
     }
 }
 
 unsafe impl PHY for GenericSMI {
-    /// Reset PHY and wait for it to come out of reset.
     fn phy_reset<S: StationManagement>(&mut self, sm: &mut S) {
-        sm.smi_write(PHY_REG_BCR, PHY_REG_BCR_RESET);
+        sm.smi_write(self.phy_addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
-        while sm.smi_read(PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
+        while sm.smi_read(self.phy_addr, PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
     }
 
-    /// PHY initialisation.
     fn phy_init<S: StationManagement>(&mut self, sm: &mut S) {
         // Clear WU CSR
         self.smi_write_ext(sm, PHY_REG_WUCSR, 0);
 
         // Enable auto-negotiation
-        sm.smi_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M);
+        sm.smi_write(
+            self.phy_addr,
+            PHY_REG_BCR,
+            PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M,
+        );
     }
 
     fn poll_link<S: StationManagement>(&mut self, sm: &mut S, cx: &mut Context) -> bool {
@@ -83,7 +84,7 @@ unsafe impl PHY for GenericSMI {
         #[cfg(feature = "time")]
         let _ = Timer::after(self.poll_interval).poll_unpin(cx);
 
-        let bsr = sm.smi_read(PHY_REG_BSR);
+        let bsr = sm.smi_read(self.phy_addr, PHY_REG_BSR);
 
         // No link without autonegotiate
         if bsr & PHY_REG_BSR_ANDONE == 0 {
@@ -108,9 +109,9 @@ impl GenericSMI {
 
     // Writes a value to an extended PHY register in MMD address space
     fn smi_write_ext<S: StationManagement>(&mut self, sm: &mut S, reg_addr: u16, reg_data: u16) {
-        sm.smi_write(PHY_REG_CTL, 0x0003); // set address
+        sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x0003); // set address
-        sm.smi_write(PHY_REG_ADDAR, reg_addr);
+        sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_addr);
-        sm.smi_write(PHY_REG_CTL, 0x4003); // set data
+        sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x4003); // set data
-        sm.smi_write(PHY_REG_ADDAR, reg_data);
+        sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_data);
     }
 }

embassy-stm32/src/eth/mod.rs

@@ -134,9 +134,9 @@ impl<'a, 'd> embassy_net_driver::TxToken for TxToken<'a, 'd> {
 /// The methods cannot move out of self
 pub unsafe trait StationManagement {
     /// Read a register over SMI.
-    fn smi_read(&mut self, reg: u8) -> u16;
+    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16;
     /// Write a register over SMI.
-    fn smi_write(&mut self, reg: u8, val: u16);
+    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16);
 }
 
 /// Traits for an Ethernet PHY

embassy-stm32/src/eth/v1/mod.rs

@@ -107,7 +107,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
         tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
         phy: P,
         mac_addr: [u8; 6],
-        phy_addr: u8,
     ) -> Self {
         into_ref!(peri, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
 
@@ -227,7 +226,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
             station_management: EthernetStationManagement {
                 peri: PhantomData,
                 clock_range: clock_range,
-                phy_addr: phy_addr,
             },
             mac_addr,
             tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
@@ -271,15 +269,14 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
 pub struct EthernetStationManagement<T: Instance> {
     peri: PhantomData<T>,
     clock_range: Cr,
-    phy_addr: u8,
 }
 
 unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
-    fn smi_read(&mut self, reg: u8) -> u16 {
+    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
         let mac = ETH.ethernet_mac();
 
         mac.macmiiar().modify(|w| {
-            w.set_pa(self.phy_addr);
+            w.set_pa(phy_addr);
             w.set_mr(reg);
             w.set_mw(Mw::READ); // read operation
             w.set_cr(self.clock_range);
@@ -289,12 +286,12 @@ unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
         mac.macmiidr().read().md()
     }
 
-    fn smi_write(&mut self, reg: u8, val: u16) {
+    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
         let mac = ETH.ethernet_mac();
 
         mac.macmiidr().write(|w| w.set_md(val));
         mac.macmiiar().modify(|w| {
-            w.set_pa(self.phy_addr);
+            w.set_pa(phy_addr);
             w.set_mr(reg);
             w.set_mw(Mw::WRITE); // write
             w.set_cr(self.clock_range);

embassy-stm32/src/eth/v2/mod.rs

@@ -71,7 +71,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
         tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
         phy: P,
         mac_addr: [u8; 6],
-        phy_addr: u8,
     ) -> Self {
         into_ref!(peri, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
 
@@ -202,7 +201,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
             station_management: EthernetStationManagement {
                 peri: PhantomData,
                 clock_range: clock_range,
-                phy_addr: phy_addr,
             },
             mac_addr,
         };
@@ -242,15 +240,14 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
 pub struct EthernetStationManagement<T: Instance> {
     peri: PhantomData<T>,
     clock_range: u8,
-    phy_addr: u8,
 }
 
 unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
-    fn smi_read(&mut self, reg: u8) -> u16 {
+    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
         let mac = ETH.ethernet_mac();
 
         mac.macmdioar().modify(|w| {
-            w.set_pa(self.phy_addr);
+            w.set_pa(phy_addr);
             w.set_rda(reg);
             w.set_goc(0b11); // read
             w.set_cr(self.clock_range);
@@ -260,12 +257,12 @@ unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
         mac.macmdiodr().read().md()
     }
 
-    fn smi_write(&mut self, reg: u8, val: u16) {
+    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
         let mac = ETH.ethernet_mac();
 
         mac.macmdiodr().write(|w| w.set_md(val));
         mac.macmdioar().modify(|w| {
-            w.set_pa(self.phy_addr);
+            w.set_pa(phy_addr);
             w.set_rda(reg);
             w.set_goc(0b01); // write
             w.set_cr(self.clock_range);

embassy-stm32/src/flash/f0.rs

@@ -19,8 +19,10 @@ pub(crate) unsafe fn lock() {
 }
 
 pub(crate) unsafe fn unlock() {
-    pac::FLASH.keyr().write(|w| w.set_fkeyr(0x4567_0123));
+    if pac::FLASH.cr().read().lock() {
-    pac::FLASH.keyr().write(|w| w.set_fkeyr(0xCDEF_89AB));
+        pac::FLASH.keyr().write(|w| w.set_fkeyr(0x4567_0123));
+        pac::FLASH.keyr().write(|w| w.set_fkeyr(0xCDEF_89AB));
+    }
 }
 
 pub(crate) unsafe fn enable_blocking_write() {

embassy-stm32/src/flash/f3.rs

@@ -19,8 +19,10 @@ pub(crate) unsafe fn lock() {
 }
 
 pub(crate) unsafe fn unlock() {
-    pac::FLASH.keyr().write(|w| w.set_fkeyr(0x4567_0123));
+    if pac::FLASH.cr().read().lock() {
-    pac::FLASH.keyr().write(|w| w.set_fkeyr(0xCDEF_89AB));
+        pac::FLASH.keyr().write(|w| w.set_fkeyr(0x4567_0123));
+        pac::FLASH.keyr().write(|w| w.set_fkeyr(0xCDEF_89AB));
+    }
 }
 
 pub(crate) unsafe fn enable_blocking_write() {

embassy-stm32/src/flash/f4.rs

@@ -228,8 +228,10 @@ pub(crate) unsafe fn lock() {
 }
 
 pub(crate) unsafe fn unlock() {
-    pac::FLASH.keyr().write(|w| w.set_key(0x45670123));
+    if pac::FLASH.cr().read().lock() {
-    pac::FLASH.keyr().write(|w| w.set_key(0xCDEF89AB));
+        pac::FLASH.keyr().write(|w| w.set_key(0x45670123));
+        pac::FLASH.keyr().write(|w| w.set_key(0xCDEF89AB));
+    }
 }
 
 pub(crate) unsafe fn enable_write() {

embassy-stm32/src/flash/f7.rs

@@ -19,8 +19,10 @@ pub(crate) unsafe fn lock() {
 }
 
 pub(crate) unsafe fn unlock() {
-    pac::FLASH.keyr().write(|w| w.set_key(0x4567_0123));
+    if pac::FLASH.cr().read().lock() {
-    pac::FLASH.keyr().write(|w| w.set_key(0xCDEF_89AB));
+        pac::FLASH.keyr().write(|w| w.set_key(0x4567_0123));
+        pac::FLASH.keyr().write(|w| w.set_key(0xCDEF_89AB));
+    }
 }
 
 pub(crate) unsafe fn enable_blocking_write() {

embassy-stm32/src/flash/g0.rs

@@ -24,8 +24,10 @@ pub(crate) unsafe fn unlock() {
     while pac::FLASH.sr().read().bsy() {}
 
     // Unlock flash
-    pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
+    if pac::FLASH.cr().read().lock() {
-    pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
+        pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
+        pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
+    }
 }
 
 pub(crate) unsafe fn enable_blocking_write() {

embassy-stm32/src/flash/h7.rs

@@ -26,11 +26,15 @@ pub(crate) unsafe fn lock() {
 }
 
 pub(crate) unsafe fn unlock() {
-    pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0x4567_0123));
+    if pac::FLASH.bank(0).cr().read().lock() {
-    pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
+        pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0x4567_0123));
+        pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
+    }
     if is_dual_bank() {
-        pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0x4567_0123));
+        if pac::FLASH.bank(1).cr().read().lock() {
-        pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
+            pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0x4567_0123));
+            pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
+        }
     }
 }
 

embassy-stm32/src/flash/l.rs

@@ -28,17 +28,23 @@ pub(crate) unsafe fn lock() {
 pub(crate) unsafe fn unlock() {
     #[cfg(any(flash_wl, flash_wb, flash_l4))]
     {
-        pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
+        if pac::FLASH.cr().read().lock() {
-        pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
+            pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
+            pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
+        }
     }
 
     #[cfg(any(flash_l0, flash_l1))]
     {
-        pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x89ABCDEF));
+        if pac::FLASH.pecr().read().pelock() {
-        pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x02030405));
+            pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x89ABCDEF));
+            pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x02030405));
+        }
 
-        pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x8C9DAEBF));
+        if pac::FLASH.pecr().read().prglock() {
-        pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x13141516));
+            pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x8C9DAEBF));
+            pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x13141516));
+        }
     }
 }
 

embassy-stm32/src/gpio.rs

@@ -974,6 +974,18 @@ mod eh1 {
         type Error = Infallible;
     }
 
+    impl<'d, T: Pin> InputPin for OutputOpenDrain<'d, T> {
+        #[inline]
+        fn is_high(&self) -> Result<bool, Self::Error> {
+            Ok(self.is_high())
+        }
+
+        #[inline]
+        fn is_low(&self) -> Result<bool, Self::Error> {
+            Ok(self.is_low())
+        }
+    }
+
     impl<'d, T: Pin> OutputPin for OutputOpenDrain<'d, T> {
         #[inline]
         fn set_high(&mut self) -> Result<(), Self::Error> {

embassy-stm32/src/i2c/mod.rs

@@ -14,7 +14,7 @@ pub use timeout::*;
 
 use crate::peripherals;
 
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
     Bus,

embassy-stm32/src/opamp.rs

@@ -4,7 +4,15 @@ use embassy_hal_internal::{into_ref, PeripheralRef};
 
 use crate::Peripheral;
 
-#[cfg(opamp_f3)]
+#[derive(Clone, Copy)]
+pub enum OpAmpGain {
+    Mul1,
+    Mul2,
+    Mul4,
+    Mul8,
+    Mul16,
+}
+
 pub struct OpAmpOutput<'d, 'p, T: Instance, P: NonInvertingPin<T>> {
     _inner: &'d OpAmp<'d, T>,
     _input: &'p mut P,
@@ -35,14 +43,32 @@ impl<'d, T: Instance> OpAmp<'d, T> {
         Self { _inner: opamp }
     }
 
-    #[cfg(opamp_f3)]
+    pub fn buffer_for<'a, 'b, P>(&'a mut self, pin: &'b mut P, gain: OpAmpGain) -> OpAmpOutput<'a, 'b, T, P>
-    pub fn buffer_for<'a, 'b, P>(&'a mut self, pin: &'b mut P) -> OpAmpOutput<'a, 'b, T, P>
     where
         P: NonInvertingPin<T>,
     {
+        let (vm_sel, pga_gain) = match gain {
+            OpAmpGain::Mul1 => (0b11, 0b00),
+            OpAmpGain::Mul2 => (0b10, 0b00),
+            OpAmpGain::Mul4 => (0b10, 0b01),
+            OpAmpGain::Mul8 => (0b10, 0b10),
+            OpAmpGain::Mul16 => (0b10, 0b11),
+        };
+
         #[cfg(opamp_f3)]
         T::regs().opampcsr().modify(|w| {
             w.set_vp_sel(pin.channel());
+            w.set_vm_sel(vm_sel);
+            w.set_pga_gain(pga_gain);
+        });
+
+        #[cfg(opamp_g4)]
+        T::regs().opamp_csr().modify(|w| {
+            use crate::pac::opamp::vals::*;
+
+            w.set_vp_sel(OpampCsrVpSel::from_bits(pin.channel()));
+            w.set_vm_sel(OpampCsrVmSel::from_bits(vm_sel));
+            w.set_pga_gain(OpampCsrPgaGain::from_bits(pga_gain));
         });
 
         OpAmpOutput {

embassy-stm32/src/rcc/bd.rs

@@ -1,110 +1,161 @@
+use core::sync::atomic::{compiler_fence, Ordering};
+
+use crate::pac::common::{Reg, RW};
+pub use crate::pac::rcc::vals::Rtcsel as RtcClockSource;
+use crate::time::Hertz;
+
+#[cfg(any(stm32f0, stm32f1, stm32f3))]
+pub const LSI_FREQ: Hertz = Hertz(40_000);
+#[cfg(not(any(stm32f0, stm32f1, stm32f3)))]
+pub const LSI_FREQ: Hertz = Hertz(32_000);
+
+#[allow(dead_code)]
+#[derive(Clone, Copy)]
+pub enum LseMode {
+    Oscillator(LseDrive),
+    Bypass,
+}
+
+pub struct LseConfig {
+    pub frequency: Hertz,
+    pub mode: LseMode,
+}
+
 #[allow(dead_code)]
 #[derive(Default, Clone, Copy)]
 pub enum LseDrive {
-    #[cfg(any(rtc_v2f7, rtc_v2l4))]
     Low = 0,
     MediumLow = 0x01,
     #[default]
     MediumHigh = 0x02,
-    #[cfg(any(rtc_v2f7, rtc_v2l4))]
     High = 0x03,
 }
 
-#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
+// All families but these have the LSEDRV register
+#[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f400, rcc_f410, rcc_l1)))]
 impl From<LseDrive> for crate::pac::rcc::vals::Lsedrv {
     fn from(value: LseDrive) -> Self {
         use crate::pac::rcc::vals::Lsedrv;
 
         match value {
-            #[cfg(any(rtc_v2f7, rtc_v2l4))]
             LseDrive::Low => Lsedrv::LOW,
             LseDrive::MediumLow => Lsedrv::MEDIUMLOW,
             LseDrive::MediumHigh => Lsedrv::MEDIUMHIGH,
-            #[cfg(any(rtc_v2f7, rtc_v2l4))]
             LseDrive::High => Lsedrv::HIGH,
         }
     }
 }
 
-pub use crate::pac::rcc::vals::Rtcsel as RtcClockSource;
-
 #[cfg(not(any(rtc_v2l0, rtc_v2l1, stm32c0)))]
-#[allow(dead_code)]
 type Bdcr = crate::pac::rcc::regs::Bdcr;
-
 #[cfg(any(rtc_v2l0, rtc_v2l1))]
-#[allow(dead_code)]
 type Bdcr = crate::pac::rcc::regs::Csr;
+#[cfg(any(stm32c0))]
+type Bdcr = crate::pac::rcc::regs::Csr1;
 
-#[allow(dead_code)]
+#[cfg(any(stm32c0))]
-pub struct BackupDomain {}
+fn unlock() {}
 
-impl BackupDomain {
+#[cfg(not(any(stm32c0)))]
-    #[cfg(any(
+fn unlock() {
-        rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
+    #[cfg(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1))]
-        rtc_v3u5
+    let cr = crate::pac::PWR.cr();
-    ))]
+    #[cfg(not(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1, stm32u5, stm32h5, stm32wba)))]
-    #[allow(dead_code, unused_variables)]
+    let cr = crate::pac::PWR.cr1();
-    fn modify<R>(f: impl FnOnce(&mut Bdcr) -> R) -> R {
+    #[cfg(any(stm32u5, stm32h5, stm32wba))]
-        #[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1, rtc_v2l0))]
+    let cr = crate::pac::PWR.dbpcr();
-        let cr = crate::pac::PWR.cr();
-        #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
-        let cr = crate::pac::PWR.cr1();
 
-        // TODO: Missing from PAC for l0 and f0?
+    cr.modify(|w| w.set_dbp(true));
-        #[cfg(not(any(rtc_v2f0, rtc_v3u5)))]
+    while !cr.read().dbp() {}
-        {
+}
-            cr.modify(|w| w.set_dbp(true));
+
-            while !cr.read().dbp() {}
+fn bdcr() -> Reg<Bdcr, RW> {
+    #[cfg(any(rtc_v2l0, rtc_v2l1))]
+    return crate::pac::RCC.csr();
+    #[cfg(not(any(rtc_v2l0, rtc_v2l1, stm32c0)))]
+    return crate::pac::RCC.bdcr();
+    #[cfg(any(stm32c0))]
+    return crate::pac::RCC.csr1();
+}
+
+pub struct LsConfig {
+    pub rtc: RtcClockSource,
+    pub lsi: bool,
+    pub lse: Option<LseConfig>,
+}
+
+impl LsConfig {
+    pub const fn default_lse() -> Self {
+        Self {
+            rtc: RtcClockSource::LSE,
+            lse: Some(LseConfig {
+                frequency: Hertz(32_768),
+                mode: LseMode::Oscillator(LseDrive::MediumHigh),
+            }),
+            lsi: false,
         }
-
-        #[cfg(any(rtc_v2l0, rtc_v2l1))]
-        let cr = crate::pac::RCC.csr();
-
-        #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
-        let cr = crate::pac::RCC.bdcr();
-
-        cr.modify(|w| f(w))
     }
 
-    #[cfg(any(
+    pub const fn default_lsi() -> Self {
-        rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
+        Self {
-        rtc_v3u5
+            rtc: RtcClockSource::LSI,
-    ))]
+            lsi: true,
-    #[allow(dead_code)]
+            lse: None,
-    fn read() -> Bdcr {
+        }
-        #[cfg(any(rtc_v2l0, rtc_v2l1))]
-        let r = crate::pac::RCC.csr().read();
-
-        #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
-        let r = crate::pac::RCC.bdcr().read();
-
-        r
     }
 
-    #[cfg(any(
+    pub const fn off() -> Self {
-        rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
+        Self {
-        rtc_v3u5
+            rtc: RtcClockSource::NOCLOCK,
-    ))]
+            lsi: false,
-    #[allow(dead_code, unused_variables)]
+            lse: None,
-    pub fn configure_ls(clock_source: RtcClockSource, lsi: bool, lse: Option<LseDrive>) {
+        }
-        use atomic_polyfill::{compiler_fence, Ordering};
+    }
+}
 
-        match clock_source {
+impl Default for LsConfig {
-            RtcClockSource::LSI => assert!(lsi),
+    fn default() -> Self {
-            RtcClockSource::LSE => assert!(&lse.is_some()),
+        // on L5, just the fact that LSI is enabled makes things crash.
-            _ => {}
+        // TODO: investigate.
+
+        #[cfg(not(stm32l5))]
+        return Self::default_lsi();
+        #[cfg(stm32l5)]
+        return Self::off();
+    }
+}
+
+impl LsConfig {
+    pub(crate) fn init(&self) -> Option<Hertz> {
+        let rtc_clk = match self.rtc {
+            RtcClockSource::LSI => {
+                assert!(self.lsi);
+                Some(LSI_FREQ)
+            }
+            RtcClockSource::LSE => Some(self.lse.as_ref().unwrap().frequency),
+            RtcClockSource::NOCLOCK => None,
+            _ => todo!(),
         };
 
-        if lsi {
+        let (lse_en, lse_byp, lse_drv) = match &self.lse {
-            #[cfg(rtc_v3u5)]
+            Some(c) => match c.mode {
+                LseMode::Oscillator(lse_drv) => (true, false, Some(lse_drv)),
+                LseMode::Bypass => (true, true, None),
+            },
+            None => (false, false, None),
+        };
+        _ = lse_drv; // not all chips have it.
+
+        // Disable backup domain write protection
+        unlock();
+
+        if self.lsi {
+            #[cfg(any(stm32u5, stm32h5, stm32wba))]
             let csr = crate::pac::RCC.bdcr();
-
+            #[cfg(not(any(stm32u5, stm32h5, stm32wba, stm32c0)))]
-            #[cfg(not(rtc_v3u5))]
             let csr = crate::pac::RCC.csr();
-
+            #[cfg(any(stm32c0))]
-            // Disable backup domain write protection
+            let csr = crate::pac::RCC.csr2();
-            Self::modify(|_| {});
 
             #[cfg(not(any(rcc_wb, rcc_wba)))]
             csr.modify(|w| w.set_lsion(true));
@@ -124,58 +175,71 @@ impl BackupDomain {
         // first check if the configuration matches what we want.
 
         // check if it's already enabled and in the source we want.
-        let reg = Self::read();
+        let reg = bdcr().read();
         let mut ok = true;
-        ok &= reg.rtcsel() == clock_source;
+        ok &= reg.rtcsel() == self.rtc;
         #[cfg(not(rcc_wba))]
         {
-            ok &= reg.rtcen() == (clock_source != RtcClockSource::NOCLOCK);
+            ok &= reg.rtcen() == (self.rtc != RtcClockSource::NOCLOCK);
         }
-        ok &= reg.lseon() == lse.is_some();
+        ok &= reg.lseon() == lse_en;
-        #[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
+        ok &= reg.lsebyp() == lse_byp;
-        if let Some(lse_drive) = lse {
+        #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f400, rcc_f410, rcc_l1)))]
-            ok &= reg.lsedrv() == lse_drive.into();
+        if let Some(lse_drv) = lse_drv {
+            ok &= reg.lsedrv() == lse_drv.into();
         }
 
         // if configuration is OK, we're done.
         if ok {
-            // RTC code assumes backup domain is unlocked
+            trace!("BDCR ok: {:08x}", bdcr().read().0);
-            Self::modify(|w| {});
+            return rtc_clk;
-
-            trace!("BDCR ok: {:08x}", Self::read().0);
-            return;
         }
 
         // If not OK, reset backup domain and configure it.
-        #[cfg(not(any(rcc_l0, rcc_l1)))]
+        #[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32c0)))]
         {
-            Self::modify(|w| w.set_bdrst(true));
+            bdcr().modify(|w| w.set_bdrst(true));
-            Self::modify(|w| w.set_bdrst(false));
+            bdcr().modify(|w| w.set_bdrst(false));
+        }
+        #[cfg(any(stm32h5))]
+        {
+            bdcr().modify(|w| w.set_vswrst(true));
+            bdcr().modify(|w| w.set_vswrst(false));
+        }
+        #[cfg(any(stm32c0))]
+        {
+            bdcr().modify(|w| w.set_rtcrst(true));
+            bdcr().modify(|w| w.set_rtcrst(false));
         }
 
-        if let Some(lse_drive) = lse {
+        if lse_en {
-            Self::modify(|w| {
+            bdcr().modify(|w| {
-                #[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
+                #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f400, rcc_f410, rcc_l1)))]
-                w.set_lsedrv(lse_drive.into());
+                if let Some(lse_drv) = lse_drv {
+                    w.set_lsedrv(lse_drv.into());
+                }
+                w.set_lsebyp(lse_byp);
                 w.set_lseon(true);
             });
 
-            while !Self::read().lserdy() {}
+            while !bdcr().read().lserdy() {}
         }
 
-        if clock_source != RtcClockSource::NOCLOCK {
+        if self.rtc != RtcClockSource::NOCLOCK {
-            Self::modify(|w| {
+            bdcr().modify(|w| {
                 #[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
                 assert!(!w.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
 
                 #[cfg(not(rcc_wba))]
                 w.set_rtcen(true);
-                w.set_rtcsel(clock_source);
+                w.set_rtcsel(self.rtc);
             });
         }
 
-        trace!("BDCR configured: {:08x}", Self::read().0);
+        trace!("BDCR configured: {:08x}", bdcr().read().0);
 
         compiler_fence(Ordering::SeqCst);
+
+        rtc_clk
     }
 }

embassy-stm32/src/rcc/bus.rs

@@ -1,56 +0,0 @@
-use core::ops::Div;
-
-#[allow(unused_imports)]
-use crate::pac::rcc;
-pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
-use crate::time::Hertz;
-
-impl Div<AHBPrescaler> for Hertz {
-    type Output = Hertz;
-
-    fn div(self, rhs: AHBPrescaler) -> Self::Output {
-        let divisor = match rhs {
-            AHBPrescaler::DIV1 => 1,
-            AHBPrescaler::DIV2 => 2,
-            #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
-            AHBPrescaler::DIV3 => 3,
-            AHBPrescaler::DIV4 => 4,
-            #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
-            AHBPrescaler::DIV5 => 5,
-            #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
-            AHBPrescaler::DIV6 => 6,
-            AHBPrescaler::DIV8 => 8,
-            #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
-            AHBPrescaler::DIV10 => 10,
-            AHBPrescaler::DIV16 => 16,
-            #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
-            AHBPrescaler::DIV32 => 32,
-            #[cfg(not(rcc_wba))]
-            AHBPrescaler::DIV64 => 64,
-            #[cfg(not(rcc_wba))]
-            AHBPrescaler::DIV128 => 128,
-            #[cfg(not(rcc_wba))]
-            AHBPrescaler::DIV256 => 256,
-            #[cfg(not(rcc_wba))]
-            AHBPrescaler::DIV512 => 512,
-            _ => unreachable!(),
-        };
-        Hertz(self.0 / divisor)
-    }
-}
-
-impl Div<APBPrescaler> for Hertz {
-    type Output = Hertz;
-
-    fn div(self, rhs: APBPrescaler) -> Self::Output {
-        let divisor = match rhs {
-            APBPrescaler::DIV1 => 1,
-            APBPrescaler::DIV2 => 2,
-            APBPrescaler::DIV4 => 4,
-            APBPrescaler::DIV8 => 8,
-            APBPrescaler::DIV16 => 16,
-            _ => unreachable!(),
-        };
-        Hertz(self.0 / divisor)
-    }
-}

embassy-stm32/src/rcc/c0.rs

@@ -1,6 +1,6 @@
-pub use super::bus::{AHBPrescaler, APBPrescaler};
 use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::{Hsidiv, Ppre, Sw};
+use crate::pac::rcc::vals::Sw;
+pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Ppre as APBPrescaler};
 use crate::pac::{FLASH, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
@@ -8,9 +8,6 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(48_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
 /// System clock mux source
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
@@ -19,47 +16,22 @@ pub enum ClockSrc {
     LSI,
 }
 
-#[derive(Clone, Copy)]
-pub enum HSIPrescaler {
-    NotDivided,
-    Div2,
-    Div4,
-    Div8,
-    Div16,
-    Div32,
-    Div64,
-    Div128,
-}
-
-impl Into<Hsidiv> for HSIPrescaler {
-    fn into(self) -> Hsidiv {
-        match self {
-            HSIPrescaler::NotDivided => Hsidiv::DIV1,
-            HSIPrescaler::Div2 => Hsidiv::DIV2,
-            HSIPrescaler::Div4 => Hsidiv::DIV4,
-            HSIPrescaler::Div8 => Hsidiv::DIV8,
-            HSIPrescaler::Div16 => Hsidiv::DIV16,
-            HSIPrescaler::Div32 => Hsidiv::DIV32,
-            HSIPrescaler::Div64 => Hsidiv::DIV64,
-            HSIPrescaler::Div128 => Hsidiv::DIV128,
-        }
-    }
-}
-
 /// Clocks configutation
 pub struct Config {
     pub mux: ClockSrc,
     pub ahb_pre: AHBPrescaler,
     pub apb_pre: APBPrescaler,
+    pub ls: super::LsConfig,
 }
 
 impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            mux: ClockSrc::HSI(HSIPrescaler::NotDivided),
+            mux: ClockSrc::HSI(HSIPrescaler::DIV1),
             ahb_pre: AHBPrescaler::DIV1,
             apb_pre: APBPrescaler::DIV1,
+            ls: Default::default(),
         }
     }
 }
@@ -68,33 +40,34 @@ pub(crate) unsafe fn init(config: Config) {
     let (sys_clk, sw) = match config.mux {
         ClockSrc::HSI(div) => {
             // Enable HSI
-            let div: Hsidiv = div.into();
             RCC.cr().write(|w| {
                 w.set_hsidiv(div);
                 w.set_hsion(true)
             });
             while !RCC.cr().read().hsirdy() {}
 
-            (HSI_FREQ.0 >> div.to_bits(), Sw::HSI)
+            (HSI_FREQ / div, Sw::HSI)
         }
         ClockSrc::HSE(freq) => {
             // Enable HSE
             RCC.cr().write(|w| w.set_hseon(true));
             while !RCC.cr().read().hserdy() {}
 
-            (freq.0, Sw::HSE)
+            (freq, Sw::HSE)
         }
         ClockSrc::LSI => {
             // Enable LSI
             RCC.csr2().write(|w| w.set_lsion(true));
             while !RCC.csr2().read().lsirdy() {}
-            (LSI_FREQ.0, Sw::LSI)
+            (super::LSI_FREQ, Sw::LSI)
         }
     };
 
+    let rtc = config.ls.init();
+
     // Determine the flash latency implied by the target clock speed
     // RM0454 § 3.3.4:
-    let target_flash_latency = if sys_clk <= 24_000_000 {
+    let target_flash_latency = if sys_clk <= Hertz(24_000_000) {
         Latency::WS0
     } else {
         Latency::WS1
@@ -129,7 +102,7 @@ pub(crate) unsafe fn init(config: Config) {
     }
 
     // Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once
-    let (sw, hpre, ppre) = (sw.into(), config.ahb_pre.into(), config.apb_pre.into());
+    let (sw, hpre, ppre) = (sw.into(), config.ahb_pre, config.apb_pre);
     RCC.cfgr().modify(|w| {
         w.set_sw(sw);
         w.set_hpre(hpre);
@@ -150,34 +123,21 @@ pub(crate) unsafe fn init(config: Config) {
         FLASH.acr().modify(|w| w.set_latency(target_flash_latency));
     }
 
-    let ahb_div = match config.ahb_pre {
+    let ahb_freq = sys_clk / config.ahb_pre;
-        AHBPrescaler::DIV1 => 1,
-        AHBPrescaler::DIV2 => 2,
-        AHBPrescaler::DIV4 => 4,
-        AHBPrescaler::DIV8 => 8,
-        AHBPrescaler::DIV16 => 16,
-        AHBPrescaler::DIV64 => 64,
-        AHBPrescaler::DIV128 => 128,
-        AHBPrescaler::DIV256 => 256,
-        AHBPrescaler::DIV512 => 512,
-        _ => unreachable!(),
-    };
-    let ahb_freq = sys_clk / ahb_div;
 
     let (apb_freq, apb_tim_freq) = match config.apb_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: Ppre = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre.to_bits() - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
         }
     };
 
     set_freqs(Clocks {
-        sys: Hertz(sys_clk),
+        sys: sys_clk,
-        ahb1: Hertz(ahb_freq),
+        ahb1: ahb_freq,
-        apb1: Hertz(apb_freq),
+        apb1: apb_freq,
-        apb1_tim: Hertz(apb_tim_freq),
+        apb1_tim: apb_tim_freq,
+        rtc,
     });
 }

embassy-stm32/src/rcc/f0.rs

@@ -8,9 +8,6 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(8_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(40_000);
-
 /// Configuration of the clocks
 ///
 /// hse takes precedence over hsi48 if both are enabled
@@ -27,6 +24,8 @@ pub struct Config {
     pub sys_ck: Option<Hertz>,
     pub hclk: Option<Hertz>,
     pub pclk: Option<Hertz>,
+
+    pub ls: super::LsConfig,
 }
 
 pub(crate) unsafe fn init(config: Config) {
@@ -159,6 +158,8 @@ pub(crate) unsafe fn init(config: Config) {
         })
     }
 
+    let rtc = config.ls.init();
+
     set_freqs(Clocks {
         sys: Hertz(real_sysclk),
         apb1: Hertz(pclk),
@@ -166,5 +167,6 @@ pub(crate) unsafe fn init(config: Config) {
         apb1_tim: Hertz(pclk * timer_mul),
         apb2_tim: Hertz(pclk * timer_mul),
         ahb1: Hertz(hclk),
+        rtc,
     });
 }

embassy-stm32/src/rcc/f1.rs

@@ -9,9 +9,6 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(8_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(40_000);
-
 /// Configuration of the clocks
 ///
 #[non_exhaustive]
@@ -25,6 +22,8 @@ pub struct Config {
     pub pclk2: Option<Hertz>,
     pub adcclk: Option<Hertz>,
     pub pllxtpre: bool,
+
+    pub ls: super::LsConfig,
 }
 
 pub(crate) unsafe fn init(config: Config) {
@@ -177,6 +176,8 @@ pub(crate) unsafe fn init(config: Config) {
         });
     });
 
+    let rtc = config.ls.init();
+
     set_freqs(Clocks {
         sys: Hertz(real_sysclk),
         apb1: Hertz(pclk1),
@@ -185,5 +186,6 @@ pub(crate) unsafe fn init(config: Config) {
         apb2_tim: Hertz(pclk2 * timer_mul2),
         ahb1: Hertz(hclk),
         adc: Some(Hertz(adcclk)),
+        rtc,
     });
 }

embassy-stm32/src/rcc/f2.rs

@@ -1,21 +1,16 @@
-use core::convert::TryFrom;
-use core::ops::{Div, Mul};
-
-pub use super::bus::{AHBPrescaler, APBPrescaler};
 use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::{Pllp, Pllsrc, Sw};
+use crate::pac::rcc::vals::Sw;
+pub use crate::pac::rcc::vals::{
+    Hpre as AHBPrescaler, Pllm as PLLPreDiv, Plln as PLLMul, Pllp as PLLPDiv, Pllq as PLLQDiv, Pllsrc as PLLSrc,
+    Ppre as APBPrescaler,
+};
 use crate::pac::{FLASH, RCC};
-use crate::rcc::bd::BackupDomain;
 use crate::rcc::{set_freqs, Clocks};
-use crate::rtc::RtcClockSource;
 use crate::time::Hertz;
 
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
 #[derive(Clone, Copy)]
 pub struct HSEConfig {
     pub frequency: Hertz,
@@ -43,17 +38,17 @@ pub enum HSESrc {
 pub struct PLLConfig {
     pub pre_div: PLLPreDiv,
     pub mul: PLLMul,
-    pub main_div: PLLMainDiv,
+    pub p_div: PLLPDiv,
-    pub pll48_div: PLL48Div,
+    pub q_div: PLLQDiv,
 }
 
 impl Default for PLLConfig {
     fn default() -> Self {
         PLLConfig {
-            pre_div: PLLPreDiv(16),
+            pre_div: PLLPreDiv::DIV16,
-            mul: PLLMul(192),
+            mul: PLLMul::MUL192,
-            main_div: PLLMainDiv::Div2,
+            p_div: PLLPDiv::DIV2,
-            pll48_div: PLL48Div(4),
+            q_div: PLLQDiv::DIV4,
         }
     }
 }
@@ -61,9 +56,9 @@ impl Default for PLLConfig {
 impl PLLConfig {
     pub fn clocks(&self, src_freq: Hertz) -> PLLClocks {
         let in_freq = src_freq / self.pre_div;
-        let vco_freq = Hertz((src_freq.0 as u64 * self.mul.0 as u64 / self.pre_div.0 as u64) as u32);
+        let vco_freq = src_freq / self.pre_div * self.mul;
-        let main_freq = vco_freq / self.main_div;
+        let main_freq = vco_freq / self.p_div;
-        let pll48_freq = vco_freq / self.pll48_div;
+        let pll48_freq = vco_freq / self.q_div;
         PLLClocks {
             in_freq,
             vco_freq,
@@ -72,129 +67,6 @@ impl PLLConfig {
         }
     }
 }
-
-/// Clock source for both main PLL and PLLI2S
-#[derive(Clone, Copy, PartialEq)]
-pub enum PLLSrc {
-    HSE,
-    HSI,
-}
-
-impl Into<Pllsrc> for PLLSrc {
-    fn into(self) -> Pllsrc {
-        match self {
-            PLLSrc::HSE => Pllsrc::HSE,
-            PLLSrc::HSI => Pllsrc::HSI,
-        }
-    }
-}
-
-/// Division factor for both main PLL and PLLI2S
-#[derive(Clone, Copy, PartialEq)]
-#[repr(transparent)]
-pub struct PLLPreDiv(u8);
-
-impl TryFrom<u8> for PLLPreDiv {
-    type Error = &'static str;
-
-    fn try_from(value: u8) -> Result<Self, Self::Error> {
-        match value {
-            2..=63 => Ok(PLLPreDiv(value)),
-            _ => Err("PLLPreDiv must be within range 2..=63"),
-        }
-    }
-}
-
-impl Div<PLLPreDiv> for Hertz {
-    type Output = Hertz;
-
-    fn div(self, rhs: PLLPreDiv) -> Self::Output {
-        Hertz(self.0 / u32::from(rhs.0))
-    }
-}
-
-/// Multiplication factor for main PLL
-#[derive(Clone, Copy, PartialEq)]
-#[repr(transparent)]
-pub struct PLLMul(u16);
-
-impl Mul<PLLMul> for Hertz {
-    type Output = Hertz;
-
-    fn mul(self, rhs: PLLMul) -> Self::Output {
-        Hertz(self.0 * u32::from(rhs.0))
-    }
-}
-
-impl TryFrom<u16> for PLLMul {
-    type Error = &'static str;
-
-    fn try_from(value: u16) -> Result<Self, Self::Error> {
-        match value {
-            192..=432 => Ok(PLLMul(value)),
-            _ => Err("PLLMul must be within range 192..=432"),
-        }
-    }
-}
-
-/// PLL division factor for the main system clock
-#[derive(Clone, Copy, PartialEq)]
-pub enum PLLMainDiv {
-    Div2,
-    Div4,
-    Div6,
-    Div8,
-}
-
-impl Into<Pllp> for PLLMainDiv {
-    fn into(self) -> Pllp {
-        match self {
-            PLLMainDiv::Div2 => Pllp::DIV2,
-            PLLMainDiv::Div4 => Pllp::DIV4,
-            PLLMainDiv::Div6 => Pllp::DIV6,
-            PLLMainDiv::Div8 => Pllp::DIV8,
-        }
-    }
-}
-
-impl Div<PLLMainDiv> for Hertz {
-    type Output = Hertz;
-
-    fn div(self, rhs: PLLMainDiv) -> Self::Output {
-        let divisor = match rhs {
-            PLLMainDiv::Div2 => 2,
-            PLLMainDiv::Div4 => 4,
-            PLLMainDiv::Div6 => 6,
-            PLLMainDiv::Div8 => 8,
-        };
-        Hertz(self.0 / divisor)
-    }
-}
-
-/// PLL division factor for USB OTG FS / SDIO / RNG
-#[derive(Clone, Copy, PartialEq)]
-#[repr(transparent)]
-pub struct PLL48Div(u8);
-
-impl Div<PLL48Div> for Hertz {
-    type Output = Hertz;
-
-    fn div(self, rhs: PLL48Div) -> Self::Output {
-        Hertz(self.0 / u32::from(rhs.0))
-    }
-}
-
-impl TryFrom<u8> for PLL48Div {
-    type Error = &'static str;
-
-    fn try_from(value: u8) -> Result<Self, Self::Error> {
-        match value {
-            2..=15 => Ok(PLL48Div(value)),
-            _ => Err("PLL48Div must be within range 2..=15"),
-        }
-    }
-}
-
 #[derive(Clone, Copy, PartialEq)]
 pub struct PLLClocks {
     pub in_freq: Hertz,
@@ -303,13 +175,11 @@ pub struct Config {
     pub pll_mux: PLLSrc,
     pub pll: PLLConfig,
     pub mux: ClockSrc,
-    pub rtc: Option<RtcClockSource>,
-    pub lsi: bool,
-    pub lse: Option<Hertz>,
     pub voltage: VoltageScale,
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
+    pub ls: super::LsConfig,
 }
 
 impl Default for Config {
@@ -322,12 +192,10 @@ impl Default for Config {
             pll: PLLConfig::default(),
             voltage: VoltageScale::Range3,
             mux: ClockSrc::HSI,
-            rtc: None,
-            lsi: false,
-            lse: None,
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
+            ls: Default::default(),
         }
     }
 }
@@ -367,11 +235,11 @@ pub(crate) unsafe fn init(config: Config) {
     assert!(pll_clocks.pll48_freq <= Hertz(48_000_000));
 
     RCC.pllcfgr().write(|w| {
-        w.set_pllsrc(config.pll_mux.into());
+        w.set_pllsrc(config.pll_mux);
-        w.set_pllm(config.pll.pre_div.0);
+        w.set_pllm(config.pll.pre_div);
-        w.set_plln(config.pll.mul.0);
+        w.set_plln(config.pll.mul);
-        w.set_pllp(config.pll.main_div.into());
+        w.set_pllp(config.pll.p_div);
-        w.set_pllq(config.pll.pll48_div.0);
+        w.set_pllq(config.pll.q_div);
     });
 
     let (sys_clk, sw) = match config.mux {
@@ -424,9 +292,9 @@ pub(crate) unsafe fn init(config: Config) {
 
     RCC.cfgr().modify(|w| {
         w.set_sw(sw.into());
-        w.set_hpre(config.ahb_pre.into());
+        w.set_hpre(config.ahb_pre);
-        w.set_ppre1(config.apb1_pre.into());
+        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre.into());
+        w.set_ppre2(config.apb2_pre);
     });
     while RCC.cfgr().read().sws().to_bits() != sw.to_bits() {}
 
@@ -435,11 +303,7 @@ pub(crate) unsafe fn init(config: Config) {
         RCC.cr().modify(|w| w.set_hsion(false));
     }
 
-    BackupDomain::configure_ls(
+    let rtc = config.ls.init();
-        config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
-        config.lsi,
-        config.lse.map(|_| Default::default()),
-    );
 
     set_freqs(Clocks {
         sys: sys_clk,
@@ -451,5 +315,6 @@ pub(crate) unsafe fn init(config: Config) {
         apb2: apb2_freq,
         apb2_tim: apb2_tim_freq,
         pll48: Some(pll_clocks.pll48_freq),
+        rtc,
     });
 }

embassy-stm32/src/rcc/f3.rs

@@ -1,7 +1,8 @@
 #[cfg(rcc_f3)]
 use crate::pac::adccommon::vals::Ckmode;
 use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::{Adcpres, Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
+pub use crate::pac::rcc::vals::Adcpres;
+use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
 use crate::pac::{FLASH, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
@@ -9,28 +10,6 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(8_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(40_000);
-
-impl From<AdcClockSource> for Adcpres {
-    fn from(value: AdcClockSource) -> Self {
-        match value {
-            AdcClockSource::PllDiv1 => Adcpres::DIV1,
-            AdcClockSource::PllDiv2 => Adcpres::DIV2,
-            AdcClockSource::PllDiv4 => Adcpres::DIV4,
-            AdcClockSource::PllDiv6 => Adcpres::DIV6,
-            AdcClockSource::PllDiv8 => Adcpres::DIV8,
-            AdcClockSource::PllDiv12 => Adcpres::DIV12,
-            AdcClockSource::PllDiv16 => Adcpres::DIV16,
-            AdcClockSource::PllDiv32 => Adcpres::DIV32,
-            AdcClockSource::PllDiv64 => Adcpres::DIV64,
-            AdcClockSource::PllDiv128 => Adcpres::DIV128,
-            AdcClockSource::PllDiv256 => Adcpres::DIV256,
-            _ => unreachable!(),
-        }
-    }
-}
-
 #[cfg(rcc_f3)]
 impl From<AdcClockSource> for Ckmode {
     fn from(value: AdcClockSource) -> Self {
@@ -45,32 +24,13 @@ impl From<AdcClockSource> for Ckmode {
 
 #[derive(Clone, Copy)]
 pub enum AdcClockSource {
-    PllDiv1 = 1,
+    Pll(Adcpres),
-    PllDiv2 = 2,
-    PllDiv4 = 4,
-    PllDiv6 = 6,
-    PllDiv8 = 8,
-    PllDiv12 = 12,
-    PllDiv16 = 16,
-    PllDiv32 = 32,
-    PllDiv64 = 64,
-    PllDiv128 = 128,
-    PllDiv256 = 256,
     BusDiv1,
     BusDiv2,
     BusDiv4,
 }
 
 impl AdcClockSource {
-    pub fn is_bus(&self) -> bool {
-        match self {
-            Self::BusDiv1 => true,
-            Self::BusDiv2 => true,
-            Self::BusDiv4 => true,
-            _ => false,
-        }
-    }
-
     pub fn bus_div(&self) -> u32 {
         match self {
             Self::BusDiv1 => 1,
@@ -124,6 +84,7 @@ pub struct Config {
     pub adc34: Option<AdcClockSource>,
     #[cfg(stm32f334)]
     pub hrtim: HrtimClockSource,
+    pub ls: super::LsConfig,
 }
 
 // Information required to setup the PLL clock
@@ -137,67 +98,67 @@ struct PllConfig {
 /// Initialize and Set the clock frequencies
 pub(crate) unsafe fn init(config: Config) {
     // Calculate the real System clock, and PLL configuration if applicable
-    let (Hertz(sysclk), pll_config) = get_sysclk(&config);
+    let (sysclk, pll_config) = get_sysclk(&config);
-    assert!(sysclk <= 72_000_000);
+    assert!(sysclk.0 <= 72_000_000);
 
     // Calculate real AHB clock
-    let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
+    let hclk = config.hclk.map(|h| h).unwrap_or(sysclk);
-    let (hpre_bits, hpre_div) = match sysclk / hclk {
+    let hpre = match sysclk.0 / hclk.0 {
         0 => unreachable!(),
-        1 => (Hpre::DIV1, 1),
+        1 => Hpre::DIV1,
-        2 => (Hpre::DIV2, 2),
+        2 => Hpre::DIV2,
-        3..=5 => (Hpre::DIV4, 4),
+        3..=5 => Hpre::DIV4,
-        6..=11 => (Hpre::DIV8, 8),
+        6..=11 => Hpre::DIV8,
-        12..=39 => (Hpre::DIV16, 16),
+        12..=39 => Hpre::DIV16,
-        40..=95 => (Hpre::DIV64, 64),
+        40..=95 => Hpre::DIV64,
-        96..=191 => (Hpre::DIV128, 128),
+        96..=191 => Hpre::DIV128,
-        192..=383 => (Hpre::DIV256, 256),
+        192..=383 => Hpre::DIV256,
-        _ => (Hpre::DIV512, 512),
+        _ => Hpre::DIV512,
     };
-    let hclk = sysclk / hpre_div;
+    let hclk = sysclk / hpre;
-    assert!(hclk <= 72_000_000);
+    assert!(hclk <= Hertz(72_000_000));
 
     // Calculate real APB1 clock
-    let pclk1 = config.pclk1.map(|p| p.0).unwrap_or(hclk);
+    let pclk1 = config.pclk1.unwrap_or(hclk);
-    let (ppre1_bits, ppre1) = match hclk / pclk1 {
+    let ppre1 = match hclk / pclk1 {
         0 => unreachable!(),
-        1 => (Ppre::DIV1, 1),
+        1 => Ppre::DIV1,
-        2 => (Ppre::DIV2, 2),
+        2 => Ppre::DIV2,
-        3..=5 => (Ppre::DIV4, 4),
+        3..=5 => Ppre::DIV4,
-        6..=11 => (Ppre::DIV8, 8),
+        6..=11 => Ppre::DIV8,
-        _ => (Ppre::DIV16, 16),
+        _ => Ppre::DIV16,
     };
-    let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
+    let timer_mul1 = if ppre1 == Ppre::DIV1 { 1u32 } else { 2 };
     let pclk1 = hclk / ppre1;
-    assert!(pclk1 <= 36_000_000);
+    assert!(pclk1 <= Hertz(36_000_000));
 
     // Calculate real APB2 clock
-    let pclk2 = config.pclk2.map(|p| p.0).unwrap_or(hclk);
+    let pclk2 = config.pclk2.unwrap_or(hclk);
-    let (ppre2_bits, ppre2) = match hclk / pclk2 {
+    let ppre2 = match hclk / pclk2 {
         0 => unreachable!(),
-        1 => (Ppre::DIV1, 1),
+        1 => Ppre::DIV1,
-        2 => (Ppre::DIV2, 2),
+        2 => Ppre::DIV2,
-        3..=5 => (Ppre::DIV4, 4),
+        3..=5 => Ppre::DIV4,
-        6..=11 => (Ppre::DIV8, 8),
+        6..=11 => Ppre::DIV8,
-        _ => (Ppre::DIV16, 16),
+        _ => Ppre::DIV16,
     };
-    let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
+    let timer_mul2 = if ppre2 == Ppre::DIV1 { 1u32 } else { 2 };
     let pclk2 = hclk / ppre2;
-    assert!(pclk2 <= 72_000_000);
+    assert!(pclk2 <= Hertz(72_000_000));
 
     // Set latency based on HCLK frquency
     // RM0316: "The prefetch buffer must be kept on when using a prescaler
     // different from 1 on the AHB clock.", "Half-cycle access cannot be
     // used when there is a prescaler different from 1 on the AHB clock"
     FLASH.acr().modify(|w| {
-        w.set_latency(if hclk <= 24_000_000 {
+        w.set_latency(if hclk <= Hertz(24_000_000) {
             Latency::WS0
-        } else if hclk <= 48_000_000 {
+        } else if hclk <= Hertz(48_000_000) {
             Latency::WS1
         } else {
             Latency::WS2
         });
-        if hpre_div != 1 {
+        if hpre != Hpre::DIV1 {
             w.set_hlfcya(false);
             w.set_prftbe(true);
         }
@@ -240,9 +201,9 @@ pub(crate) unsafe fn init(config: Config) {
     // Set prescalers
     // CFGR has been written before (PLL, PLL48) don't overwrite these settings
     RCC.cfgr().modify(|w| {
-        w.set_ppre2(ppre2_bits);
+        w.set_ppre2(ppre2);
-        w.set_ppre1(ppre1_bits);
+        w.set_ppre1(ppre1);
-        w.set_hpre(hpre_bits);
+        w.set_hpre(hpre);
     });
 
     // Wait for the new prescalers to kick in
@@ -260,45 +221,43 @@ pub(crate) unsafe fn init(config: Config) {
     });
 
     #[cfg(rcc_f3)]
-    let adc = config.adc.map(|adc| {
+    let adc = config.adc.map(|adc| match adc {
-        if !adc.is_bus() {
+        AdcClockSource::Pll(adcpres) => {
             RCC.cfgr2().modify(|w| {
                 // Make sure that we're using the PLL
                 pll_config.unwrap();
-                w.set_adc12pres(adc.into());
+                w.set_adc12pres(adcpres);
 
-                Hertz(sysclk / adc as u32)
+                sysclk / adcpres
-            })
-        } else {
-            crate::pac::ADC_COMMON.ccr().modify(|w| {
-                assert!(!(adc.bus_div() == 1 && hpre_bits != Hpre::DIV1));
-
-                w.set_ckmode(adc.into());
-
-                Hertz(sysclk / adc.bus_div() as u32)
             })
         }
+        _ => crate::pac::ADC_COMMON.ccr().modify(|w| {
+            assert!(!(adc.bus_div() == 1 && hpre != Hpre::DIV1));
+
+            w.set_ckmode(adc.into());
+
+            sysclk / adc.bus_div()
+        }),
     });
 
     #[cfg(all(rcc_f3, adc3_common))]
-    let adc34 = config.adc.map(|adc| {
+    let adc34 = config.adc34.map(|adc| match adc {
-        if !adc.is_bus() {
+        AdcClockSource::Pll(adcpres) => {
             RCC.cfgr2().modify(|w| {
                 // Make sure that we're using the PLL
                 pll_config.unwrap();
-                w.set_adc12pres(adc.into());
+                w.set_adc34pres(adcpres);
 
-                Hertz(sysclk / adc as u32)
+                sysclk / adcpres
-            })
-        } else {
-            crate::pac::ADC3_COMMON.ccr().modify(|w| {
-                assert!(!(adc.bus_div() == 1 && hpre_bits != Hpre::DIV1));
-
-                w.set_ckmode(adc.into());
-
-                Hertz(sysclk / adc.bus_div() as u32)
             })
         }
+        _ => crate::pac::ADC_COMMON.ccr().modify(|w| {
+            assert!(!(adc.bus_div() == 1 && hpre != Hpre::DIV1));
+
+            w.set_ckmode(adc.into());
+
+            sysclk / adc.bus_div()
+        }),
     });
 
     #[cfg(stm32f334)]
@@ -310,21 +269,23 @@ pub(crate) unsafe fn init(config: Config) {
 
             // Make sure that we're using the PLL
             pll_config.unwrap();
-            assert!((pclk2 == sysclk) || (pclk2 * 2 == sysclk));
+            assert!((pclk2 == sysclk) || (pclk2 * 2u32 == sysclk));
 
             RCC.cfgr3().modify(|w| w.set_hrtim1sw(Timsw::PLL));
 
-            Some(Hertz(sysclk * 2))
+            Some(sysclk * 2u32)
         }
     };
 
+    let rtc = config.ls.init();
+
     set_freqs(Clocks {
-        sys: Hertz(sysclk),
+        sys: sysclk,
-        apb1: Hertz(pclk1),
+        apb1: pclk1,
-        apb2: Hertz(pclk2),
+        apb2: pclk2,
-        apb1_tim: Hertz(pclk1 * timer_mul1),
+        apb1_tim: pclk1 * timer_mul1,
-        apb2_tim: Hertz(pclk2 * timer_mul2),
+        apb2_tim: pclk2 * timer_mul2,
-        ahb1: Hertz(hclk),
+        ahb1: hclk,
         #[cfg(rcc_f3)]
         adc: adc,
         #[cfg(all(rcc_f3, adc3_common))]
@@ -333,6 +294,7 @@ pub(crate) unsafe fn init(config: Config) {
         adc34: None,
         #[cfg(stm32f334)]
         hrtim: hrtim,
+        rtc,
     });
 }
 
@@ -421,16 +383,16 @@ fn calc_pll(config: &Config, Hertz(sysclk): Hertz) -> (Hertz, PllConfig) {
 
 #[inline]
 #[allow(unused_variables)]
-fn get_usb_pre(config: &Config, sysclk: u32, pclk1: u32, pll_config: &Option<PllConfig>) -> Usbpre {
+fn get_usb_pre(config: &Config, sysclk: Hertz, pclk1: Hertz, pll_config: &Option<PllConfig>) -> Usbpre {
     cfg_if::cfg_if! {
         // Some chips do not have USB
         if #[cfg(any(stm32f301, stm32f318, stm32f334))] {
             panic!("USB clock not supported by the chip");
         } else {
-            let usb_ok = config.hse.is_some() && pll_config.is_some() && (pclk1 >= 10_000_000);
+            let usb_ok = config.hse.is_some() && pll_config.is_some() && (pclk1 >= Hertz(10_000_000));
             match (usb_ok, sysclk) {
-                (true, 72_000_000) => Usbpre::DIV1_5,
+                (true, Hertz(72_000_000)) => Usbpre::DIV1_5,
-                (true, 48_000_000) => Usbpre::DIV1,
+                (true, Hertz(48_000_000)) => Usbpre::DIV1,
                 _ => panic!(
                     "USB clock is only valid if the PLL output frequency is either 48MHz or 72MHz"
                 ),

embassy-stm32/src/rcc/f4.rs

@@ -1,23 +1,11 @@
-use core::marker::PhantomData;
+use crate::pac::rcc::vals::{Hpre, Pllm, Plln, Pllq, Pllr, Ppre, Sw};
-
-use embassy_hal_internal::into_ref;
-use stm32_metapac::rcc::vals::{Mco1, Mco2, Mcopre};
-
-use crate::gpio::sealed::AFType;
-use crate::gpio::Speed;
-use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
 use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::bd::{BackupDomain, RtcClockSource};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
-use crate::{peripherals, Peripheral};
 
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
 /// Clocks configuration
 #[non_exhaustive]
 #[derive(Default)]
@@ -36,9 +24,7 @@ pub struct Config {
     pub pllsai: Option<Hertz>,
 
     pub pll48: bool,
-    pub rtc: Option<RtcClockSource>,
+    pub ls: super::LsConfig,
-    pub lsi: bool,
-    pub lse: Option<Hertz>,
 }
 
 #[cfg(stm32f410)]
@@ -178,12 +164,12 @@ fn setup_pll(
     let real_pll48clk = vco_in * plln / pllq;
 
     RCC.pllcfgr().modify(|w| {
-        w.set_pllm(pllm as u8);
+        w.set_pllm(Pllm::from_bits(pllm as u8));
-        w.set_plln(plln as u16);
+        w.set_plln(Plln::from_bits(plln as u16));
         w.set_pllp(Pllp::from_bits(pllp as u8));
-        w.set_pllq(pllq as u8);
+        w.set_pllq(Pllq::from_bits(pllq as u8));
         w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
-        w.set_pllr(0);
+        w.set_pllr(Pllr::from_bits(0));
     });
 
     let real_pllsysclk = vco_in * plln / sysclk_div;
@@ -197,164 +183,6 @@ fn setup_pll(
     }
 }
 
-pub enum McoClock {
-    DIV1,
-    DIV2,
-    DIV3,
-    DIV4,
-    DIV5,
-}
-
-impl McoClock {
-    fn into_raw(&self) -> Mcopre {
-        match self {
-            McoClock::DIV1 => Mcopre::DIV1,
-            McoClock::DIV2 => Mcopre::DIV2,
-            McoClock::DIV3 => Mcopre::DIV3,
-            McoClock::DIV4 => Mcopre::DIV4,
-            McoClock::DIV5 => Mcopre::DIV5,
-        }
-    }
-}
-
-#[derive(Copy, Clone)]
-pub enum Mco1Source {
-    Hsi,
-    Lse,
-    Hse,
-    Pll,
-}
-
-impl Default for Mco1Source {
-    fn default() -> Self {
-        Self::Hsi
-    }
-}
-
-pub trait McoSource {
-    type Raw;
-
-    fn into_raw(&self) -> Self::Raw;
-}
-
-impl McoSource for Mco1Source {
-    type Raw = Mco1;
-    fn into_raw(&self) -> Self::Raw {
-        match self {
-            Mco1Source::Hsi => Mco1::HSI,
-            Mco1Source::Lse => Mco1::LSE,
-            Mco1Source::Hse => Mco1::HSE,
-            Mco1Source::Pll => Mco1::PLL,
-        }
-    }
-}
-
-#[derive(Copy, Clone)]
-pub enum Mco2Source {
-    SysClk,
-    Plli2s,
-    Hse,
-    Pll,
-}
-
-impl Default for Mco2Source {
-    fn default() -> Self {
-        Self::SysClk
-    }
-}
-
-impl McoSource for Mco2Source {
-    type Raw = Mco2;
-    fn into_raw(&self) -> Self::Raw {
-        match self {
-            Mco2Source::SysClk => Mco2::SYSCLK,
-            Mco2Source::Plli2s => Mco2::PLLI2S,
-            Mco2Source::Hse => Mco2::HSE,
-            Mco2Source::Pll => Mco2::PLL,
-        }
-    }
-}
-
-pub(crate) mod sealed {
-    use stm32_metapac::rcc::vals::Mcopre;
-    pub trait McoInstance {
-        type Source;
-        unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre);
-    }
-}
-
-pub trait McoInstance: sealed::McoInstance + 'static {}
-
-pin_trait!(McoPin, McoInstance);
-
-impl sealed::McoInstance for peripherals::MCO1 {
-    type Source = Mco1;
-    unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre) {
-        RCC.cfgr().modify(|w| {
-            w.set_mco1(source);
-            w.set_mco1pre(prescaler);
-        });
-        match source {
-            Mco1::PLL => {
-                RCC.cr().modify(|w| w.set_pllon(true));
-                while !RCC.cr().read().pllrdy() {}
-            }
-            Mco1::HSI => {
-                RCC.cr().modify(|w| w.set_hsion(true));
-                while !RCC.cr().read().hsirdy() {}
-            }
-            _ => {}
-        }
-    }
-}
-impl McoInstance for peripherals::MCO1 {}
-
-impl sealed::McoInstance for peripherals::MCO2 {
-    type Source = Mco2;
-    unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre) {
-        RCC.cfgr().modify(|w| {
-            w.set_mco2(source);
-            w.set_mco2pre(prescaler);
-        });
-        match source {
-            Mco2::PLL => {
-                RCC.cr().modify(|w| w.set_pllon(true));
-                while !RCC.cr().read().pllrdy() {}
-            }
-            #[cfg(not(stm32f410))]
-            Mco2::PLLI2S => {
-                RCC.cr().modify(|w| w.set_plli2son(true));
-                while !RCC.cr().read().plli2srdy() {}
-            }
-            _ => {}
-        }
-    }
-}
-impl McoInstance for peripherals::MCO2 {}
-
-pub struct Mco<'d, T: McoInstance> {
-    phantom: PhantomData<&'d mut T>,
-}
-
-impl<'d, T: McoInstance> Mco<'d, T> {
-    pub fn new(
-        _peri: impl Peripheral<P = T> + 'd,
-        pin: impl Peripheral<P = impl McoPin<T>> + 'd,
-        source: impl McoSource<Raw = T::Source>,
-        prescaler: McoClock,
-    ) -> Self {
-        into_ref!(pin);
-
-        critical_section::with(|_| unsafe {
-            T::apply_clock_settings(source.into_raw(), prescaler.into_raw());
-            pin.set_as_af(pin.af_num(), AFType::OutputPushPull);
-            pin.set_speed(Speed::VeryHigh);
-        });
-
-        Self { phantom: PhantomData }
-    }
-}
-
 fn flash_setup(sysclk: u32) {
     use crate::pac::flash::vals::Latency;
 
@@ -508,17 +336,7 @@ pub(crate) unsafe fn init(config: Config) {
         })
     });
 
-    BackupDomain::configure_ls(
+    let rtc = config.ls.init();
-        config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
-        config.lsi,
-        config.lse.map(|_| Default::default()),
-    );
-
-    let rtc = match config.rtc {
-        Some(RtcClockSource::LSI) => Some(LSI_FREQ),
-        Some(RtcClockSource::LSE) => Some(config.lse.unwrap()),
-        _ => None,
-    };
 
     set_freqs(Clocks {
         sys: Hertz(sysclk),
@@ -540,8 +358,7 @@ pub(crate) unsafe fn init(config: Config) {
         #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
         pllsai: plls.pllsaiclk.map(Hertz),
 
-        rtc: rtc,
+        rtc,
-        rtc_hse: None,
     });
 }
 

embassy-stm32/src/rcc/f7.rs

@@ -1,16 +1,12 @@
 use crate::pac::pwr::vals::Vos;
-use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
+use crate::pac::rcc::vals::{Hpre, Pllm, Plln, Pllp, Pllq, Pllsrc, Ppre, Sw};
 use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::bd::{BackupDomain, RtcClockSource};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
 
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
 /// Clocks configuration
 #[non_exhaustive]
 #[derive(Default)]
@@ -23,14 +19,10 @@ pub struct Config {
     pub pclk2: Option<Hertz>,
 
     pub pll48: bool,
-    pub rtc: Option<RtcClockSource>,
+    pub ls: super::LsConfig,
-    pub lsi: bool,
-    pub lse: Option<Hertz>,
 }
 
 fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
-    use crate::pac::rcc::vals::{Pllp, Pllsrc};
-
     let sysclk = pllsysclk.unwrap_or(pllsrcclk);
     if pllsysclk.is_none() && !pll48clk {
         RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)));
@@ -84,10 +76,10 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bo
     let real_pll48clk = vco_in * plln / pllq;
 
     RCC.pllcfgr().modify(|w| {
-        w.set_pllm(pllm as u8);
+        w.set_pllm(Pllm::from_bits(pllm as u8));
-        w.set_plln(plln as u16);
+        w.set_plln(Plln::from_bits(plln as u16));
         w.set_pllp(Pllp::from_bits(pllp as u8));
-        w.set_pllq(pllq as u8);
+        w.set_pllq(Pllq::from_bits(pllq as u8));
         w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
     });
 
@@ -263,17 +255,7 @@ pub(crate) unsafe fn init(config: Config) {
         })
     });
 
-    BackupDomain::configure_ls(
+    let rtc = config.ls.init();
-        config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
-        config.lsi,
-        config.lse.map(|_| Default::default()),
-    );
-
-    let rtc = match config.rtc {
-        Some(RtcClockSource::LSI) => Some(LSI_FREQ),
-        Some(RtcClockSource::LSE) => Some(config.lse.unwrap()),
-        _ => None,
-    };
 
     set_freqs(Clocks {
         sys: Hertz(sysclk),

embassy-stm32/src/rcc/g0.rs

@@ -1,6 +1,8 @@
-pub use super::bus::{AHBPrescaler, APBPrescaler};
 use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::{self, Hsidiv, Ppre, Sw};
+use crate::pac::rcc::vals::{self, Sw};
+pub use crate::pac::rcc::vals::{
+    Hpre as AHBPrescaler, Hsidiv as HSI16Prescaler, Pllm, Plln, Pllp, Pllq, Pllr, Ppre as APBPrescaler,
+};
 use crate::pac::{FLASH, PWR, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
@@ -8,9 +10,6 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
 /// System clock mux source
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
@@ -20,33 +19,6 @@ pub enum ClockSrc {
     LSI,
 }
 
-#[derive(Clone, Copy)]
-pub enum HSI16Prescaler {
-    NotDivided,
-    Div2,
-    Div4,
-    Div8,
-    Div16,
-    Div32,
-    Div64,
-    Div128,
-}
-
-impl Into<Hsidiv> for HSI16Prescaler {
-    fn into(self) -> Hsidiv {
-        match self {
-            HSI16Prescaler::NotDivided => Hsidiv::DIV1,
-            HSI16Prescaler::Div2 => Hsidiv::DIV2,
-            HSI16Prescaler::Div4 => Hsidiv::DIV4,
-            HSI16Prescaler::Div8 => Hsidiv::DIV8,
-            HSI16Prescaler::Div16 => Hsidiv::DIV16,
-            HSI16Prescaler::Div32 => Hsidiv::DIV32,
-            HSI16Prescaler::Div64 => Hsidiv::DIV64,
-            HSI16Prescaler::Div128 => Hsidiv::DIV128,
-        }
-    }
-}
-
 /// The PLL configuration.
 ///
 /// * `VCOCLK = source / m * n`
@@ -60,15 +32,15 @@ pub struct PllConfig {
     /// The initial divisor of that clock signal
     pub m: Pllm,
     /// The PLL VCO multiplier, which must be in the range `8..=86`.
-    pub n: u8,
+    pub n: Plln,
     /// The final divisor for `PLLRCLK` output which drives the system clock
     pub r: Pllr,
 
     /// The divisor for the `PLLQCLK` output, if desired
-    pub q: Option<Pllr>,
+    pub q: Option<Pllq>,
 
     /// The divisor for the `PLLPCLK` output, if desired
-    pub p: Option<Pllr>,
+    pub p: Option<Pllp>,
 }
 
 impl Default for PllConfig {
@@ -77,9 +49,9 @@ impl Default for PllConfig {
         // HSI16 / 1 * 8 / 2 = 64 MHz
         PllConfig {
             source: PllSrc::HSI16,
-            m: Pllm::Div1,
+            m: Pllm::DIV1,
-            n: 8,
+            n: Plln::MUL8,
-            r: Pllr::Div2,
+            r: Pllr::DIV2,
             q: None,
             p: None,
         }
@@ -92,131 +64,51 @@ pub enum PllSrc {
     HSE(Hertz),
 }
 
-#[derive(Clone, Copy)]
-pub enum Pllm {
-    Div1,
-    Div2,
-    Div3,
-    Div4,
-    Div5,
-    Div6,
-    Div7,
-    Div8,
-}
-
-impl From<Pllm> for u8 {
-    fn from(v: Pllm) -> Self {
-        match v {
-            Pllm::Div1 => 0b000,
-            Pllm::Div2 => 0b001,
-            Pllm::Div3 => 0b010,
-            Pllm::Div4 => 0b011,
-            Pllm::Div5 => 0b100,
-            Pllm::Div6 => 0b101,
-            Pllm::Div7 => 0b110,
-            Pllm::Div8 => 0b111,
-        }
-    }
-}
-
-impl From<Pllm> for u32 {
-    fn from(v: Pllm) -> Self {
-        match v {
-            Pllm::Div1 => 1,
-            Pllm::Div2 => 2,
-            Pllm::Div3 => 3,
-            Pllm::Div4 => 4,
-            Pllm::Div5 => 5,
-            Pllm::Div6 => 6,
-            Pllm::Div7 => 7,
-            Pllm::Div8 => 8,
-        }
-    }
-}
-
-#[derive(Clone, Copy)]
-pub enum Pllr {
-    Div2,
-    Div3,
-    Div4,
-    Div5,
-    Div6,
-    Div7,
-    Div8,
-}
-
-impl From<Pllr> for u8 {
-    fn from(v: Pllr) -> Self {
-        match v {
-            Pllr::Div2 => 0b000,
-            Pllr::Div3 => 0b001,
-            Pllr::Div4 => 0b010,
-            Pllr::Div5 => 0b011,
-            Pllr::Div6 => 0b101,
-            Pllr::Div7 => 0b110,
-            Pllr::Div8 => 0b111,
-        }
-    }
-}
-
-impl From<Pllr> for u32 {
-    fn from(v: Pllr) -> Self {
-        match v {
-            Pllr::Div2 => 2,
-            Pllr::Div3 => 3,
-            Pllr::Div4 => 4,
-            Pllr::Div5 => 5,
-            Pllr::Div6 => 6,
-            Pllr::Div7 => 7,
-            Pllr::Div8 => 8,
-        }
-    }
-}
-
 /// Clocks configutation
 pub struct Config {
     pub mux: ClockSrc,
     pub ahb_pre: AHBPrescaler,
     pub apb_pre: APBPrescaler,
     pub low_power_run: bool,
+    pub ls: super::LsConfig,
 }
 
 impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            mux: ClockSrc::HSI16(HSI16Prescaler::NotDivided),
+            mux: ClockSrc::HSI16(HSI16Prescaler::DIV1),
             ahb_pre: AHBPrescaler::DIV1,
             apb_pre: APBPrescaler::DIV1,
             low_power_run: false,
+            ls: Default::default(),
         }
     }
 }
 
 impl PllConfig {
-    pub(crate) fn init(self) -> u32 {
+    pub(crate) fn init(self) -> Hertz {
-        assert!(self.n >= 8 && self.n <= 86);
         let (src, input_freq) = match self.source {
-            PllSrc::HSI16 => (vals::Pllsrc::HSI16, HSI_FREQ.0),
+            PllSrc::HSI16 => (vals::Pllsrc::HSI16, HSI_FREQ),
-            PllSrc::HSE(freq) => (vals::Pllsrc::HSE, freq.0),
+            PllSrc::HSE(freq) => (vals::Pllsrc::HSE, freq),
         };
 
-        let m_freq = input_freq / u32::from(self.m);
+        let m_freq = input_freq / self.m;
         // RM0454 § 5.4.4:
         // > Caution: The software must set these bits so that the PLL input frequency after the
         // > /M divider is between 2.66 and 16 MHz.
-        debug_assert!(m_freq >= 2_660_000 && m_freq <= 16_000_000);
+        debug_assert!(m_freq.0 >= 2_660_000 && m_freq.0 <= 16_000_000);
 
         let n_freq = m_freq * self.n as u32;
         // RM0454 § 5.4.4:
         // > Caution: The software must set these bits so that the VCO output frequency is between
         // > 64 and 344 MHz.
-        debug_assert!(n_freq >= 64_000_000 && n_freq <= 344_000_000);
+        debug_assert!(n_freq.0 >= 64_000_000 && n_freq.0 <= 344_000_000);
 
-        let r_freq = n_freq / u32::from(self.r);
+        let r_freq = n_freq / self.r;
         // RM0454 § 5.4.4:
         // > Caution: The software must set this bitfield so as not to exceed 64 MHz on this clock.
-        debug_assert!(r_freq <= 64_000_000);
+        debug_assert!(r_freq.0 <= 64_000_000);
 
         // RM0454 § 5.2.3:
         // > To modify the PLL configuration, proceed as follows:
@@ -239,25 +131,16 @@ impl PllConfig {
             }
         }
 
-        // Configure PLLSYSCFGR
+        // Configure PLLCFGR
-        RCC.pllsyscfgr().modify(|w| {
+        RCC.pllcfgr().modify(|w| {
-            w.set_pllr(u8::from(self.r));
+            w.set_pllr(self.r);
             w.set_pllren(false);
-
+            w.set_pllq(self.q.unwrap_or(Pllq::DIV2));
-            if let Some(q) = self.q {
-                w.set_pllq(u8::from(q));
-            }
             w.set_pllqen(false);
-
+            w.set_pllp(self.p.unwrap_or(Pllp::DIV2));
-            if let Some(p) = self.p {
-                w.set_pllp(u8::from(p));
-            }
             w.set_pllpen(false);
-
             w.set_plln(self.n);
-
+            w.set_pllm(self.m);
-            w.set_pllm(self.m as u8);
-
             w.set_pllsrc(src)
         });
 
@@ -269,7 +152,7 @@ impl PllConfig {
 
         // > 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, and PLLREN in PLL
         // > configuration register (RCC_PLLCFGR).
-        RCC.pllsyscfgr().modify(|w| {
+        RCC.pllcfgr().modify(|w| {
             // We'll use R for system clock, so enable that unconditionally
             w.set_pllren(true);
 
@@ -286,21 +169,20 @@ pub(crate) unsafe fn init(config: Config) {
     let (sys_clk, sw) = match config.mux {
         ClockSrc::HSI16(div) => {
             // Enable HSI16
-            let div: Hsidiv = div.into();
             RCC.cr().write(|w| {
                 w.set_hsidiv(div);
                 w.set_hsion(true)
             });
             while !RCC.cr().read().hsirdy() {}
 
-            (HSI_FREQ.0 >> div.to_bits(), Sw::HSI)
+            (HSI_FREQ / div, Sw::HSI)
         }
         ClockSrc::HSE(freq) => {
             // Enable HSE
             RCC.cr().write(|w| w.set_hseon(true));
             while !RCC.cr().read().hserdy() {}
 
-            (freq.0, Sw::HSE)
+            (freq, Sw::HSE)
         }
         ClockSrc::PLL(pll) => {
             let freq = pll.init();
@@ -310,15 +192,15 @@ pub(crate) unsafe fn init(config: Config) {
             // Enable LSI
             RCC.csr().write(|w| w.set_lsion(true));
             while !RCC.csr().read().lsirdy() {}
-            (LSI_FREQ.0, Sw::LSI)
+            (super::LSI_FREQ, Sw::LSI)
         }
     };
 
     // Determine the flash latency implied by the target clock speed
     // RM0454 § 3.3.4:
-    let target_flash_latency = if sys_clk <= 24_000_000 {
+    let target_flash_latency = if sys_clk.0 <= 24_000_000 {
         Latency::WS0
-    } else if sys_clk <= 48_000_000 {
+    } else if sys_clk.0 <= 48_000_000 {
         Latency::WS1
     } else {
         Latency::WS2
@@ -353,7 +235,7 @@ pub(crate) unsafe fn init(config: Config) {
     }
 
     // Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once
-    let (sw, hpre, ppre) = (sw.into(), config.ahb_pre.into(), config.apb_pre.into());
+    let (sw, hpre, ppre) = (sw.into(), config.ahb_pre, config.apb_pre);
     RCC.cfgr().modify(|w| {
         w.set_sw(sw);
         w.set_hpre(hpre);
@@ -374,27 +256,28 @@ pub(crate) unsafe fn init(config: Config) {
         FLASH.acr().modify(|w| w.set_latency(target_flash_latency));
     }
 
-    let ahb_freq = Hertz(sys_clk) / config.ahb_pre;
+    let ahb_freq = sys_clk / config.ahb_pre;
 
     let (apb_freq, apb_tim_freq) = match config.apb_pre {
-        APBPrescaler::DIV1 => (ahb_freq.0, ahb_freq.0),
+        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: Ppre = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre.to_bits() - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq.0 / pre as u32;
-            (freq, freq * 2)
         }
     };
 
     if config.low_power_run {
-        assert!(sys_clk <= 2_000_000);
+        assert!(sys_clk.0 <= 2_000_000);
         PWR.cr1().modify(|w| w.set_lpr(true));
     }
 
+    let rtc = config.ls.init();
+
     set_freqs(Clocks {
-        sys: Hertz(sys_clk),
+        sys: sys_clk,
         ahb1: ahb_freq,
-        apb1: Hertz(apb_freq),
+        apb1: apb_freq,
-        apb1_tim: Hertz(apb_tim_freq),
+        apb1_tim: apb_tim_freq,
+        rtc,
     });
 }

embassy-stm32/src/rcc/g4.rs

@@ -2,7 +2,10 @@ use stm32_metapac::flash::vals::Latency;
 use stm32_metapac::rcc::vals::{Adcsel, Pllsrc, Sw};
 use stm32_metapac::FLASH;
 
-pub use super::bus::{AHBPrescaler, APBPrescaler};
+pub use crate::pac::rcc::vals::{
+    Adcsel as AdcClockSource, Hpre as AHBPrescaler, Pllm as PllM, Plln as PllN, Pllp as PllP, Pllq as PllQ,
+    Pllr as PllR, Ppre as APBPrescaler,
+};
 use crate::pac::{PWR, RCC};
 use crate::rcc::sealed::RccPeripheral;
 use crate::rcc::{set_freqs, Clocks};
@@ -11,32 +14,6 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
-#[derive(Clone, Copy)]
-pub enum AdcClockSource {
-    NoClk,
-    SysClk,
-    PllP,
-}
-
-impl AdcClockSource {
-    pub fn adcsel(&self) -> Adcsel {
-        match self {
-            AdcClockSource::NoClk => Adcsel::NOCLK,
-            AdcClockSource::SysClk => Adcsel::SYSCLK,
-            AdcClockSource::PllP => Adcsel::PLLP,
-        }
-    }
-}
-
-impl Default for AdcClockSource {
-    fn default() -> Self {
-        Self::NoClk
-    }
-}
-
 /// System clock mux source
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
@@ -61,181 +38,6 @@ impl Into<Pllsrc> for PllSrc {
     }
 }
 
-seq_macro::seq!(P in 2..=31 {
-    /// Output divider for the PLL P output.
-    #[derive(Clone, Copy)]
-    pub enum PllP {
-        // Note: If PLL P is set to 0 the PLLP bit controls the output division. There does not seem to
-        // a good reason to do this so the API does not support it.
-        // Div1 is invalid
-        #(
-            Div~P,
-        )*
-    }
-
-    impl From<PllP> for u8 {
-        /// Returns the register value for the P output divider.
-        fn from(val: PllP) -> u8 {
-            match val {
-                #(
-                    PllP::Div~P => P,
-                )*
-            }
-        }
-    }
-});
-
-impl PllP {
-    /// Returns the numeric value of the P output divider.
-    pub fn to_div(self) -> u32 {
-        let val: u8 = self.into();
-        val as u32
-    }
-}
-
-/// Output divider for the PLL Q output.
-#[derive(Clone, Copy)]
-pub enum PllQ {
-    Div2,
-    Div4,
-    Div6,
-    Div8,
-}
-
-impl PllQ {
-    /// Returns the numeric value of the Q output divider.
-    pub fn to_div(self) -> u32 {
-        let val: u8 = self.into();
-        (val as u32 + 1) * 2
-    }
-}
-
-impl From<PllQ> for u8 {
-    /// Returns the register value for the Q output divider.
-    fn from(val: PllQ) -> u8 {
-        match val {
-            PllQ::Div2 => 0b00,
-            PllQ::Div4 => 0b01,
-            PllQ::Div6 => 0b10,
-            PllQ::Div8 => 0b11,
-        }
-    }
-}
-
-/// Output divider for the PLL R output.
-#[derive(Clone, Copy)]
-pub enum PllR {
-    Div2,
-    Div4,
-    Div6,
-    Div8,
-}
-
-impl PllR {
-    /// Returns the numeric value of the R output divider.
-    pub fn to_div(self) -> u32 {
-        let val: u8 = self.into();
-        (val as u32 + 1) * 2
-    }
-}
-
-impl From<PllR> for u8 {
-    /// Returns the register value for the R output divider.
-    fn from(val: PllR) -> u8 {
-        match val {
-            PllR::Div2 => 0b00,
-            PllR::Div4 => 0b01,
-            PllR::Div6 => 0b10,
-            PllR::Div8 => 0b11,
-        }
-    }
-}
-
-seq_macro::seq!(N in 8..=127 {
-    /// Multiplication factor for the PLL VCO input clock.
-    #[derive(Clone, Copy)]
-    pub enum PllN {
-        #(
-            Mul~N,
-        )*
-    }
-
-    impl From<PllN> for u8 {
-        /// Returns the register value for the N multiplication factor.
-        fn from(val: PllN) -> u8 {
-            match val {
-                #(
-                    PllN::Mul~N => N,
-                )*
-            }
-        }
-    }
-
-    impl PllN {
-        /// Returns the numeric value of the N multiplication factor.
-        pub fn to_mul(self) -> u32 {
-            match self {
-                #(
-                    PllN::Mul~N => N,
-                )*
-            }
-        }
-    }
-});
-
-/// PLL Pre-division. This must be set such that the PLL input is between 2.66 MHz and 16 MHz.
-#[derive(Copy, Clone)]
-pub enum PllM {
-    Div1,
-    Div2,
-    Div3,
-    Div4,
-    Div5,
-    Div6,
-    Div7,
-    Div8,
-    Div9,
-    Div10,
-    Div11,
-    Div12,
-    Div13,
-    Div14,
-    Div15,
-    Div16,
-}
-
-impl PllM {
-    /// Returns the numeric value of the M pre-division.
-    pub fn to_div(self) -> u32 {
-        let val: u8 = self.into();
-        val as u32 + 1
-    }
-}
-
-impl From<PllM> for u8 {
-    /// Returns the register value for the M pre-division.
-    fn from(val: PllM) -> u8 {
-        match val {
-            PllM::Div1 => 0b0000,
-            PllM::Div2 => 0b0001,
-            PllM::Div3 => 0b0010,
-            PllM::Div4 => 0b0011,
-            PllM::Div5 => 0b0100,
-            PllM::Div6 => 0b0101,
-            PllM::Div7 => 0b0110,
-            PllM::Div8 => 0b0111,
-            PllM::Div9 => 0b1000,
-            PllM::Div10 => 0b1001,
-            PllM::Div11 => 0b1010,
-            PllM::Div12 => 0b1011,
-            PllM::Div13 => 0b1100,
-            PllM::Div14 => 0b1101,
-            PllM::Div15 => 0b1110,
-            PllM::Div16 => 0b1111,
-        }
-    }
-}
-
 /// PLL Configuration
 ///
 /// Use this struct to configure the PLL source, input frequency, multiplication factor, and output
@@ -261,32 +63,6 @@ pub struct Pll {
     pub div_r: Option<PllR>,
 }
 
-fn ahb_div(ahb: AHBPrescaler) -> u32 {
-    match ahb {
-        AHBPrescaler::DIV1 => 1,
-        AHBPrescaler::DIV2 => 2,
-        AHBPrescaler::DIV4 => 4,
-        AHBPrescaler::DIV8 => 8,
-        AHBPrescaler::DIV16 => 16,
-        AHBPrescaler::DIV64 => 64,
-        AHBPrescaler::DIV128 => 128,
-        AHBPrescaler::DIV256 => 256,
-        AHBPrescaler::DIV512 => 512,
-        _ => unreachable!(),
-    }
-}
-
-fn apb_div(apb: APBPrescaler) -> u32 {
-    match apb {
-        APBPrescaler::DIV1 => 1,
-        APBPrescaler::DIV2 => 2,
-        APBPrescaler::DIV4 => 4,
-        APBPrescaler::DIV8 => 8,
-        APBPrescaler::DIV16 => 16,
-        _ => unreachable!(),
-    }
-}
-
 /// Sets the source for the 48MHz clock to the USB and RNG peripherals.
 pub enum Clock48MhzSrc {
     /// Use the High Speed Internal Oscillator. For USB usage, the CRS must be used to calibrate the
@@ -322,6 +98,8 @@ pub struct Config {
     pub clock_48mhz_src: Option<Clock48MhzSrc>,
     pub adc12_clock_source: AdcClockSource,
     pub adc345_clock_source: AdcClockSource,
+
+    pub ls: super::LsConfig,
 }
 
 /// Configuration for the Clock Recovery System (CRS) used to trim the HSI48 oscillator.
@@ -341,8 +119,9 @@ impl Default for Config {
             low_power_run: false,
             pll: None,
             clock_48mhz_src: None,
-            adc12_clock_source: Default::default(),
+            adc12_clock_source: Adcsel::NOCLK,
-            adc345_clock_source: Default::default(),
+            adc345_clock_source: Adcsel::NOCLK,
+            ls: Default::default(),
         }
     }
 }
@@ -360,12 +139,12 @@ pub(crate) unsafe fn init(config: Config) {
                 RCC.cr().write(|w| w.set_hsion(true));
                 while !RCC.cr().read().hsirdy() {}
 
-                HSI_FREQ.0
+                HSI_FREQ
             }
             PllSrc::HSE(freq) => {
                 RCC.cr().write(|w| w.set_hseon(true));
                 while !RCC.cr().read().hserdy() {}
-                freq.0
+                freq
             }
         };
 
@@ -373,36 +152,36 @@ pub(crate) unsafe fn init(config: Config) {
         RCC.cr().modify(|w| w.set_pllon(false));
         while RCC.cr().read().pllrdy() {}
 
-        let internal_freq = src_freq / pll_config.prediv_m.to_div() * pll_config.mul_n.to_mul();
+        let internal_freq = src_freq / pll_config.prediv_m * pll_config.mul_n;
 
         RCC.pllcfgr().write(|w| {
-            w.set_plln(pll_config.mul_n.into());
+            w.set_plln(pll_config.mul_n);
-            w.set_pllm(pll_config.prediv_m.into());
+            w.set_pllm(pll_config.prediv_m);
             w.set_pllsrc(pll_config.source.into());
         });
 
         let pll_p_freq = pll_config.div_p.map(|div_p| {
             RCC.pllcfgr().modify(|w| {
-                w.set_pllpdiv(div_p.into());
+                w.set_pllp(div_p);
                 w.set_pllpen(true);
             });
-            Hertz(internal_freq / div_p.to_div())
+            internal_freq / div_p
         });
 
         let pll_q_freq = pll_config.div_q.map(|div_q| {
             RCC.pllcfgr().modify(|w| {
-                w.set_pllq(div_q.into());
+                w.set_pllq(div_q);
                 w.set_pllqen(true);
             });
-            Hertz(internal_freq / div_q.to_div())
+            internal_freq / div_q
         });
 
         let pll_r_freq = pll_config.div_r.map(|div_r| {
             RCC.pllcfgr().modify(|w| {
-                w.set_pllr(div_r.into());
+                w.set_pllr(div_r);
                 w.set_pllren(true);
             });
-            Hertz(internal_freq / div_r.to_div())
+            internal_freq / div_r
         });
 
         // Enable the PLL
@@ -422,14 +201,14 @@ pub(crate) unsafe fn init(config: Config) {
             RCC.cr().write(|w| w.set_hsion(true));
             while !RCC.cr().read().hsirdy() {}
 
-            (HSI_FREQ.0, Sw::HSI16)
+            (HSI_FREQ, Sw::HSI16)
         }
         ClockSrc::HSE(freq) => {
             // Enable HSE
             RCC.cr().write(|w| w.set_hseon(true));
             while !RCC.cr().read().hserdy() {}
 
-            (freq.0, Sw::HSE)
+            (freq, Sw::HSE)
         }
         ClockSrc::PLL => {
             assert!(pll_freq.is_some());
@@ -470,35 +249,32 @@ pub(crate) unsafe fn init(config: Config) {
                 }
             }
 
-            (freq, Sw::PLLRCLK)
+            (Hertz(freq), Sw::PLLRCLK)
         }
     };
 
     RCC.cfgr().modify(|w| {
         w.set_sw(sw);
-        w.set_hpre(config.ahb_pre.into());
+        w.set_hpre(config.ahb_pre);
-        w.set_ppre1(config.apb1_pre.into());
+        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre.into());
+        w.set_ppre2(config.apb2_pre);
     });
 
-    let ahb_freq: u32 = match config.ahb_pre {
+    let ahb_freq = sys_clk / config.ahb_pre;
-        AHBPrescaler::DIV1 => sys_clk,
-        pre => sys_clk / ahb_div(pre),
-    };
 
     let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let freq = ahb_freq / apb_div(pre);
+            let freq = ahb_freq / pre;
-            (freq, freq * 2)
+            (freq, freq * 2u32)
         }
     };
 
     let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let freq = ahb_freq / apb_div(pre);
+            let freq = ahb_freq / pre;
-            (freq, freq * 2)
+            (freq, freq * 2u32)
         }
     };
 
@@ -546,43 +322,40 @@ pub(crate) unsafe fn init(config: Config) {
         RCC.ccipr().modify(|w| w.set_clk48sel(source));
     }
 
-    RCC.ccipr()
+    RCC.ccipr().modify(|w| w.set_adc12sel(config.adc12_clock_source));
-        .modify(|w| w.set_adc12sel(config.adc12_clock_source.adcsel()));
+    RCC.ccipr().modify(|w| w.set_adc345sel(config.adc345_clock_source));
-    RCC.ccipr()
-        .modify(|w| w.set_adc345sel(config.adc345_clock_source.adcsel()));
 
     let adc12_ck = match config.adc12_clock_source {
-        AdcClockSource::NoClk => None,
+        AdcClockSource::NOCLK => None,
-        AdcClockSource::PllP => match &pll_freq {
+        AdcClockSource::PLLP => pll_freq.as_ref().unwrap().pll_p,
-            Some(pll) => pll.pll_p,
+        AdcClockSource::SYSCLK => Some(sys_clk),
-            None => None,
+        _ => unreachable!(),
-        },
-        AdcClockSource::SysClk => Some(Hertz(sys_clk)),
     };
 
     let adc345_ck = match config.adc345_clock_source {
-        AdcClockSource::NoClk => None,
+        AdcClockSource::NOCLK => None,
-        AdcClockSource::PllP => match &pll_freq {
+        AdcClockSource::PLLP => pll_freq.as_ref().unwrap().pll_p,
-            Some(pll) => pll.pll_p,
+        AdcClockSource::SYSCLK => Some(sys_clk),
-            None => None,
+        _ => unreachable!(),
-        },
-        AdcClockSource::SysClk => Some(Hertz(sys_clk)),
     };
 
     if config.low_power_run {
-        assert!(sys_clk <= 2_000_000);
+        assert!(sys_clk <= Hertz(2_000_000));
         PWR.cr1().modify(|w| w.set_lpr(true));
     }
 
+    let rtc = config.ls.init();
+
     set_freqs(Clocks {
-        sys: Hertz(sys_clk),
+        sys: sys_clk,
-        ahb1: Hertz(ahb_freq),
+        ahb1: ahb_freq,
-        ahb2: Hertz(ahb_freq),
+        ahb2: ahb_freq,
-        apb1: Hertz(apb1_freq),
+        apb1: apb1_freq,
-        apb1_tim: Hertz(apb1_tim_freq),
+        apb1_tim: apb1_tim_freq,
-        apb2: Hertz(apb2_freq),
+        apb2: apb2_freq,
-        apb2_tim: Hertz(apb2_tim_freq),
+        apb2_tim: apb2_tim_freq,
         adc: adc12_ck,
         adc34: adc345_ck,
+        rtc,
     });
 }

embassy-stm32/src/rcc/h.rs

@@ -6,8 +6,8 @@ use crate::pac::pwr::vals::Vos;
 pub use crate::pac::rcc::vals::Adcdacsel as AdcClockSource;
 #[cfg(stm32h7)]
 pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
-pub use crate::pac::rcc::vals::Ckpersel as PerClockSource;
 use crate::pac::rcc::vals::{Ckpersel, Hsidiv, Pllrge, Pllsrc, Pllvcosel, Sw, Timpre};
+pub use crate::pac::rcc::vals::{Ckpersel as PerClockSource, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul};
 use crate::pac::{FLASH, PWR, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
@@ -21,18 +21,15 @@ pub const CSI_FREQ: Hertz = Hertz(4_000_000);
 /// HSI48 speed
 pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
 
-/// LSI speed
+const VCO_RANGE: RangeInclusive<Hertz> = Hertz(150_000_000)..=Hertz(420_000_000);
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
-const VCO_RANGE: RangeInclusive<u32> = 150_000_000..=420_000_000;
 #[cfg(any(stm32h5, pwr_h7rm0455))]
-const VCO_WIDE_RANGE: RangeInclusive<u32> = 128_000_000..=560_000_000;
+const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(128_000_000)..=Hertz(560_000_000);
 #[cfg(pwr_h7rm0468)]
-const VCO_WIDE_RANGE: RangeInclusive<u32> = 192_000_000..=836_000_000;
+const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(192_000_000)..=Hertz(836_000_000);
 #[cfg(any(pwr_h7rm0399, pwr_h7rm0433))]
-const VCO_WIDE_RANGE: RangeInclusive<u32> = 192_000_000..=960_000_000;
+const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(192_000_000)..=Hertz(960_000_000);
 
-pub use super::bus::{AHBPrescaler, APBPrescaler};
+pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
 
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum VoltageScale {
@@ -46,9 +43,9 @@ pub enum VoltageScale {
 pub enum HseMode {
     /// crystal/ceramic oscillator (HSEBYP=0)
     Oscillator,
-    ///  external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
+    /// external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
     Bypass,
-    ///  external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
+    /// external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
     #[cfg(any(rcc_h5, rcc_h50))]
     BypassDigital,
 }
@@ -61,6 +58,15 @@ pub struct Hse {
     pub mode: HseMode,
 }
 
+#[cfg(stm32h7)]
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum Lse {
+    /// 32.768 kHz crystal/ceramic oscillator (LSEBYP=0)
+    Oscillator,
+    /// external clock input up to 1MHz (LSEBYP=1)
+    Bypass(Hertz),
+}
+
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum Hsi {
     /// 64Mhz
@@ -98,19 +104,19 @@ pub struct Pll {
     #[cfg(stm32h5)]
     pub source: PllSource,
 
-    /// PLL pre-divider (DIVM). Must be between 1 and 63.
+    /// PLL pre-divider (DIVM).
-    pub prediv: u8,
+    pub prediv: PllPreDiv,
 
-    /// PLL multiplication factor. Must be between 4 and 512.
+    /// PLL multiplication factor.
-    pub mul: u16,
+    pub mul: PllMul,
 
-    /// PLL P division factor. If None, PLL P output is disabled. Must be between 1 and 128.
+    /// PLL P division factor. If None, PLL P output is disabled.
     /// On PLL1, it must be even (in particular, it cannot be 1.)
-    pub divp: Option<u16>,
+    pub divp: Option<PllDiv>,
-    /// PLL Q division factor. If None, PLL Q output is disabled. Must be between 1 and 128.
+    /// PLL Q division factor. If None, PLL Q output is disabled.
-    pub divq: Option<u16>,
+    pub divq: Option<PllDiv>,
-    /// PLL R division factor. If None, PLL R output is disabled. Must be between 1 and 128.
+    /// PLL R division factor. If None, PLL R output is disabled.
-    pub divr: Option<u16>,
+    pub divr: Option<PllDiv>,
 }
 
 fn apb_div_tim(apb: &APBPrescaler, clk: Hertz, tim: TimerPrescaler) -> Hertz {
@@ -157,6 +163,10 @@ impl From<TimerPrescaler> for Timpre {
 pub struct Config {
     pub hsi: Option<Hsi>,
     pub hse: Option<Hse>,
+    #[cfg(stm32h7)]
+    pub lse: Option<Lse>,
+    #[cfg(stm32h7)]
+    pub lsi: bool,
     pub csi: bool,
     pub hsi48: bool,
     pub sys: Sysclk,
@@ -181,6 +191,7 @@ pub struct Config {
     pub adc_clock_source: AdcClockSource,
     pub timer_prescaler: TimerPrescaler,
     pub voltage_scale: VoltageScale,
+    pub ls: super::LsConfig,
 }
 
 impl Default for Config {
@@ -188,6 +199,10 @@ impl Default for Config {
         Self {
             hsi: Some(Hsi::Mhz64),
             hse: None,
+            #[cfg(stm32h7)]
+            lse: None,
+            #[cfg(stm32h7)]
+            lsi: false,
             csi: false,
             hsi48: false,
             sys: Sysclk::HSI,
@@ -210,6 +225,7 @@ impl Default for Config {
             adc_clock_source: AdcClockSource::from_bits(0), // PLL2_P on H7, HCLK on H5
             timer_prescaler: TimerPrescaler::DefaultX2,
             voltage_scale: VoltageScale::Scale0,
+            ls: Default::default(),
         }
     }
 }
@@ -448,6 +464,8 @@ pub(crate) unsafe fn init(config: Config) {
 
     flash_setup(hclk, config.voltage_scale);
 
+    let rtc = config.ls.init();
+
     #[cfg(stm32h7)]
     {
         RCC.d1cfgr().modify(|w| {
@@ -525,7 +543,8 @@ pub(crate) unsafe fn init(config: Config) {
         apb4,
         apb1_tim,
         apb2_tim,
-        adc: adc,
+        adc,
+        rtc,
     });
 }
 
@@ -553,9 +572,9 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
 
         // "To save power when PLL1 is not used, the value of PLL1M must be set to 0.""
         #[cfg(stm32h7)]
-        RCC.pllckselr().write(|w| w.set_divm(num, 0));
+        RCC.pllckselr().write(|w| w.set_divm(num, PllPreDiv::from_bits(0)));
         #[cfg(stm32h5)]
-        RCC.pllcfgr(num).write(|w| w.set_divm(0));
+        RCC.pllcfgr(num).write(|w| w.set_divm(PllPreDiv::from_bits(0)));
 
         return PllOutput {
             p: None,
@@ -564,9 +583,6 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
         };
     };
 
-    assert!(1 <= config.prediv && config.prediv <= 63);
-    assert!(4 <= config.mul && config.mul <= 512);
-
     #[cfg(stm32h5)]
     let source = config.source;
     #[cfg(stm32h7)]
@@ -593,31 +609,25 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
     let wide_allowed = ref_range != Pllrge::RANGE1;
 
     let vco_clk = ref_clk * config.mul;
-    let vco_range = if VCO_RANGE.contains(&vco_clk.0) {
+    let vco_range = if VCO_RANGE.contains(&vco_clk) {
         Pllvcosel::MEDIUMVCO
-    } else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk.0) {
+    } else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk) {
         Pllvcosel::WIDEVCO
     } else {
         panic!("pll vco_clk out of range: {} mhz", vco_clk.0)
     };
 
     let p = config.divp.map(|div| {
-        assert!(1 <= div && div <= 128);
         if num == 0 {
             // on PLL1, DIVP must be even.
-            assert!(div % 2 == 0);
+            // The enum value is 1 less than the divider, so check it's odd.
+            assert!(div.to_bits() % 2 == 1);
         }
 
         vco_clk / div
     });
-    let q = config.divq.map(|div| {
+    let q = config.divq.map(|div| vco_clk / div);
-        assert!(1 <= div && div <= 128);
+    let r = config.divr.map(|div| vco_clk / div);
-        vco_clk / div
-    });
-    let r = config.divr.map(|div| {
-        assert!(1 <= div && div <= 128);
-        vco_clk / div
-    });
 
     #[cfg(stm32h5)]
     RCC.pllcfgr(num).write(|w| {
@@ -648,10 +658,10 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
     }
 
     RCC.plldivr(num).write(|w| {
-        w.set_plln(config.mul - 1);
+        w.set_plln(config.mul);
-        w.set_pllp((config.divp.unwrap_or(1) - 1) as u8);
+        w.set_pllp(config.divp.unwrap_or(PllDiv::DIV2));
-        w.set_pllq((config.divq.unwrap_or(1) - 1) as u8);
+        w.set_pllq(config.divq.unwrap_or(PllDiv::DIV2));
-        w.set_pllr((config.divr.unwrap_or(1) - 1) as u8);
+        w.set_pllr(config.divr.unwrap_or(PllDiv::DIV2));
     });
 
     RCC.cr().modify(|w| w.set_pllon(num, true));

embassy-stm32/src/rcc/l0.rs

@@ -1,349 +0,0 @@
-use super::bd::BackupDomain;
-pub use super::bus::{AHBPrescaler, APBPrescaler};
-use super::RtcClockSource;
-pub use crate::pac::pwr::vals::Vos as VoltageScale;
-use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
-#[cfg(crs)]
-use crate::pac::{crs, CRS, SYSCFG};
-use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::{set_freqs, Clocks};
-use crate::time::Hertz;
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
-/// System clock mux source
-#[derive(Clone, Copy)]
-pub enum ClockSrc {
-    MSI(MSIRange),
-    PLL(PLLSource, PLLMul, PLLDiv),
-    HSE(Hertz),
-    HSI16,
-}
-
-/// MSI Clock Range
-///
-/// These ranges control the frequency of the MSI. Internally, these ranges map
-/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
-#[derive(Clone, Copy)]
-pub enum MSIRange {
-    /// Around 65.536 kHz
-    Range0,
-    /// Around 131.072 kHz
-    Range1,
-    /// Around 262.144 kHz
-    Range2,
-    /// Around 524.288 kHz
-    Range3,
-    /// Around 1.048 MHz
-    Range4,
-    /// Around 2.097 MHz (reset value)
-    Range5,
-    /// Around 4.194 MHz
-    Range6,
-}
-
-impl Default for MSIRange {
-    fn default() -> MSIRange {
-        MSIRange::Range5
-    }
-}
-
-/// PLL divider
-#[derive(Clone, Copy)]
-pub enum PLLDiv {
-    Div2,
-    Div3,
-    Div4,
-}
-
-/// PLL multiplier
-#[derive(Clone, Copy)]
-pub enum PLLMul {
-    Mul3,
-    Mul4,
-    Mul6,
-    Mul8,
-    Mul12,
-    Mul16,
-    Mul24,
-    Mul32,
-    Mul48,
-}
-
-/// PLL clock input source
-#[derive(Clone, Copy)]
-pub enum PLLSource {
-    HSI16,
-    HSE(Hertz),
-}
-
-impl From<PLLMul> for Pllmul {
-    fn from(val: PLLMul) -> Pllmul {
-        match val {
-            PLLMul::Mul3 => Pllmul::MUL3,
-            PLLMul::Mul4 => Pllmul::MUL4,
-            PLLMul::Mul6 => Pllmul::MUL6,
-            PLLMul::Mul8 => Pllmul::MUL8,
-            PLLMul::Mul12 => Pllmul::MUL12,
-            PLLMul::Mul16 => Pllmul::MUL16,
-            PLLMul::Mul24 => Pllmul::MUL24,
-            PLLMul::Mul32 => Pllmul::MUL32,
-            PLLMul::Mul48 => Pllmul::MUL48,
-        }
-    }
-}
-
-impl From<PLLDiv> for Plldiv {
-    fn from(val: PLLDiv) -> Plldiv {
-        match val {
-            PLLDiv::Div2 => Plldiv::DIV2,
-            PLLDiv::Div3 => Plldiv::DIV3,
-            PLLDiv::Div4 => Plldiv::DIV4,
-        }
-    }
-}
-
-impl From<PLLSource> for Pllsrc {
-    fn from(val: PLLSource) -> Pllsrc {
-        match val {
-            PLLSource::HSI16 => Pllsrc::HSI16,
-            PLLSource::HSE(_) => Pllsrc::HSE,
-        }
-    }
-}
-
-impl From<MSIRange> for Msirange {
-    fn from(val: MSIRange) -> Msirange {
-        match val {
-            MSIRange::Range0 => Msirange::RANGE0,
-            MSIRange::Range1 => Msirange::RANGE1,
-            MSIRange::Range2 => Msirange::RANGE2,
-            MSIRange::Range3 => Msirange::RANGE3,
-            MSIRange::Range4 => Msirange::RANGE4,
-            MSIRange::Range5 => Msirange::RANGE5,
-            MSIRange::Range6 => Msirange::RANGE6,
-        }
-    }
-}
-
-/// Clocks configutation
-pub struct Config {
-    pub mux: ClockSrc,
-    pub ahb_pre: AHBPrescaler,
-    pub apb1_pre: APBPrescaler,
-    pub apb2_pre: APBPrescaler,
-    #[cfg(crs)]
-    pub enable_hsi48: bool,
-    pub rtc: Option<RtcClockSource>,
-    pub lse: Option<Hertz>,
-    pub lsi: bool,
-    pub voltage_scale: VoltageScale,
-}
-
-impl Default for Config {
-    #[inline]
-    fn default() -> Config {
-        Config {
-            mux: ClockSrc::MSI(MSIRange::default()),
-            ahb_pre: AHBPrescaler::DIV1,
-            apb1_pre: APBPrescaler::DIV1,
-            apb2_pre: APBPrescaler::DIV1,
-            #[cfg(crs)]
-            enable_hsi48: false,
-            rtc: None,
-            lse: None,
-            lsi: false,
-            voltage_scale: VoltageScale::RANGE1,
-        }
-    }
-}
-
-pub(crate) unsafe fn init(config: Config) {
-    // Set voltage scale
-    while PWR.csr().read().vosf() {}
-    PWR.cr().write(|w| w.set_vos(config.voltage_scale));
-    while PWR.csr().read().vosf() {}
-
-    let (sys_clk, sw) = match config.mux {
-        ClockSrc::MSI(range) => {
-            // Set MSI range
-            RCC.icscr().write(|w| w.set_msirange(range.into()));
-
-            // Enable MSI
-            RCC.cr().write(|w| w.set_msion(true));
-            while !RCC.cr().read().msirdy() {}
-
-            let freq = 32_768 * (1 << (range as u8 + 1));
-            (freq, Sw::MSI)
-        }
-        ClockSrc::HSI16 => {
-            // Enable HSI16
-            RCC.cr().write(|w| w.set_hsi16on(true));
-            while !RCC.cr().read().hsi16rdyf() {}
-
-            (HSI_FREQ.0, Sw::HSI16)
-        }
-        ClockSrc::HSE(freq) => {
-            // Enable HSE
-            RCC.cr().write(|w| w.set_hseon(true));
-            while !RCC.cr().read().hserdy() {}
-
-            (freq.0, Sw::HSE)
-        }
-        ClockSrc::PLL(src, mul, div) => {
-            let freq = match src {
-                PLLSource::HSE(freq) => {
-                    // Enable HSE
-                    RCC.cr().write(|w| w.set_hseon(true));
-                    while !RCC.cr().read().hserdy() {}
-                    freq.0
-                }
-                PLLSource::HSI16 => {
-                    // Enable HSI
-                    RCC.cr().write(|w| w.set_hsi16on(true));
-                    while !RCC.cr().read().hsi16rdyf() {}
-                    HSI_FREQ.0
-                }
-            };
-
-            // Disable PLL
-            RCC.cr().modify(|w| w.set_pllon(false));
-            while RCC.cr().read().pllrdy() {}
-
-            let freq = match mul {
-                PLLMul::Mul3 => freq * 3,
-                PLLMul::Mul4 => freq * 4,
-                PLLMul::Mul6 => freq * 6,
-                PLLMul::Mul8 => freq * 8,
-                PLLMul::Mul12 => freq * 12,
-                PLLMul::Mul16 => freq * 16,
-                PLLMul::Mul24 => freq * 24,
-                PLLMul::Mul32 => freq * 32,
-                PLLMul::Mul48 => freq * 48,
-            };
-
-            let freq = match div {
-                PLLDiv::Div2 => freq / 2,
-                PLLDiv::Div3 => freq / 3,
-                PLLDiv::Div4 => freq / 4,
-            };
-            assert!(freq <= 32_000_000);
-
-            RCC.cfgr().write(move |w| {
-                w.set_pllmul(mul.into());
-                w.set_plldiv(div.into());
-                w.set_pllsrc(src.into());
-            });
-
-            // Enable PLL
-            RCC.cr().modify(|w| w.set_pllon(true));
-            while !RCC.cr().read().pllrdy() {}
-
-            (freq, Sw::PLL)
-        }
-    };
-
-    BackupDomain::configure_ls(
-        config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
-        config.lsi,
-        config.lse.map(|_| Default::default()),
-    );
-
-    let wait_states = match config.voltage_scale {
-        VoltageScale::RANGE1 => match sys_clk {
-            ..=16_000_000 => 0,
-            _ => 1,
-        },
-        VoltageScale::RANGE2 => match sys_clk {
-            ..=8_000_000 => 0,
-            _ => 1,
-        },
-        VoltageScale::RANGE3 => 0,
-        _ => unreachable!(),
-    };
-    FLASH.acr().modify(|w| {
-        w.set_latency(wait_states != 0);
-    });
-
-    RCC.cfgr().modify(|w| {
-        w.set_sw(sw);
-        w.set_hpre(config.ahb_pre.into());
-        w.set_ppre1(config.apb1_pre.into());
-        w.set_ppre2(config.apb2_pre.into());
-    });
-
-    let ahb_freq: u32 = match config.ahb_pre {
-        AHBPrescaler::DIV1 => sys_clk,
-        pre => {
-            let pre: Hpre = pre.into();
-            let pre = 1 << (pre.to_bits() as u32 - 7);
-            sys_clk / pre
-        }
-    };
-
-    let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let pre: Ppre = pre.into();
-            let pre: u8 = 1 << (pre.to_bits() - 3);
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
-        }
-    };
-
-    let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let pre: Ppre = pre.into();
-            let pre: u8 = 1 << (pre.to_bits() - 3);
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
-        }
-    };
-
-    #[cfg(crs)]
-    if config.enable_hsi48 {
-        // Reset CRS peripheral
-        RCC.apb1rstr().modify(|w| w.set_crsrst(true));
-        RCC.apb1rstr().modify(|w| w.set_crsrst(false));
-
-        // Enable CRS peripheral
-        RCC.apb1enr().modify(|w| w.set_crsen(true));
-
-        // Initialize CRS
-        CRS.cfgr().write(|w|
-
-        // Select LSE as synchronization source
-        w.set_syncsrc(crs::vals::Syncsrc::LSE));
-        CRS.cr().modify(|w| {
-            w.set_autotrimen(true);
-            w.set_cen(true);
-        });
-
-        // Enable VREFINT reference for HSI48 oscillator
-        SYSCFG.cfgr3().modify(|w| {
-            w.set_enref_hsi48(true);
-            w.set_en_vrefint(true);
-        });
-
-        // Select HSI48 as USB clock
-        RCC.ccipr().modify(|w| w.set_hsi48msel(true));
-
-        // Enable dedicated USB clock
-        RCC.crrcr().modify(|w| w.set_hsi48on(true));
-        while !RCC.crrcr().read().hsi48rdy() {}
-    }
-
-    set_freqs(Clocks {
-        sys: Hertz(sys_clk),
-        ahb1: Hertz(ahb_freq),
-        apb1: Hertz(apb1_freq),
-        apb2: Hertz(apb2_freq),
-        apb1_tim: Hertz(apb1_tim_freq),
-        apb2_tim: Hertz(apb2_tim_freq),
-    });
-}

embassy-stm32/src/rcc/l0l1.rs

@@ -0,0 +1,219 @@
+pub use crate::pac::pwr::vals::Vos as VoltageScale;
+pub use crate::pac::rcc::vals::{
+    Hpre as AHBPrescaler, Msirange as MSIRange, Plldiv as PLLDiv, Pllmul as PLLMul, Ppre as APBPrescaler,
+};
+use crate::pac::rcc::vals::{Pllsrc, Sw};
+#[cfg(crs)]
+use crate::pac::{crs, CRS, SYSCFG};
+use crate::pac::{FLASH, PWR, RCC};
+use crate::rcc::{set_freqs, Clocks};
+use crate::time::Hertz;
+
+/// HSI speed
+pub const HSI_FREQ: Hertz = Hertz(16_000_000);
+
+/// System clock mux source
+#[derive(Clone, Copy)]
+pub enum ClockSrc {
+    MSI(MSIRange),
+    PLL(PLLSource, PLLMul, PLLDiv),
+    HSE(Hertz),
+    HSI16,
+}
+
+/// PLL clock input source
+#[derive(Clone, Copy)]
+pub enum PLLSource {
+    HSI16,
+    HSE(Hertz),
+}
+
+impl From<PLLSource> for Pllsrc {
+    fn from(val: PLLSource) -> Pllsrc {
+        match val {
+            PLLSource::HSI16 => Pllsrc::HSI16,
+            PLLSource::HSE(_) => Pllsrc::HSE,
+        }
+    }
+}
+
+/// Clocks configutation
+pub struct Config {
+    pub mux: ClockSrc,
+    pub ahb_pre: AHBPrescaler,
+    pub apb1_pre: APBPrescaler,
+    pub apb2_pre: APBPrescaler,
+    #[cfg(crs)]
+    pub enable_hsi48: bool,
+    pub ls: super::LsConfig,
+    pub voltage_scale: VoltageScale,
+}
+
+impl Default for Config {
+    #[inline]
+    fn default() -> Config {
+        Config {
+            mux: ClockSrc::MSI(MSIRange::RANGE5),
+            ahb_pre: AHBPrescaler::DIV1,
+            apb1_pre: APBPrescaler::DIV1,
+            apb2_pre: APBPrescaler::DIV1,
+            #[cfg(crs)]
+            enable_hsi48: false,
+            voltage_scale: VoltageScale::RANGE1,
+            ls: Default::default(),
+        }
+    }
+}
+
+pub(crate) unsafe fn init(config: Config) {
+    // Set voltage scale
+    while PWR.csr().read().vosf() {}
+    PWR.cr().write(|w| w.set_vos(config.voltage_scale));
+    while PWR.csr().read().vosf() {}
+
+    let (sys_clk, sw) = match config.mux {
+        ClockSrc::MSI(range) => {
+            // Set MSI range
+            RCC.icscr().write(|w| w.set_msirange(range));
+
+            // Enable MSI
+            RCC.cr().write(|w| w.set_msion(true));
+            while !RCC.cr().read().msirdy() {}
+
+            let freq = 32_768 * (1 << (range as u8 + 1));
+            (Hertz(freq), Sw::MSI)
+        }
+        ClockSrc::HSI16 => {
+            // Enable HSI16
+            RCC.cr().write(|w| w.set_hsi16on(true));
+            while !RCC.cr().read().hsi16rdy() {}
+
+            (HSI_FREQ, Sw::HSI16)
+        }
+        ClockSrc::HSE(freq) => {
+            // Enable HSE
+            RCC.cr().write(|w| w.set_hseon(true));
+            while !RCC.cr().read().hserdy() {}
+
+            (freq, Sw::HSE)
+        }
+        ClockSrc::PLL(src, mul, div) => {
+            let freq = match src {
+                PLLSource::HSE(freq) => {
+                    // Enable HSE
+                    RCC.cr().write(|w| w.set_hseon(true));
+                    while !RCC.cr().read().hserdy() {}
+                    freq
+                }
+                PLLSource::HSI16 => {
+                    // Enable HSI
+                    RCC.cr().write(|w| w.set_hsi16on(true));
+                    while !RCC.cr().read().hsi16rdy() {}
+                    HSI_FREQ
+                }
+            };
+
+            // Disable PLL
+            RCC.cr().modify(|w| w.set_pllon(false));
+            while RCC.cr().read().pllrdy() {}
+
+            let freq = freq * mul / div;
+
+            assert!(freq <= Hertz(32_000_000));
+
+            RCC.cfgr().write(move |w| {
+                w.set_pllmul(mul);
+                w.set_plldiv(div);
+                w.set_pllsrc(src.into());
+            });
+
+            // Enable PLL
+            RCC.cr().modify(|w| w.set_pllon(true));
+            while !RCC.cr().read().pllrdy() {}
+
+            (freq, Sw::PLL)
+        }
+    };
+
+    let rtc = config.ls.init();
+
+    let wait_states = match (config.voltage_scale, sys_clk.0) {
+        (VoltageScale::RANGE1, ..=16_000_000) => 0,
+        (VoltageScale::RANGE2, ..=8_000_000) => 0,
+        (VoltageScale::RANGE3, ..=4_200_000) => 0,
+        _ => 1,
+    };
+
+    #[cfg(stm32l1)]
+    FLASH.acr().write(|w| w.set_acc64(true));
+    FLASH.acr().modify(|w| w.set_prften(true));
+    FLASH.acr().modify(|w| w.set_latency(wait_states != 0));
+
+    RCC.cfgr().modify(|w| {
+        w.set_sw(sw);
+        w.set_hpre(config.ahb_pre);
+        w.set_ppre1(config.apb1_pre);
+        w.set_ppre2(config.apb2_pre);
+    });
+
+    let ahb_freq = sys_clk / config.ahb_pre;
+
+    let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
+        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
+        pre => {
+            let freq = ahb_freq / pre;
+            (freq, freq * 2u32)
+        }
+    };
+
+    let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
+        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
+        pre => {
+            let freq = ahb_freq / pre;
+            (freq, freq * 2u32)
+        }
+    };
+
+    #[cfg(crs)]
+    if config.enable_hsi48 {
+        // Reset CRS peripheral
+        RCC.apb1rstr().modify(|w| w.set_crsrst(true));
+        RCC.apb1rstr().modify(|w| w.set_crsrst(false));
+
+        // Enable CRS peripheral
+        RCC.apb1enr().modify(|w| w.set_crsen(true));
+
+        // Initialize CRS
+        CRS.cfgr().write(|w|
+
+        // Select LSE as synchronization source
+        w.set_syncsrc(crs::vals::Syncsrc::LSE));
+        CRS.cr().modify(|w| {
+            w.set_autotrimen(true);
+            w.set_cen(true);
+        });
+
+        // Enable VREFINT reference for HSI48 oscillator
+        SYSCFG.cfgr3().modify(|w| {
+            w.set_enref_hsi48(true);
+            w.set_en_vrefint(true);
+        });
+
+        // Select HSI48 as USB clock
+        RCC.ccipr().modify(|w| w.set_hsi48msel(true));
+
+        // Enable dedicated USB clock
+        RCC.crrcr().modify(|w| w.set_hsi48on(true));
+        while !RCC.crrcr().read().hsi48rdy() {}
+    }
+
+    set_freqs(Clocks {
+        sys: sys_clk,
+        ahb1: ahb_freq,
+        apb1: apb1_freq,
+        apb2: apb2_freq,
+        apb1_tim: apb1_tim_freq,
+        apb2_tim: apb2_tim_freq,
+        rtc,
+    });
+}

embassy-stm32/src/rcc/l1.rs

@@ -1,279 +0,0 @@
-pub use super::bus::{AHBPrescaler, APBPrescaler};
-use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
-use crate::pac::{FLASH, RCC};
-use crate::rcc::{set_freqs, Clocks};
-use crate::time::Hertz;
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
-/// System clock mux source
-#[derive(Clone, Copy)]
-pub enum ClockSrc {
-    MSI(MSIRange),
-    PLL(PLLSource, PLLMul, PLLDiv),
-    HSE(Hertz),
-    HSI,
-}
-
-/// MSI Clock Range
-///
-/// These ranges control the frequency of the MSI. Internally, these ranges map
-/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
-#[derive(Clone, Copy)]
-pub enum MSIRange {
-    /// Around 65.536 kHz
-    Range0,
-    /// Around 131.072 kHz
-    Range1,
-    /// Around 262.144 kHz
-    Range2,
-    /// Around 524.288 kHz
-    Range3,
-    /// Around 1.048 MHz
-    Range4,
-    /// Around 2.097 MHz (reset value)
-    Range5,
-    /// Around 4.194 MHz
-    Range6,
-}
-
-impl Default for MSIRange {
-    fn default() -> MSIRange {
-        MSIRange::Range5
-    }
-}
-
-/// PLL divider
-#[derive(Clone, Copy)]
-pub enum PLLDiv {
-    Div2,
-    Div3,
-    Div4,
-}
-
-/// PLL multiplier
-#[derive(Clone, Copy)]
-pub enum PLLMul {
-    Mul3,
-    Mul4,
-    Mul6,
-    Mul8,
-    Mul12,
-    Mul16,
-    Mul24,
-    Mul32,
-    Mul48,
-}
-
-/// PLL clock input source
-#[derive(Clone, Copy)]
-pub enum PLLSource {
-    HSI,
-    HSE(Hertz),
-}
-
-impl From<PLLMul> for Pllmul {
-    fn from(val: PLLMul) -> Pllmul {
-        match val {
-            PLLMul::Mul3 => Pllmul::MUL3,
-            PLLMul::Mul4 => Pllmul::MUL4,
-            PLLMul::Mul6 => Pllmul::MUL6,
-            PLLMul::Mul8 => Pllmul::MUL8,
-            PLLMul::Mul12 => Pllmul::MUL12,
-            PLLMul::Mul16 => Pllmul::MUL16,
-            PLLMul::Mul24 => Pllmul::MUL24,
-            PLLMul::Mul32 => Pllmul::MUL32,
-            PLLMul::Mul48 => Pllmul::MUL48,
-        }
-    }
-}
-
-impl From<PLLDiv> for Plldiv {
-    fn from(val: PLLDiv) -> Plldiv {
-        match val {
-            PLLDiv::Div2 => Plldiv::DIV2,
-            PLLDiv::Div3 => Plldiv::DIV3,
-            PLLDiv::Div4 => Plldiv::DIV4,
-        }
-    }
-}
-
-impl From<PLLSource> for Pllsrc {
-    fn from(val: PLLSource) -> Pllsrc {
-        match val {
-            PLLSource::HSI => Pllsrc::HSI,
-            PLLSource::HSE(_) => Pllsrc::HSE,
-        }
-    }
-}
-
-impl From<MSIRange> for Msirange {
-    fn from(val: MSIRange) -> Msirange {
-        match val {
-            MSIRange::Range0 => Msirange::RANGE0,
-            MSIRange::Range1 => Msirange::RANGE1,
-            MSIRange::Range2 => Msirange::RANGE2,
-            MSIRange::Range3 => Msirange::RANGE3,
-            MSIRange::Range4 => Msirange::RANGE4,
-            MSIRange::Range5 => Msirange::RANGE5,
-            MSIRange::Range6 => Msirange::RANGE6,
-        }
-    }
-}
-
-/// Clocks configutation
-pub struct Config {
-    pub mux: ClockSrc,
-    pub ahb_pre: AHBPrescaler,
-    pub apb1_pre: APBPrescaler,
-    pub apb2_pre: APBPrescaler,
-}
-
-impl Default for Config {
-    #[inline]
-    fn default() -> Config {
-        Config {
-            mux: ClockSrc::MSI(MSIRange::default()),
-            ahb_pre: AHBPrescaler::DIV1,
-            apb1_pre: APBPrescaler::DIV1,
-            apb2_pre: APBPrescaler::DIV1,
-        }
-    }
-}
-
-pub(crate) unsafe fn init(config: Config) {
-    let (sys_clk, sw) = match config.mux {
-        ClockSrc::MSI(range) => {
-            // Set MSI range
-            RCC.icscr().write(|w| w.set_msirange(range.into()));
-
-            // Enable MSI
-            RCC.cr().write(|w| w.set_msion(true));
-            while !RCC.cr().read().msirdy() {}
-
-            let freq = 32_768 * (1 << (range as u8 + 1));
-            (freq, Sw::MSI)
-        }
-        ClockSrc::HSI => {
-            // Enable HSI
-            RCC.cr().write(|w| w.set_hsion(true));
-            while !RCC.cr().read().hsirdy() {}
-
-            (HSI_FREQ.0, Sw::HSI)
-        }
-        ClockSrc::HSE(freq) => {
-            // Enable HSE
-            RCC.cr().write(|w| w.set_hseon(true));
-            while !RCC.cr().read().hserdy() {}
-
-            (freq.0, Sw::HSE)
-        }
-        ClockSrc::PLL(src, mul, div) => {
-            let freq = match src {
-                PLLSource::HSE(freq) => {
-                    // Enable HSE
-                    RCC.cr().write(|w| w.set_hseon(true));
-                    while !RCC.cr().read().hserdy() {}
-                    freq.0
-                }
-                PLLSource::HSI => {
-                    // Enable HSI
-                    RCC.cr().write(|w| w.set_hsion(true));
-                    while !RCC.cr().read().hsirdy() {}
-                    HSI_FREQ.0
-                }
-            };
-
-            // Disable PLL
-            RCC.cr().modify(|w| w.set_pllon(false));
-            while RCC.cr().read().pllrdy() {}
-
-            let freq = match mul {
-                PLLMul::Mul3 => freq * 3,
-                PLLMul::Mul4 => freq * 4,
-                PLLMul::Mul6 => freq * 6,
-                PLLMul::Mul8 => freq * 8,
-                PLLMul::Mul12 => freq * 12,
-                PLLMul::Mul16 => freq * 16,
-                PLLMul::Mul24 => freq * 24,
-                PLLMul::Mul32 => freq * 32,
-                PLLMul::Mul48 => freq * 48,
-            };
-
-            let freq = match div {
-                PLLDiv::Div2 => freq / 2,
-                PLLDiv::Div3 => freq / 3,
-                PLLDiv::Div4 => freq / 4,
-            };
-            assert!(freq <= 32_000_000);
-
-            RCC.cfgr().write(move |w| {
-                w.set_pllmul(mul.into());
-                w.set_plldiv(div.into());
-                w.set_pllsrc(src.into());
-            });
-
-            // Enable PLL
-            RCC.cr().modify(|w| w.set_pllon(true));
-            while !RCC.cr().read().pllrdy() {}
-
-            (freq, Sw::PLL)
-        }
-    };
-
-    // Set flash 64-bit access, prefetch and wait states
-    if sys_clk >= 16_000_000 {
-        FLASH.acr().write(|w| w.set_acc64(true));
-        FLASH.acr().modify(|w| w.set_prften(true));
-        FLASH.acr().modify(|w| w.set_latency(true));
-    }
-
-    RCC.cfgr().modify(|w| {
-        w.set_sw(sw);
-        w.set_hpre(config.ahb_pre.into());
-        w.set_ppre1(config.apb1_pre.into());
-        w.set_ppre2(config.apb2_pre.into());
-    });
-
-    let ahb_freq: u32 = match config.ahb_pre {
-        AHBPrescaler::DIV1 => sys_clk,
-        pre => {
-            let pre: Hpre = pre.into();
-            let pre = 1 << (pre.to_bits() as u32 - 7);
-            sys_clk / pre
-        }
-    };
-
-    let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let pre: Ppre = pre.into();
-            let pre: u8 = 1 << (pre.to_bits() - 3);
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
-        }
-    };
-
-    let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let pre: Ppre = pre.into();
-            let pre: u8 = 1 << (pre.to_bits() - 3);
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
-        }
-    };
-
-    set_freqs(Clocks {
-        sys: Hertz(sys_clk),
-        ahb1: Hertz(ahb_freq),
-        apb1: Hertz(apb1_freq),
-        apb2: Hertz(apb2_freq),
-        apb1_tim: Hertz(apb1_tim_freq),
-        apb2_tim: Hertz(apb2_tim_freq),
-    });
-}

embassy-stm32/src/rcc/l4.rs

@@ -1,85 +1,25 @@
-use core::marker::PhantomData;
+use crate::pac::rcc::regs::Cfgr;
-
+pub use crate::pac::rcc::vals::{
-use embassy_hal_internal::into_ref;
+    Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv,
-use stm32_metapac::rcc::regs::Cfgr;
+    Pllr as PllRDiv, Ppre as APBPrescaler,
-use stm32_metapac::rcc::vals::{Mcopre, Mcosel};
+};
-
+use crate::pac::rcc::vals::{Msirange, Pllsrc, Sw};
-pub use super::bus::{AHBPrescaler, APBPrescaler};
-use crate::gpio::sealed::AFType;
-use crate::gpio::Speed;
-use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
 use crate::pac::{FLASH, RCC};
-use crate::rcc::bd::{BackupDomain, RtcClockSource};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
-use crate::{peripherals, Peripheral};
 
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
 /// System clock mux source
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
     MSI(MSIRange),
-    PLL(PLLSource, PLLClkDiv, PLLSrcDiv, PLLMul, Option<PLL48Div>),
+    PLL(PLLSource, PllRDiv, PllPreDiv, PllMul, Option<PllQDiv>),
     HSE(Hertz),
     HSI16,
 }
 
-/// MSI Clock Range
-///
-/// These ranges control the frequency of the MSI. Internally, these ranges map
-/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
-#[derive(Clone, Copy)]
-pub enum MSIRange {
-    /// Around 100 kHz
-    Range0,
-    /// Around 200 kHz
-    Range1,
-    /// Around 400 kHz
-    Range2,
-    /// Around 800 kHz
-    Range3,
-    /// Around 1 MHz
-    Range4,
-    /// Around 2 MHz
-    Range5,
-    /// Around 4 MHz (reset value)
-    Range6,
-    /// Around 8 MHz
-    Range7,
-    /// Around 16 MHz
-    Range8,
-    /// Around 24 MHz
-    Range9,
-    /// Around 32 MHz
-    Range10,
-    /// Around 48 MHz
-    Range11,
-}
-
-impl Default for MSIRange {
-    fn default() -> MSIRange {
-        MSIRange::Range6
-    }
-}
-
-pub type PLL48Div = PLLClkDiv;
-pub type PLLSAI1RDiv = PLLClkDiv;
-pub type PLLSAI1QDiv = PLLClkDiv;
-pub type PLLSAI1PDiv = PLLClkDiv;
-
-/// PLL divider
-#[derive(Clone, Copy)]
-pub enum PLLDiv {
-    Div2,
-    Div3,
-    Div4,
-}
-
 /// PLL clock input source
 #[derive(Clone, Copy)]
 pub enum PLLSource {
@@ -88,95 +28,6 @@ pub enum PLLSource {
     MSI(MSIRange),
 }
 
-seq_macro::seq!(N in 8..=86 {
-    #[derive(Clone, Copy)]
-    pub enum PLLMul {
-        #(
-            Mul~N,
-        )*
-    }
-
-    impl From<PLLMul> for u8 {
-        fn from(val: PLLMul) -> u8 {
-            match val {
-                #(
-                    PLLMul::Mul~N => N,
-                )*
-            }
-        }
-    }
-
-    impl PLLMul {
-        pub fn to_mul(self) -> u32 {
-            match self {
-                #(
-                    PLLMul::Mul~N => N,
-                )*
-            }
-        }
-    }
-});
-
-#[derive(Clone, Copy)]
-pub enum PLLClkDiv {
-    Div2,
-    Div4,
-    Div6,
-    Div8,
-}
-
-impl PLLClkDiv {
-    pub fn to_div(self) -> u32 {
-        let val: u8 = self.into();
-        (val as u32 + 1) * 2
-    }
-}
-
-impl From<PLLClkDiv> for u8 {
-    fn from(val: PLLClkDiv) -> u8 {
-        match val {
-            PLLClkDiv::Div2 => 0b00,
-            PLLClkDiv::Div4 => 0b01,
-            PLLClkDiv::Div6 => 0b10,
-            PLLClkDiv::Div8 => 0b11,
-        }
-    }
-}
-
-#[derive(Clone, Copy)]
-pub enum PLLSrcDiv {
-    Div1,
-    Div2,
-    Div3,
-    Div4,
-    Div5,
-    Div6,
-    Div7,
-    Div8,
-}
-
-impl PLLSrcDiv {
-    pub fn to_div(self) -> u32 {
-        let val: u8 = self.into();
-        val as u32 + 1
-    }
-}
-
-impl From<PLLSrcDiv> for u8 {
-    fn from(val: PLLSrcDiv) -> u8 {
-        match val {
-            PLLSrcDiv::Div1 => 0b000,
-            PLLSrcDiv::Div2 => 0b001,
-            PLLSrcDiv::Div3 => 0b010,
-            PLLSrcDiv::Div4 => 0b011,
-            PLLSrcDiv::Div5 => 0b100,
-            PLLSrcDiv::Div6 => 0b101,
-            PLLSrcDiv::Div7 => 0b110,
-            PLLSrcDiv::Div8 => 0b111,
-        }
-    }
-}
-
 impl From<PLLSource> for Pllsrc {
     fn from(val: PLLSource) -> Pllsrc {
         match val {
@@ -187,214 +38,41 @@ impl From<PLLSource> for Pllsrc {
     }
 }
 
-impl From<MSIRange> for Msirange {
-    fn from(val: MSIRange) -> Msirange {
-        match val {
-            MSIRange::Range0 => Msirange::RANGE100K,
-            MSIRange::Range1 => Msirange::RANGE200K,
-            MSIRange::Range2 => Msirange::RANGE400K,
-            MSIRange::Range3 => Msirange::RANGE800K,
-            MSIRange::Range4 => Msirange::RANGE1M,
-            MSIRange::Range5 => Msirange::RANGE2M,
-            MSIRange::Range6 => Msirange::RANGE4M,
-            MSIRange::Range7 => Msirange::RANGE8M,
-            MSIRange::Range8 => Msirange::RANGE16M,
-            MSIRange::Range9 => Msirange::RANGE24M,
-            MSIRange::Range10 => Msirange::RANGE32M,
-            MSIRange::Range11 => Msirange::RANGE48M,
-        }
-    }
-}
-
-impl From<MSIRange> for u32 {
-    fn from(val: MSIRange) -> u32 {
-        match val {
-            MSIRange::Range0 => 100_000,
-            MSIRange::Range1 => 200_000,
-            MSIRange::Range2 => 400_000,
-            MSIRange::Range3 => 800_000,
-            MSIRange::Range4 => 1_000_000,
-            MSIRange::Range5 => 2_000_000,
-            MSIRange::Range6 => 4_000_000,
-            MSIRange::Range7 => 8_000_000,
-            MSIRange::Range8 => 16_000_000,
-            MSIRange::Range9 => 24_000_000,
-            MSIRange::Range10 => 32_000_000,
-            MSIRange::Range11 => 48_000_000,
-        }
-    }
-}
-
 /// Clocks configutation
 pub struct Config {
     pub mux: ClockSrc,
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
-    pub pllsai1: Option<(
+    pub pllsai1: Option<(PllMul, PllPreDiv, Option<PllRDiv>, Option<PllQDiv>, Option<PllPDiv>)>,
-        PLLMul,
-        PLLSrcDiv,
-        Option<PLLSAI1RDiv>,
-        Option<PLLSAI1QDiv>,
-        Option<PLLSAI1PDiv>,
-    )>,
     #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
     pub hsi48: bool,
-    pub rtc_mux: RtcClockSource,
+    pub ls: super::LsConfig,
-    pub lse: Option<Hertz>,
-    pub lsi: bool,
 }
 
 impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            mux: ClockSrc::MSI(MSIRange::Range6),
+            mux: ClockSrc::MSI(MSIRange::RANGE4M),
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
             pllsai1: None,
             #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
             hsi48: false,
-            rtc_mux: RtcClockSource::LSI,
+            ls: Default::default(),
-            lsi: true,
-            lse: None,
         }
     }
 }
 
-pub enum McoClock {
-    DIV1,
-    DIV2,
-    DIV4,
-    DIV8,
-    DIV16,
-}
-
-impl McoClock {
-    fn into_raw(&self) -> Mcopre {
-        match self {
-            McoClock::DIV1 => Mcopre::DIV1,
-            McoClock::DIV2 => Mcopre::DIV2,
-            McoClock::DIV4 => Mcopre::DIV4,
-            McoClock::DIV8 => Mcopre::DIV8,
-            McoClock::DIV16 => Mcopre::DIV16,
-        }
-    }
-}
-
-#[derive(Copy, Clone)]
-pub enum Mco1Source {
-    Disabled,
-    Lse,
-    Lsi,
-    Hse,
-    Hsi16,
-    PllClk,
-    SysClk,
-    Msi,
-    #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
-    Hsi48,
-}
-
-impl Default for Mco1Source {
-    fn default() -> Self {
-        Self::Hsi16
-    }
-}
-
-pub trait McoSource {
-    type Raw;
-
-    fn into_raw(&self) -> Self::Raw;
-}
-
-impl McoSource for Mco1Source {
-    type Raw = Mcosel;
-    fn into_raw(&self) -> Self::Raw {
-        match self {
-            Mco1Source::Disabled => Mcosel::NOCLOCK,
-            Mco1Source::Lse => Mcosel::LSE,
-            Mco1Source::Lsi => Mcosel::LSI,
-            Mco1Source::Hse => Mcosel::HSE,
-            Mco1Source::Hsi16 => Mcosel::HSI16,
-            Mco1Source::PllClk => Mcosel::PLL,
-            Mco1Source::SysClk => Mcosel::SYSCLK,
-            Mco1Source::Msi => Mcosel::MSI,
-            #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
-            Mco1Source::Hsi48 => Mcosel::HSI48,
-        }
-    }
-}
-
-pub(crate) mod sealed {
-    use stm32_metapac::rcc::vals::Mcopre;
-    pub trait McoInstance {
-        type Source;
-        unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre);
-    }
-}
-
-pub trait McoInstance: sealed::McoInstance + 'static {}
-
-pin_trait!(McoPin, McoInstance);
-
-impl sealed::McoInstance for peripherals::MCO {
-    type Source = Mcosel;
-
-    unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre) {
-        RCC.cfgr().modify(|w| {
-            w.set_mcosel(source);
-            w.set_mcopre(prescaler);
-        });
-
-        match source {
-            Mcosel::HSI16 => {
-                RCC.cr().modify(|w| w.set_hsion(true));
-                while !RCC.cr().read().hsirdy() {}
-            }
-            #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
-            Mcosel::HSI48 => {
-                RCC.crrcr().modify(|w| w.set_hsi48on(true));
-                while !RCC.crrcr().read().hsi48rdy() {}
-            }
-            _ => {}
-        }
-    }
-}
-
-impl McoInstance for peripherals::MCO {}
-
-pub struct Mco<'d, T: McoInstance> {
-    phantom: PhantomData<&'d mut T>,
-}
-
-impl<'d, T: McoInstance> Mco<'d, T> {
-    pub fn new(
-        _peri: impl Peripheral<P = T> + 'd,
-        pin: impl Peripheral<P = impl McoPin<T>> + 'd,
-        source: impl McoSource<Raw = T::Source>,
-        prescaler: McoClock,
-    ) -> Self {
-        into_ref!(pin);
-
-        critical_section::with(|_| unsafe {
-            T::apply_clock_settings(source.into_raw(), prescaler.into_raw());
-            pin.set_as_af(pin.af_num(), AFType::OutputPushPull);
-            pin.set_speed(Speed::VeryHigh);
-        });
-
-        Self { phantom: PhantomData }
-    }
-}
-
 pub(crate) unsafe fn init(config: Config) {
     // Switch to MSI to prevent problems with PLL configuration.
     if !RCC.cr().read().msion() {
         // Turn on MSI and configure it to 4MHz.
         RCC.cr().modify(|w| {
             w.set_msirgsel(true); // MSI Range is provided by MSIRANGE[3:0].
-            w.set_msirange(MSIRange::default().into());
+            w.set_msirange(MSIRange::RANGE4M);
             w.set_msipllen(false);
             w.set_msion(true)
         });
@@ -409,73 +87,68 @@ pub(crate) unsafe fn init(config: Config) {
         while RCC.cfgr().read().sws() != Sw::MSI {}
     }
 
-    BackupDomain::configure_ls(config.rtc_mux, config.lsi, config.lse.map(|_| Default::default()));
+    let rtc = config.ls.init();
 
     let (sys_clk, sw) = match config.mux {
         ClockSrc::MSI(range) => {
             // Enable MSI
             RCC.cr().write(|w| {
-                let bits: Msirange = range.into();
+                w.set_msirange(range);
-                w.set_msirange(bits);
                 w.set_msirgsel(true);
                 w.set_msion(true);
 
-                if let RtcClockSource::LSE = config.rtc_mux {
+                // If LSE is enabled, enable calibration of MSI
-                    // If LSE is enabled, enable calibration of MSI
+                w.set_msipllen(config.ls.lse.is_some());
-                    w.set_msipllen(true);
-                } else {
-                    w.set_msipllen(false);
-                }
             });
             while !RCC.cr().read().msirdy() {}
 
             // Enable as clock source for USB, RNG if running at 48 MHz
-            if let MSIRange::Range11 = range {
+            if range == MSIRange::RANGE48M {
                 RCC.ccipr().modify(|w| {
                     w.set_clk48sel(0b11);
                 });
             }
-            (range.into(), Sw::MSI)
+            (msirange_to_hertz(range), Sw::MSI)
         }
         ClockSrc::HSI16 => {
             // Enable HSI16
             RCC.cr().write(|w| w.set_hsion(true));
             while !RCC.cr().read().hsirdy() {}
 
-            (HSI_FREQ.0, Sw::HSI16)
+            (HSI_FREQ, Sw::HSI16)
         }
         ClockSrc::HSE(freq) => {
             // Enable HSE
             RCC.cr().write(|w| w.set_hseon(true));
             while !RCC.cr().read().hserdy() {}
 
-            (freq.0, Sw::HSE)
+            (freq, Sw::HSE)
         }
-        ClockSrc::PLL(src, div, prediv, mul, pll48div) => {
+        ClockSrc::PLL(src, divr, prediv, mul, divq) => {
             let src_freq = match src {
                 PLLSource::HSE(freq) => {
                     // Enable HSE
                     RCC.cr().write(|w| w.set_hseon(true));
                     while !RCC.cr().read().hserdy() {}
-                    freq.0
+                    freq
                 }
                 PLLSource::HSI16 => {
                     // Enable HSI
                     RCC.cr().write(|w| w.set_hsion(true));
                     while !RCC.cr().read().hsirdy() {}
-                    HSI_FREQ.0
+                    HSI_FREQ
                 }
                 PLLSource::MSI(range) => {
                     // Enable MSI
                     RCC.cr().write(|w| {
-                        let bits: Msirange = range.into();
+                        w.set_msirange(range);
-                        w.set_msirange(bits);
                         w.set_msipllen(false); // should be turned on if LSE is started
                         w.set_msirgsel(true);
                         w.set_msion(true);
                     });
                     while !RCC.cr().read().msirdy() {}
-                    range.into()
+
+                    msirange_to_hertz(range)
                 }
             };
 
@@ -483,28 +156,28 @@ pub(crate) unsafe fn init(config: Config) {
             RCC.cr().modify(|w| w.set_pllon(false));
             while RCC.cr().read().pllrdy() {}
 
-            let freq = (src_freq / prediv.to_div() * mul.to_mul()) / div.to_div();
+            let freq = src_freq / prediv * mul / divr;
 
             #[cfg(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx))]
-            assert!(freq <= 120_000_000);
+            assert!(freq.0 <= 120_000_000);
             #[cfg(not(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx)))]
-            assert!(freq <= 80_000_000);
+            assert!(freq.0 <= 80_000_000);
 
             RCC.pllcfgr().write(move |w| {
-                w.set_plln(mul.into());
+                w.set_plln(mul);
-                w.set_pllm(prediv.into());
+                w.set_pllm(prediv);
-                w.set_pllr(div.into());
+                w.set_pllr(divr);
-                if let Some(pll48div) = pll48div {
+                if let Some(divq) = divq {
-                    w.set_pllq(pll48div.into());
+                    w.set_pllq(divq);
                     w.set_pllqen(true);
                 }
                 w.set_pllsrc(src.into());
             });
 
             // Enable as clock source for USB, RNG if PLL48 divisor is provided
-            if let Some(pll48div) = pll48div {
+            if let Some(divq) = divq {
-                let freq = (src_freq / prediv.to_div() * mul.to_mul()) / pll48div.to_div();
+                let freq = src_freq / prediv * mul / divq;
-                assert!(freq == 48_000_000);
+                assert!(freq.0 == 48_000_000);
                 RCC.ccipr().modify(|w| {
                     w.set_clk48sel(0b10);
                 });
@@ -512,25 +185,25 @@ pub(crate) unsafe fn init(config: Config) {
 
             if let Some((mul, prediv, r_div, q_div, p_div)) = config.pllsai1 {
                 RCC.pllsai1cfgr().write(move |w| {
-                    w.set_pllsai1n(mul.into());
+                    w.set_plln(mul);
-                    w.set_pllsai1m(prediv.into());
+                    w.set_pllm(prediv);
                     if let Some(r_div) = r_div {
-                        w.set_pllsai1r(r_div.into());
+                        w.set_pllr(r_div);
-                        w.set_pllsai1ren(true);
+                        w.set_pllren(true);
                     }
                     if let Some(q_div) = q_div {
-                        w.set_pllsai1q(q_div.into());
+                        w.set_pllq(q_div);
-                        w.set_pllsai1qen(true);
+                        w.set_pllqen(true);
-                        let freq = (src_freq / prediv.to_div() * mul.to_mul()) / q_div.to_div();
+                        let freq = src_freq / prediv * mul / q_div;
-                        if freq == 48_000_000 {
+                        if freq.0 == 48_000_000 {
                             RCC.ccipr().modify(|w| {
                                 w.set_clk48sel(0b1);
                             });
                         }
                     }
                     if let Some(p_div) = p_div {
-                        w.set_pllsai1pdiv(p_div.into());
+                        w.set_pllp(p_div);
-                        w.set_pllsai1pen(true);
+                        w.set_pllpen(true);
                     }
                 });
 
@@ -557,63 +230,67 @@ pub(crate) unsafe fn init(config: Config) {
 
     // Set flash wait states
     FLASH.acr().modify(|w| {
-        w.set_latency(if sys_clk <= 16_000_000 {
+        w.set_latency(match sys_clk.0 {
-            0b000
+            0..=16_000_000 => 0,
-        } else if sys_clk <= 32_000_000 {
+            0..=32_000_000 => 1,
-            0b001
+            0..=48_000_000 => 2,
-        } else if sys_clk <= 48_000_000 {
+            0..=64_000_000 => 3,
-            0b010
+            _ => 4,
-        } else if sys_clk <= 64_000_000 {
+        })
-            0b011
-        } else {
-            0b100
-        });
     });
 
     RCC.cfgr().modify(|w| {
         w.set_sw(sw);
-        w.set_hpre(config.ahb_pre.into());
+        w.set_hpre(config.ahb_pre);
-        w.set_ppre1(config.apb1_pre.into());
+        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre.into());
+        w.set_ppre2(config.apb2_pre);
     });
 
-    let ahb_freq: u32 = match config.ahb_pre {
+    let ahb_freq = sys_clk / config.ahb_pre;
-        AHBPrescaler::DIV1 => sys_clk,
-        pre => {
-            let pre: Hpre = pre.into();
-            let pre = 1 << (pre.to_bits() as u32 - 7);
-            sys_clk / pre
-        }
-    };
 
     let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: Ppre = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre.to_bits() - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
         }
     };
 
     let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: Ppre = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre.to_bits() - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
         }
     };
 
     set_freqs(Clocks {
-        sys: Hertz(sys_clk),
+        sys: sys_clk,
-        ahb1: Hertz(ahb_freq),
+        ahb1: ahb_freq,
-        ahb2: Hertz(ahb_freq),
+        ahb2: ahb_freq,
-        ahb3: Hertz(ahb_freq),
+        ahb3: ahb_freq,
-        apb1: Hertz(apb1_freq),
+        apb1: apb1_freq,
-        apb2: Hertz(apb2_freq),
+        apb2: apb2_freq,
-        apb1_tim: Hertz(apb1_tim_freq),
+        apb1_tim: apb1_tim_freq,
-        apb2_tim: Hertz(apb2_tim_freq),
+        apb2_tim: apb2_tim_freq,
+        rtc,
     });
 }
+
+fn msirange_to_hertz(range: Msirange) -> Hertz {
+    match range {
+        MSIRange::RANGE100K => Hertz(100_000),
+        MSIRange::RANGE200K => Hertz(200_000),
+        MSIRange::RANGE400K => Hertz(400_000),
+        MSIRange::RANGE800K => Hertz(800_000),
+        MSIRange::RANGE1M => Hertz(1_000_000),
+        MSIRange::RANGE2M => Hertz(2_000_000),
+        MSIRange::RANGE4M => Hertz(4_000_000),
+        MSIRange::RANGE8M => Hertz(8_000_000),
+        MSIRange::RANGE16M => Hertz(16_000_000),
+        MSIRange::RANGE24M => Hertz(24_000_000),
+        MSIRange::RANGE32M => Hertz(32_000_000),
+        MSIRange::RANGE48M => Hertz(48_000_000),
+        _ => unreachable!(),
+    }
+}

embassy-stm32/src/rcc/l5.rs

@@ -1,77 +1,25 @@
-use stm32_metapac::PWR;
+use crate::pac::rcc::regs::Cfgr;
-
+pub use crate::pac::rcc::vals::{
-pub use super::bus::{AHBPrescaler, APBPrescaler};
+    Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv,
-use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
+    Pllr as PllRDiv, Ppre as APBPrescaler,
-use crate::pac::{FLASH, RCC};
+};
+use crate::pac::rcc::vals::{Msirange, Pllsrc, Sw};
+use crate::pac::{FLASH, PWR, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
 
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
 /// System clock mux source
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
     MSI(MSIRange),
-    PLL(PLLSource, PLLClkDiv, PLLSrcDiv, PLLMul, Option<PLL48Div>),
+    PLL(PLLSource, PllRDiv, PllPreDiv, PllMul, Option<PllQDiv>),
     HSE(Hertz),
     HSI16,
 }
 
-/// MSI Clock Range
-///
-/// These ranges control the frequency of the MSI. Internally, these ranges map
-/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
-#[derive(Clone, Copy)]
-pub enum MSIRange {
-    /// Around 100 kHz
-    Range0,
-    /// Around 200 kHz
-    Range1,
-    /// Around 400 kHz
-    Range2,
-    /// Around 800 kHz
-    Range3,
-    /// Around 1 MHz
-    Range4,
-    /// Around 2 MHz
-    Range5,
-    /// Around 4 MHz (reset value)
-    Range6,
-    /// Around 8 MHz
-    Range7,
-    /// Around 16 MHz
-    Range8,
-    /// Around 24 MHz
-    Range9,
-    /// Around 32 MHz
-    Range10,
-    /// Around 48 MHz
-    Range11,
-}
-
-impl Default for MSIRange {
-    fn default() -> MSIRange {
-        MSIRange::Range6
-    }
-}
-
-pub type PLL48Div = PLLClkDiv;
-pub type PLLSAI1RDiv = PLLClkDiv;
-pub type PLLSAI1QDiv = PLLClkDiv;
-pub type PLLSAI1PDiv = PLLClkDiv;
-
-/// PLL divider
-#[derive(Clone, Copy)]
-pub enum PLLDiv {
-    Div2,
-    Div3,
-    Div4,
-}
-
 /// PLL clock input source
 #[derive(Clone, Copy)]
 pub enum PLLSource {
@@ -80,95 +28,6 @@ pub enum PLLSource {
     MSI(MSIRange),
 }
 
-seq_macro::seq!(N in 8..=86 {
-    #[derive(Clone, Copy)]
-    pub enum PLLMul {
-        #(
-            Mul~N,
-        )*
-    }
-
-    impl From<PLLMul> for u8 {
-        fn from(val: PLLMul) -> u8 {
-            match val {
-                #(
-                    PLLMul::Mul~N => N,
-                )*
-            }
-        }
-    }
-
-    impl PLLMul {
-        pub fn to_mul(self) -> u32 {
-            match self {
-                #(
-                    PLLMul::Mul~N => N,
-                )*
-            }
-        }
-    }
-});
-
-#[derive(Clone, Copy)]
-pub enum PLLClkDiv {
-    Div2,
-    Div4,
-    Div6,
-    Div8,
-}
-
-impl PLLClkDiv {
-    pub fn to_div(self) -> u32 {
-        let val: u8 = self.into();
-        (val as u32 + 1) * 2
-    }
-}
-
-impl From<PLLClkDiv> for u8 {
-    fn from(val: PLLClkDiv) -> u8 {
-        match val {
-            PLLClkDiv::Div2 => 0b00,
-            PLLClkDiv::Div4 => 0b01,
-            PLLClkDiv::Div6 => 0b10,
-            PLLClkDiv::Div8 => 0b11,
-        }
-    }
-}
-
-#[derive(Clone, Copy)]
-pub enum PLLSrcDiv {
-    Div1,
-    Div2,
-    Div3,
-    Div4,
-    Div5,
-    Div6,
-    Div7,
-    Div8,
-}
-
-impl PLLSrcDiv {
-    pub fn to_div(self) -> u32 {
-        let val: u8 = self.into();
-        val as u32 + 1
-    }
-}
-
-impl From<PLLSrcDiv> for u8 {
-    fn from(val: PLLSrcDiv) -> u8 {
-        match val {
-            PLLSrcDiv::Div1 => 0b000,
-            PLLSrcDiv::Div2 => 0b001,
-            PLLSrcDiv::Div3 => 0b010,
-            PLLSrcDiv::Div4 => 0b011,
-            PLLSrcDiv::Div5 => 0b100,
-            PLLSrcDiv::Div6 => 0b101,
-            PLLSrcDiv::Div7 => 0b110,
-            PLLSrcDiv::Div8 => 0b111,
-        }
-    }
-}
-
 impl From<PLLSource> for Pllsrc {
     fn from(val: PLLSource) -> Pllsrc {
         match val {
@@ -179,135 +38,116 @@ impl From<PLLSource> for Pllsrc {
     }
 }
 
-impl From<MSIRange> for Msirange {
-    fn from(val: MSIRange) -> Msirange {
-        match val {
-            MSIRange::Range0 => Msirange::RANGE100K,
-            MSIRange::Range1 => Msirange::RANGE200K,
-            MSIRange::Range2 => Msirange::RANGE400K,
-            MSIRange::Range3 => Msirange::RANGE800K,
-            MSIRange::Range4 => Msirange::RANGE1M,
-            MSIRange::Range5 => Msirange::RANGE2M,
-            MSIRange::Range6 => Msirange::RANGE4M,
-            MSIRange::Range7 => Msirange::RANGE8M,
-            MSIRange::Range8 => Msirange::RANGE16M,
-            MSIRange::Range9 => Msirange::RANGE24M,
-            MSIRange::Range10 => Msirange::RANGE32M,
-            MSIRange::Range11 => Msirange::RANGE48M,
-        }
-    }
-}
-
-impl From<MSIRange> for u32 {
-    fn from(val: MSIRange) -> u32 {
-        match val {
-            MSIRange::Range0 => 100_000,
-            MSIRange::Range1 => 200_000,
-            MSIRange::Range2 => 400_000,
-            MSIRange::Range3 => 800_000,
-            MSIRange::Range4 => 1_000_000,
-            MSIRange::Range5 => 2_000_000,
-            MSIRange::Range6 => 4_000_000,
-            MSIRange::Range7 => 8_000_000,
-            MSIRange::Range8 => 16_000_000,
-            MSIRange::Range9 => 24_000_000,
-            MSIRange::Range10 => 32_000_000,
-            MSIRange::Range11 => 48_000_000,
-        }
-    }
-}
-
 /// Clocks configutation
 pub struct Config {
     pub mux: ClockSrc,
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
-    pub pllsai1: Option<(
+    pub pllsai1: Option<(PllMul, PllPreDiv, Option<PllRDiv>, Option<PllQDiv>, Option<PllPDiv>)>,
-        PLLMul,
-        PLLSrcDiv,
-        Option<PLLSAI1RDiv>,
-        Option<PLLSAI1QDiv>,
-        Option<PLLSAI1PDiv>,
-    )>,
     pub hsi48: bool,
+    pub ls: super::LsConfig,
 }
 
 impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            mux: ClockSrc::MSI(MSIRange::Range6),
+            mux: ClockSrc::MSI(MSIRange::RANGE4M),
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
             pllsai1: None,
             hsi48: false,
+            ls: Default::default(),
         }
     }
 }
 
 pub(crate) unsafe fn init(config: Config) {
+    // Switch to MSI to prevent problems with PLL configuration.
+    if !RCC.cr().read().msion() {
+        // Turn on MSI and configure it to 4MHz.
+        RCC.cr().modify(|w| {
+            w.set_msirgsel(true); // MSI Range is provided by MSIRANGE[3:0].
+            w.set_msirange(MSIRange::RANGE4M);
+            w.set_msipllen(false);
+            w.set_msion(true)
+        });
+
+        // Wait until MSI is running
+        while !RCC.cr().read().msirdy() {}
+    }
+    if RCC.cfgr().read().sws() != Sw::MSI {
+        // Set MSI as a clock source, reset prescalers.
+        RCC.cfgr().write_value(Cfgr::default());
+        // Wait for clock switch status bits to change.
+        while RCC.cfgr().read().sws() != Sw::MSI {}
+    }
+
+    let rtc = config.ls.init();
+
     PWR.cr1().modify(|w| w.set_vos(stm32_metapac::pwr::vals::Vos::RANGE0));
     let (sys_clk, sw) = match config.mux {
         ClockSrc::MSI(range) => {
             // Enable MSI
             RCC.cr().write(|w| {
-                let bits: Msirange = range.into();
+                w.set_msirange(range);
-                w.set_msirange(bits);
-                w.set_msipllen(false);
                 w.set_msirgsel(true);
                 w.set_msion(true);
+
+                // If LSE is enabled, enable calibration of MSI
+                w.set_msipllen(config.ls.lse.is_some());
             });
             while !RCC.cr().read().msirdy() {}
 
             // Enable as clock source for USB, RNG if running at 48 MHz
-            if let MSIRange::Range11 = range {
+            if range == MSIRange::RANGE48M {
                 RCC.ccipr1().modify(|w| {
                     w.set_clk48msel(0b11);
                 });
             }
-            (range.into(), Sw::MSI)
+            (msirange_to_hertz(range), Sw::MSI)
         }
         ClockSrc::HSI16 => {
             // Enable HSI16
             RCC.cr().write(|w| w.set_hsion(true));
             while !RCC.cr().read().hsirdy() {}
 
-            (HSI_FREQ.0, Sw::HSI16)
+            (HSI_FREQ, Sw::HSI16)
         }
         ClockSrc::HSE(freq) => {
             // Enable HSE
             RCC.cr().write(|w| w.set_hseon(true));
             while !RCC.cr().read().hserdy() {}
 
-            (freq.0, Sw::HSE)
+            (freq, Sw::HSE)
         }
-        ClockSrc::PLL(src, div, prediv, mul, pll48div) => {
+        ClockSrc::PLL(src, divr, prediv, mul, divq) => {
             let src_freq = match src {
                 PLLSource::HSE(freq) => {
                     // Enable HSE
                     RCC.cr().write(|w| w.set_hseon(true));
                     while !RCC.cr().read().hserdy() {}
-                    freq.0
+                    freq
                 }
                 PLLSource::HSI16 => {
                     // Enable HSI
                     RCC.cr().write(|w| w.set_hsion(true));
                     while !RCC.cr().read().hsirdy() {}
-                    HSI_FREQ.0
+                    HSI_FREQ
                 }
                 PLLSource::MSI(range) => {
                     // Enable MSI
                     RCC.cr().write(|w| {
-                        let bits: Msirange = range.into();
+                        w.set_msirange(range);
-                        w.set_msirange(bits);
                         w.set_msipllen(false); // should be turned on if LSE is started
                         w.set_msirgsel(true);
                         w.set_msion(true);
                     });
                     while !RCC.cr().read().msirdy() {}
-                    range.into()
+
+                    msirange_to_hertz(range)
                 }
             };
 
@@ -315,23 +155,23 @@ pub(crate) unsafe fn init(config: Config) {
             RCC.cr().modify(|w| w.set_pllon(false));
             while RCC.cr().read().pllrdy() {}
 
-            let freq = (src_freq / prediv.to_div() * mul.to_mul()) / div.to_div();
+            let freq = src_freq / prediv * mul / divr;
 
             RCC.pllcfgr().write(move |w| {
-                w.set_plln(mul.into());
+                w.set_plln(mul);
-                w.set_pllm(prediv.into());
+                w.set_pllm(prediv);
-                w.set_pllr(div.into());
+                w.set_pllr(divr);
-                if let Some(pll48div) = pll48div {
+                if let Some(divq) = divq {
-                    w.set_pllq(pll48div.into());
+                    w.set_pllq(divq);
                     w.set_pllqen(true);
                 }
                 w.set_pllsrc(src.into());
             });
 
             // Enable as clock source for USB, RNG if PLL48 divisor is provided
-            if let Some(pll48div) = pll48div {
+            if let Some(divq) = divq {
-                let freq = (src_freq / prediv.to_div() * mul.to_mul()) / pll48div.to_div();
+                let freq = src_freq / prediv * mul / divq;
-                assert!(freq == 48_000_000);
+                assert!(freq.0 == 48_000_000);
                 RCC.ccipr1().modify(|w| {
                     w.set_clk48msel(0b10);
                 });
@@ -339,25 +179,25 @@ pub(crate) unsafe fn init(config: Config) {
 
             if let Some((mul, prediv, r_div, q_div, p_div)) = config.pllsai1 {
                 RCC.pllsai1cfgr().write(move |w| {
-                    w.set_pllsai1n(mul.into());
+                    w.set_plln(mul);
-                    w.set_pllsai1m(prediv.into());
+                    w.set_pllm(prediv);
                     if let Some(r_div) = r_div {
-                        w.set_pllsai1r(r_div.into());
+                        w.set_pllr(r_div);
-                        w.set_pllsai1ren(true);
+                        w.set_pllren(true);
                     }
                     if let Some(q_div) = q_div {
-                        w.set_pllsai1q(q_div.into());
+                        w.set_pllq(q_div);
-                        w.set_pllsai1qen(true);
+                        w.set_pllqen(true);
-                        let freq = (src_freq / prediv.to_div() * mul.to_mul()) / q_div.to_div();
+                        let freq = src_freq / prediv * mul / q_div;
-                        if freq == 48_000_000 {
+                        if freq.0 == 48_000_000 {
                             RCC.ccipr1().modify(|w| {
                                 w.set_clk48msel(0b1);
                             });
                         }
                     }
                     if let Some(p_div) = p_div {
-                        w.set_pllsai1pdiv(p_div.into());
+                        w.set_pllp(p_div);
-                        w.set_pllsai1pen(true);
+                        w.set_pllpen(true);
                     }
                 });
 
@@ -384,7 +224,7 @@ pub(crate) unsafe fn init(config: Config) {
     // Set flash wait states
     // VCORE Range 0 (performance), others TODO
     FLASH.acr().modify(|w| {
-        w.set_latency(match sys_clk {
+        w.set_latency(match sys_clk.0 {
             0..=20_000_000 => 0,
             0..=40_000_000 => 1,
             0..=60_000_000 => 2,
@@ -396,48 +236,56 @@ pub(crate) unsafe fn init(config: Config) {
 
     RCC.cfgr().modify(|w| {
         w.set_sw(sw);
-        w.set_hpre(config.ahb_pre.into());
+        w.set_hpre(config.ahb_pre);
-        w.set_ppre1(config.apb1_pre.into());
+        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre.into());
+        w.set_ppre2(config.apb2_pre);
     });
 
-    let ahb_freq: u32 = match config.ahb_pre {
+    let ahb_freq = sys_clk / config.ahb_pre;
-        AHBPrescaler::DIV1 => sys_clk,
-        pre => {
-            let pre: Hpre = pre.into();
-            let pre = 1 << (pre.to_bits() as u32 - 7);
-            sys_clk / pre
-        }
-    };
 
     let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: Ppre = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre.to_bits() - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
         }
     };
 
     let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: Ppre = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre.to_bits() - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
         }
     };
 
     set_freqs(Clocks {
-        sys: Hertz(sys_clk),
+        sys: sys_clk,
-        ahb1: Hertz(ahb_freq),
+        ahb1: ahb_freq,
-        ahb2: Hertz(ahb_freq),
+        ahb2: ahb_freq,
-        ahb3: Hertz(ahb_freq),
+        ahb3: ahb_freq,
-        apb1: Hertz(apb1_freq),
+        apb1: apb1_freq,
-        apb2: Hertz(apb2_freq),
+        apb2: apb2_freq,
-        apb1_tim: Hertz(apb1_tim_freq),
+        apb1_tim: apb1_tim_freq,
-        apb2_tim: Hertz(apb2_tim_freq),
+        apb2_tim: apb2_tim_freq,
+        rtc,
     });
 }
+
+fn msirange_to_hertz(range: Msirange) -> Hertz {
+    match range {
+        MSIRange::RANGE100K => Hertz(100_000),
+        MSIRange::RANGE200K => Hertz(200_000),
+        MSIRange::RANGE400K => Hertz(400_000),
+        MSIRange::RANGE800K => Hertz(800_000),
+        MSIRange::RANGE1M => Hertz(1_000_000),
+        MSIRange::RANGE2M => Hertz(2_000_000),
+        MSIRange::RANGE4M => Hertz(4_000_000),
+        MSIRange::RANGE8M => Hertz(8_000_000),
+        MSIRange::RANGE16M => Hertz(16_000_000),
+        MSIRange::RANGE24M => Hertz(24_000_000),
+        MSIRange::RANGE32M => Hertz(32_000_000),
+        MSIRange::RANGE48M => Hertz(48_000_000),
+        _ => unreachable!(),
+    }
+}

embassy-stm32/src/rcc/mco.rs

@@ -4,14 +4,19 @@ use embassy_hal_internal::into_ref;
 
 use crate::gpio::sealed::AFType;
 use crate::gpio::Speed;
-pub use crate::pac::rcc::vals::{Mco1 as Mco1Source, Mco2 as Mco2Source};
+#[cfg(not(stm32f1))]
+pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
+#[cfg(not(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7)))]
+pub use crate::pac::rcc::vals::Mcosel as McoSource;
+#[cfg(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7))]
+pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
 use crate::pac::RCC;
 use crate::{peripherals, Peripheral};
 
 pub(crate) mod sealed {
     pub trait McoInstance {
         type Source;
-        unsafe fn apply_clock_settings(source: Self::Source, prescaler: u8);
+        unsafe fn apply_clock_settings(source: Self::Source, #[cfg(not(stm32f1))] prescaler: super::McoPrescaler);
     }
 }
 
@@ -24,9 +29,15 @@ macro_rules! impl_peri {
         impl sealed::McoInstance for peripherals::$peri {
             type Source = $source;
 
-            unsafe fn apply_clock_settings(source: Self::Source, prescaler: u8) {
+            unsafe fn apply_clock_settings(source: Self::Source, #[cfg(not(stm32f1))] prescaler: McoPrescaler) {
-                RCC.cfgr().modify(|w| {
+                #[cfg(not(any(stm32u5, stm32wba)))]
+                let r = RCC.cfgr();
+                #[cfg(any(stm32u5, stm32wba))]
+                let r = RCC.cfgr1();
+
+                r.modify(|w| {
                     w.$set_source(source);
+                    #[cfg(not(stm32f1))]
                     w.$set_prescaler(prescaler);
                 });
             }
@@ -36,8 +47,16 @@ macro_rules! impl_peri {
     };
 }
 
-impl_peri!(MCO1, Mco1Source, set_mco1, set_mco1pre);
+#[cfg(any(rcc_c0, rcc_g0))]
-impl_peri!(MCO2, Mco2Source, set_mco2, set_mco2pre);
+#[allow(unused_imports)]
+use self::{McoSource as Mco1Source, McoSource as Mco2Source};
+
+#[cfg(mco)]
+impl_peri!(MCO, McoSource, set_mcosel, set_mcopre);
+#[cfg(mco1)]
+impl_peri!(MCO1, Mco1Source, set_mco1sel, set_mco1pre);
+#[cfg(mco2)]
+impl_peri!(MCO2, Mco2Source, set_mco2sel, set_mco2pre);
 
 pub struct Mco<'d, T: McoInstance> {
     phantom: PhantomData<&'d mut T>,
@@ -45,23 +64,20 @@ pub struct Mco<'d, T: McoInstance> {
 
 impl<'d, T: McoInstance> Mco<'d, T> {
     /// Create a new MCO instance.
-    ///
-    /// `prescaler` must be between 1 and 15.
     pub fn new(
         _peri: impl Peripheral<P = T> + 'd,
         pin: impl Peripheral<P = impl McoPin<T>> + 'd,
         source: T::Source,
-        prescaler: u8,
+        #[cfg(not(stm32f1))] prescaler: McoPrescaler,
     ) -> Self {
         into_ref!(pin);
 
-        assert!(
-            1 <= prescaler && prescaler <= 15,
-            "Mco prescaler must be between 1 and 15. Refer to the reference manual for more information."
-        );
-
         critical_section::with(|_| unsafe {
-            T::apply_clock_settings(source, prescaler);
+            T::apply_clock_settings(
+                source,
+                #[cfg(not(stm32f1))]
+                prescaler,
+            );
             pin.set_as_af(pin.af_num(), AFType::OutputPushPull);
             pin.set_speed(Speed::VeryHigh);
         });

embassy-stm32/src/rcc/mod.rs

@@ -2,14 +2,11 @@
 
 use core::mem::MaybeUninit;
 
-pub use crate::rcc::bd::RtcClockSource;
 use crate::time::Hertz;
 
-pub(crate) mod bd;
+mod bd;
-mod bus;
-#[cfg(any(stm32h5, stm32h7))]
 mod mco;
-#[cfg(any(stm32h5, stm32h7))]
+pub use bd::*;
 pub use mco::*;
 
 #[cfg_attr(rcc_f0, path = "f0.rs")]
@@ -21,9 +18,8 @@ pub use mco::*;
 #[cfg_attr(rcc_c0, path = "c0.rs")]
 #[cfg_attr(rcc_g0, path = "g0.rs")]
 #[cfg_attr(rcc_g4, path = "g4.rs")]
-#[cfg_attr(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab), path = "h.rs")]
+#[cfg_attr(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab), path = "h.rs")]
-#[cfg_attr(rcc_l0, path = "l0.rs")]
+#[cfg_attr(any(rcc_l0, rcc_l0_v2, rcc_l1), path = "l0l1.rs")]
-#[cfg_attr(rcc_l1, path = "l1.rs")]
 #[cfg_attr(rcc_l4, path = "l4.rs")]
 #[cfg_attr(rcc_l5, path = "l5.rs")]
 #[cfg_attr(rcc_u5, path = "u5.rs")]
@@ -57,9 +53,9 @@ pub struct Clocks {
     pub apb2: Hertz,
     #[cfg(not(any(rcc_c0, rcc_g0)))]
     pub apb2_tim: Hertz,
-    #[cfg(any(rcc_wl5, rcc_wle, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_u5))]
+    #[cfg(any(rcc_wl5, rcc_wle, rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_u5))]
     pub apb3: Hertz,
-    #[cfg(any(rcc_h7, rcc_h7ab))]
+    #[cfg(any(rcc_h7, rcc_h7rm0433, rcc_h7ab))]
     pub apb4: Hertz,
     #[cfg(any(rcc_wba))]
     pub apb7: Hertz,
@@ -67,16 +63,44 @@ pub struct Clocks {
     // AHB
     pub ahb1: Hertz,
     #[cfg(any(
-        rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb,
+        rcc_l4,
-        rcc_wba, rcc_wl5, rcc_wle
+        rcc_l5,
+        rcc_f2,
+        rcc_f4,
+        rcc_f410,
+        rcc_f7,
+        rcc_h5,
+        rcc_h50,
+        rcc_h7,
+        rcc_h7rm0433,
+        rcc_h7ab,
+        rcc_g4,
+        rcc_u5,
+        rcc_wb,
+        rcc_wba,
+        rcc_wl5,
+        rcc_wle
     ))]
     pub ahb2: Hertz,
     #[cfg(any(
-        rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb, rcc_wl5,
+        rcc_l4,
+        rcc_l5,
+        rcc_f2,
+        rcc_f4,
+        rcc_f410,
+        rcc_f7,
+        rcc_h5,
+        rcc_h50,
+        rcc_h7,
+        rcc_h7rm0433,
+        rcc_h7ab,
+        rcc_u5,
+        rcc_wb,
+        rcc_wl5,
         rcc_wle
     ))]
     pub ahb3: Hertz,
-    #[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_wba))]
+    #[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_wba))]
     pub ahb4: Hertz,
 
     #[cfg(any(rcc_f2, rcc_f4, rcc_f410, rcc_f7))]
@@ -88,7 +112,18 @@ pub struct Clocks {
     #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
     pub pllsai: Option<Hertz>,
 
-    #[cfg(any(rcc_f1, rcc_f100, rcc_f1cl, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_f3, rcc_g4))]
+    #[cfg(any(
+        rcc_f1,
+        rcc_f100,
+        rcc_f1cl,
+        rcc_h5,
+        rcc_h50,
+        rcc_h7,
+        rcc_h7rm0433,
+        rcc_h7ab,
+        rcc_f3,
+        rcc_g4
+    ))]
     pub adc: Option<Hertz>,
 
     #[cfg(any(rcc_f3, rcc_g4))]
@@ -97,13 +132,7 @@ pub struct Clocks {
     #[cfg(stm32f334)]
     pub hrtim: Option<Hertz>,
 
-    #[cfg(any(rcc_wb, rcc_f4, rcc_f410, rcc_f7))]
-    /// Set only if the lsi or lse is configured, indicates stop is supported
     pub rtc: Option<Hertz>,
-
-    #[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
-    /// Set if the hse is configured, indicates stop is not supported
-    pub rtc_hse: Option<Hertz>,
 }
 
 #[cfg(feature = "low-power")]
@@ -131,14 +160,6 @@ pub(crate) fn clock_refcount_sub() {
 /// The existence of this value indicates that the clock configuration can no longer be changed
 static mut CLOCK_FREQS: MaybeUninit<Clocks> = MaybeUninit::uninit();
 
-#[cfg(stm32wb)]
-/// RCC initialization function
-pub(crate) unsafe fn init(config: Config) {
-    set_freqs(compute_clocks(&config));
-
-    configure_clocks(&config);
-}
-
 /// Sets the clock frequencies
 ///
 /// Safety: Sets a mutable global.

embassy-stm32/src/rcc/u5.rs

@@ -1,124 +1,102 @@
-use stm32_metapac::rcc::vals::{Msirange, Msirgsel, Pllm, Pllsrc, Sw};
+pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange, Plldiv, Pllm, Plln, Ppre as APBPrescaler};
-
+use crate::pac::rcc::vals::{Msirgsel, Pllmboost, Pllrge, Pllsrc, Sw};
-pub use super::bus::{AHBPrescaler, APBPrescaler};
+use crate::pac::{FLASH, PWR, RCC};
-use crate::pac::{FLASH, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
 
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
 
 #[derive(Copy, Clone)]
 pub enum ClockSrc {
-    MSI(MSIRange),
+    /// Use an internal medium speed oscillator (MSIS) as the system clock.
+    MSI(Msirange),
+    /// Use the external high speed clock as the system clock.
+    ///
+    /// HSE clocks faster than 25 MHz require at least `VoltageScale::RANGE3`, and HSE clocks must
+    /// never exceed 50 MHz.
     HSE(Hertz),
+    /// Use the 16 MHz internal high speed oscillator as the system clock.
     HSI16,
-    PLL1R(PllSrc, PllM, PllN, PllClkDiv),
+    /// Use PLL1 as the system clock.
+    PLL1R(PllConfig),
 }
 
-#[derive(Clone, Copy, Debug)]
+impl Default for ClockSrc {
+    fn default() -> Self {
+        // The default system clock source is MSIS @ 4 MHz, per RM0456 § 11.4.9
+        ClockSrc::MSI(Msirange::RANGE_4MHZ)
+    }
+}
+
+#[derive(Clone, Copy)]
+pub struct PllConfig {
+    /// The clock source for the PLL.
+    pub source: PllSrc,
+    /// The PLL prescaler.
+    ///
+    /// The clock speed of the `source` divided by `m` must be between 4 and 16 MHz.
+    pub m: Pllm,
+    /// The PLL multiplier.
+    ///
+    /// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
+    /// MHz. The upper limit may be lower depending on the `Config { voltage_range }`.
+    pub n: Plln,
+    /// The divider for the R output.
+    ///
+    /// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
+    /// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
+    /// `Config { voltage_range }`.
+    pub r: Plldiv,
+}
+
+impl PllConfig {
+    /// A configuration for HSI16 / 1 * 10 / 1 = 160 MHz
+    pub const fn hsi16_160mhz() -> Self {
+        PllConfig {
+            source: PllSrc::HSI16,
+            m: Pllm::DIV1,
+            n: Plln::MUL10,
+            r: Plldiv::DIV1,
+        }
+    }
+
+    /// A configuration for MSIS @ 48 MHz / 3 * 10 / 1 = 160 MHz
+    pub const fn msis_160mhz() -> Self {
+        PllConfig {
+            source: PllSrc::MSIS(Msirange::RANGE_48MHZ),
+            m: Pllm::DIV3,
+            n: Plln::MUL10,
+            r: Plldiv::DIV1,
+        }
+    }
+}
+
+#[derive(Clone, Copy)]
 pub enum PllSrc {
-    MSI(MSIRange),
+    /// Use an internal medium speed oscillator as the PLL source.
+    MSIS(Msirange),
+    /// Use the external high speed clock as the system PLL source.
+    ///
+    /// HSE clocks faster than 25 MHz require at least `VoltageScale::RANGE3`, and HSE clocks must
+    /// never exceed 50 MHz.
     HSE(Hertz),
+    /// Use the 16 MHz internal high speed oscillator as the PLL source.
     HSI16,
 }
 
 impl Into<Pllsrc> for PllSrc {
     fn into(self) -> Pllsrc {
         match self {
-            PllSrc::MSI(..) => Pllsrc::MSIS,
+            PllSrc::MSIS(..) => Pllsrc::MSIS,
             PllSrc::HSE(..) => Pllsrc::HSE,
             PllSrc::HSI16 => Pllsrc::HSI16,
         }
     }
 }
 
-seq_macro::seq!(N in 2..=128 {
-    #[derive(Copy, Clone, Debug)]
-    pub enum PllClkDiv {
-        NotDivided,
-        #(
-            Div~N = (N-1),
-        )*
-    }
-
-    impl PllClkDiv {
-        fn to_div(&self) -> u8 {
-            match self {
-                PllClkDiv::NotDivided => 1,
-                #(
-                    PllClkDiv::Div~N => N + 1,
-                )*
-            }
-        }
-    }
-});
-
-impl Into<u8> for PllClkDiv {
-    fn into(self) -> u8 {
-        (self as u8) + 1
-    }
-}
-
-seq_macro::seq!(N in 4..=512 {
-    #[derive(Copy, Clone, Debug)]
-    pub enum PllN {
-        NotMultiplied,
-        #(
-            Mul~N = N-1,
-        )*
-    }
-
-    impl PllN {
-        fn to_mul(&self) -> u16 {
-            match self {
-                PllN::NotMultiplied => 1,
-                #(
-                    PllN::Mul~N => N + 1,
-                )*
-            }
-        }
-    }
-});
-
-impl Into<u16> for PllN {
-    fn into(self) -> u16 {
-        (self as u16) + 1
-    }
-}
-
-// Pre-division
-#[derive(Copy, Clone, Debug)]
-pub enum PllM {
-    NotDivided = 0b0000,
-    Div2 = 0b0001,
-    Div3 = 0b0010,
-    Div4 = 0b0011,
-    Div5 = 0b0100,
-    Div6 = 0b0101,
-    Div7 = 0b0110,
-    Div8 = 0b0111,
-    Div9 = 0b1000,
-    Div10 = 0b1001,
-    Div11 = 0b1010,
-    Div12 = 0b1011,
-    Div13 = 0b1100,
-    Div14 = 0b1101,
-    Div15 = 0b1110,
-    Div16 = 0b1111,
-}
-
-impl Into<Pllm> for PllM {
-    fn into(self) -> Pllm {
-        Pllm::from_bits(self as u8)
-    }
-}
-
 impl Into<Sw> for ClockSrc {
     fn into(self) -> Sw {
         match self {
@@ -130,62 +108,6 @@ impl Into<Sw> for ClockSrc {
     }
 }
 
-#[derive(Debug, Copy, Clone)]
-pub enum MSIRange {
-    Range48mhz = 48_000_000,
-    Range24mhz = 24_000_000,
-    Range16mhz = 16_000_000,
-    Range12mhz = 12_000_000,
-    Range4mhz = 4_000_000,
-    Range2mhz = 2_000_000,
-    Range1_33mhz = 1_330_000,
-    Range1mhz = 1_000_000,
-    Range3_072mhz = 3_072_000,
-    Range1_536mhz = 1_536_000,
-    Range1_024mhz = 1_024_000,
-    Range768khz = 768_000,
-    Range400khz = 400_000,
-    Range200khz = 200_000,
-    Range133khz = 133_000,
-    Range100khz = 100_000,
-}
-
-impl Into<u32> for MSIRange {
-    fn into(self) -> u32 {
-        self as u32
-    }
-}
-
-impl Into<Msirange> for MSIRange {
-    fn into(self) -> Msirange {
-        match self {
-            MSIRange::Range48mhz => Msirange::RANGE_48MHZ,
-            MSIRange::Range24mhz => Msirange::RANGE_24MHZ,
-            MSIRange::Range16mhz => Msirange::RANGE_16MHZ,
-            MSIRange::Range12mhz => Msirange::RANGE_12MHZ,
-            MSIRange::Range4mhz => Msirange::RANGE_4MHZ,
-            MSIRange::Range2mhz => Msirange::RANGE_2MHZ,
-            MSIRange::Range1_33mhz => Msirange::RANGE_1_33MHZ,
-            MSIRange::Range1mhz => Msirange::RANGE_1MHZ,
-            MSIRange::Range3_072mhz => Msirange::RANGE_3_072MHZ,
-            MSIRange::Range1_536mhz => Msirange::RANGE_1_536MHZ,
-            MSIRange::Range1_024mhz => Msirange::RANGE_1_024MHZ,
-            MSIRange::Range768khz => Msirange::RANGE_768KHZ,
-            MSIRange::Range400khz => Msirange::RANGE_400KHZ,
-            MSIRange::Range200khz => Msirange::RANGE_200KHZ,
-            MSIRange::Range133khz => Msirange::RANGE_133KHZ,
-            MSIRange::Range100khz => Msirange::RANGE_100KHZ,
-        }
-    }
-}
-
-impl Default for MSIRange {
-    fn default() -> Self {
-        MSIRange::Range4mhz
-    }
-}
-
-#[derive(Copy, Clone)]
 pub struct Config {
     pub mux: ClockSrc,
     pub ahb_pre: AHBPrescaler,
@@ -193,90 +115,209 @@ pub struct Config {
     pub apb2_pre: APBPrescaler,
     pub apb3_pre: APBPrescaler,
     pub hsi48: bool,
+    /// The voltage range influences the maximum clock frequencies for different parts of the
+    /// device. In particular, system clocks exceeding 110 MHz require `RANGE1`, and system clocks
+    /// exceeding 55 MHz require at least `RANGE2`.
+    ///
+    /// See RM0456 § 10.5.4 for a general overview and § 11.4.10 for clock source frequency limits.
+    pub voltage_range: VoltageScale,
+    pub ls: super::LsConfig,
+}
+
+impl Config {
+    unsafe fn init_hsi16(&self) -> Hertz {
+        RCC.cr().write(|w| w.set_hsion(true));
+        while !RCC.cr().read().hsirdy() {}
+
+        HSI_FREQ
+    }
+
+    unsafe fn init_hse(&self, frequency: Hertz) -> Hertz {
+        // Check frequency limits per RM456 § 11.4.10
+        match self.voltage_range {
+            VoltageScale::RANGE1 | VoltageScale::RANGE2 | VoltageScale::RANGE3 => {
+                assert!(frequency.0 <= 50_000_000);
+            }
+            VoltageScale::RANGE4 => {
+                assert!(frequency.0 <= 25_000_000);
+            }
+        }
+
+        // Enable HSE, and wait for it to stabilize
+        RCC.cr().write(|w| w.set_hseon(true));
+        while !RCC.cr().read().hserdy() {}
+
+        frequency
+    }
+
+    unsafe fn init_msis(&self, range: Msirange) -> Hertz {
+        // Check MSI output per RM0456 § 11.4.10
+        match self.voltage_range {
+            VoltageScale::RANGE4 => {
+                assert!(msirange_to_hertz(range).0 <= 24_000_000);
+            }
+            _ => {}
+        }
+
+        // RM0456 § 11.8.2: spin until MSIS is off or MSIS is ready before setting its range
+        loop {
+            let cr = RCC.cr().read();
+            if cr.msison() == false || cr.msisrdy() == true {
+                break;
+            }
+        }
+
+        RCC.icscr1().modify(|w| {
+            w.set_msisrange(range);
+            w.set_msirgsel(Msirgsel::RCC_ICSCR1);
+        });
+        RCC.cr().write(|w| {
+            w.set_msipllen(false);
+            w.set_msison(true);
+        });
+        while !RCC.cr().read().msisrdy() {}
+        msirange_to_hertz(range)
+    }
 }
 
 impl Default for Config {
     fn default() -> Self {
         Self {
-            mux: ClockSrc::MSI(MSIRange::default()),
+            mux: ClockSrc::default(),
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
             apb3_pre: APBPrescaler::DIV1,
             hsi48: false,
+            voltage_range: VoltageScale::RANGE3,
+            ls: Default::default(),
         }
     }
 }
 
 pub(crate) unsafe fn init(config: Config) {
+    // Ensure PWR peripheral clock is enabled
+    RCC.ahb3enr().modify(|w| {
+        w.set_pwren(true);
+    });
+    RCC.ahb3enr().read(); // synchronize
+
+    // Set the requested power mode
+    PWR.vosr().modify(|w| {
+        w.set_vos(config.voltage_range);
+    });
+    while !PWR.vosr().read().vosrdy() {}
+
     let sys_clk = match config.mux {
-        ClockSrc::MSI(range) => {
+        ClockSrc::MSI(range) => config.init_msis(range),
-            RCC.icscr1().modify(|w| {
+        ClockSrc::HSE(freq) => config.init_hse(freq),
-                let bits: Msirange = range.into();
+        ClockSrc::HSI16 => config.init_hsi16(),
-                w.set_msisrange(bits);
+        ClockSrc::PLL1R(pll) => {
-                w.set_msirgsel(Msirgsel::RCC_ICSCR1);
+            // Configure the PLL source
-            });
+            let source_clk = match pll.source {
-            RCC.cr().write(|w| {
+                PllSrc::MSIS(range) => config.init_msis(range),
-                w.set_msipllen(false);
+                PllSrc::HSE(hertz) => config.init_hse(hertz),
-                w.set_msison(true);
+                PllSrc::HSI16 => config.init_hsi16(),
-            });
-            while !RCC.cr().read().msisrdy() {}
-
-            range.into()
-        }
-        ClockSrc::HSE(freq) => {
-            RCC.cr().write(|w| w.set_hseon(true));
-            while !RCC.cr().read().hserdy() {}
-
-            freq.0
-        }
-        ClockSrc::HSI16 => {
-            RCC.cr().write(|w| w.set_hsion(true));
-            while !RCC.cr().read().hsirdy() {}
-
-            HSI_FREQ.0
-        }
-        ClockSrc::PLL1R(src, m, n, div) => {
-            let freq = match src {
-                PllSrc::MSI(_) => {
-                    // TODO: enable MSI
-                    MSIRange::default().into()
-                }
-                PllSrc::HSE(hertz) => {
-                    // TODO: enable HSE
-                    hertz.0
-                }
-                PllSrc::HSI16 => {
-                    RCC.cr().write(|w| w.set_hsion(true));
-                    while !RCC.cr().read().hsirdy() {}
-
-                    HSI_FREQ.0
-                }
             };
 
-            // disable
+            // Calculate the reference clock, which is the source divided by m
+            let reference_clk = source_clk / pll.m;
+
+            // Check limits per RM0456 § 11.4.6
+            assert!(Hertz::mhz(4) <= reference_clk && reference_clk <= Hertz::mhz(16));
+
+            // Calculate the PLL1 VCO clock and PLL1 R output clock
+            let pll1_clk = reference_clk * pll.n;
+            let pll1r_clk = pll1_clk / pll.r;
+
+            // Check system clock per RM0456 § 11.4.9
+            assert!(pll1r_clk <= Hertz::mhz(160));
+
+            // Check PLL clocks per RM0456 § 11.4.10
+            match config.voltage_range {
+                VoltageScale::RANGE1 => {
+                    assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(544));
+                    assert!(pll1r_clk <= Hertz::mhz(208));
+                }
+                VoltageScale::RANGE2 => {
+                    assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(544));
+                    assert!(pll1r_clk <= Hertz::mhz(110));
+                }
+                VoltageScale::RANGE3 => {
+                    assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(330));
+                    assert!(pll1r_clk <= Hertz::mhz(55));
+                }
+                VoltageScale::RANGE4 => {
+                    panic!("PLL is unavailable in voltage range 4");
+                }
+            }
+
+            // § 10.5.4: if we're targeting >= 55 MHz, we must configure PLL1MBOOST to a prescaler
+            // value that results in an output between 4 and 16 MHz for the PWR EPOD boost
+            let mboost = if pll1r_clk >= Hertz::mhz(55) {
+                // source_clk can be up to 50 MHz, so there's just a few cases:
+                if source_clk > Hertz::mhz(32) {
+                    // Divide by 4, giving EPOD 8-12.5 MHz
+                    Pllmboost::DIV4
+                } else if source_clk > Hertz::mhz(16) {
+                    // Divide by 2, giving EPOD 8-16 MHz
+                    Pllmboost::DIV2
+                } else {
+                    // Bypass, giving EPOD 4-16 MHz
+                    Pllmboost::DIV1
+                }
+            } else {
+                // Nothing to do
+                Pllmboost::DIV1
+            };
+
+            // Disable the PLL, and wait for it to disable
             RCC.cr().modify(|w| w.set_pllon(0, false));
             while RCC.cr().read().pllrdy(0) {}
 
-            let vco = freq * n as u8 as u32;
+            // Configure the PLL
-            let pll_ck = vco / (div as u8 as u32 + 1);
-
             RCC.pll1cfgr().write(|w| {
-                w.set_pllm(m.into());
+                // Configure PLL1 source and prescaler
-                w.set_pllsrc(src.into());
+                w.set_pllsrc(pll.source.into());
+                w.set_pllm(pll.m);
+
+                // Configure PLL1 input frequncy range
+                let input_range = if reference_clk <= Hertz::mhz(8) {
+                    Pllrge::FREQ_4TO8MHZ
+                } else {
+                    Pllrge::FREQ_8TO16MHZ
+                };
+                w.set_pllrge(input_range);
+
+                // Set the prescaler for PWR EPOD
+                w.set_pllmboost(mboost);
+
+                // Enable PLL1R output
                 w.set_pllren(true);
             });
 
+            // Configure the PLL divisors
             RCC.pll1divr().modify(|w| {
-                w.set_pllr(div.to_div());
+                // Set the VCO multiplier
-                w.set_plln(n.to_mul());
+                w.set_plln(pll.n);
+                // Set the R output divisor
+                w.set_pllr(pll.r);
             });
 
-            // Enable PLL
+            // Do we need the EPOD booster to reach the target clock speed per § 10.5.4?
+            if pll1r_clk >= Hertz::mhz(55) {
+                // Enable the booster
+                PWR.vosr().modify(|w| {
+                    w.set_boosten(true);
+                });
+                while !PWR.vosr().read().boostrdy() {}
+            }
+
+            // Enable the PLL
             RCC.cr().modify(|w| w.set_pllon(0, true));
             while !RCC.cr().read().pllrdy(0) {}
 
-            pll_ck
+            pll1r_clk
         }
     };
 
@@ -285,20 +326,18 @@ pub(crate) unsafe fn init(config: Config) {
         while !RCC.cr().read().hsi48rdy() {}
     }
 
-    // TODO make configurable
+    // The clock source is ready
-    let power_vos = VoltageScale::RANGE3;
+    // Calculate and set the flash wait states
-
+    let wait_states = match config.voltage_range {
-    // states and programming delay
-    let wait_states = match power_vos {
         // VOS 1 range VCORE 1.26V - 1.40V
         VoltageScale::RANGE1 => {
-            if sys_clk < 32_000_000 {
+            if sys_clk.0 < 32_000_000 {
                 0
-            } else if sys_clk < 64_000_000 {
+            } else if sys_clk.0 < 64_000_000 {
                 1
-            } else if sys_clk < 96_000_000 {
+            } else if sys_clk.0 < 96_000_000 {
                 2
-            } else if sys_clk < 128_000_000 {
+            } else if sys_clk.0 < 128_000_000 {
                 3
             } else {
                 4
@@ -306,11 +345,11 @@ pub(crate) unsafe fn init(config: Config) {
         }
         // VOS 2 range VCORE 1.15V - 1.26V
         VoltageScale::RANGE2 => {
-            if sys_clk < 30_000_000 {
+            if sys_clk.0 < 30_000_000 {
                 0
-            } else if sys_clk < 60_000_000 {
+            } else if sys_clk.0 < 60_000_000 {
                 1
-            } else if sys_clk < 90_000_000 {
+            } else if sys_clk.0 < 90_000_000 {
                 2
             } else {
                 3
@@ -318,9 +357,9 @@ pub(crate) unsafe fn init(config: Config) {
         }
         // VOS 3 range VCORE 1.05V - 1.15V
         VoltageScale::RANGE3 => {
-            if sys_clk < 24_000_000 {
+            if sys_clk.0 < 24_000_000 {
                 0
-            } else if sys_clk < 48_000_000 {
+            } else if sys_clk.0 < 48_000_000 {
                 1
             } else {
                 2
@@ -328,80 +367,104 @@ pub(crate) unsafe fn init(config: Config) {
         }
         // VOS 4 range VCORE 0.95V - 1.05V
         VoltageScale::RANGE4 => {
-            if sys_clk < 12_000_000 {
+            if sys_clk.0 < 12_000_000 {
                 0
             } else {
                 1
             }
         }
     };
-
     FLASH.acr().modify(|w| {
         w.set_latency(wait_states);
     });
 
+    // Switch the system clock source
     RCC.cfgr1().modify(|w| {
         w.set_sw(config.mux.into());
     });
 
+    // RM0456 § 11.4.9 specifies maximum bus frequencies per voltage range, but the maximum bus
+    // frequency for each voltage range exactly matches the maximum permitted PLL output frequency.
+    // Given that:
+    //
+    //   1. Any bus frequency can never exceed the system clock frequency;
+    //   2. We checked the PLL output frequency if we're using it as a system clock;
+    //   3. The maximum HSE frequencies at each voltage range are lower than the bus limits, and
+    //      we checked the HSE frequency if configured as a system clock; and
+    //   4. The maximum frequencies from the other clock sources are lower than the lowest bus
+    //      frequency limit
+    //
+    // ...then we do not need to perform additional bus-related frequency checks.
+
+    // Configure the bus prescalers
     RCC.cfgr2().modify(|w| {
-        w.set_hpre(config.ahb_pre.into());
+        w.set_hpre(config.ahb_pre);
-        w.set_ppre1(config.apb1_pre.into());
+        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre.into());
+        w.set_ppre2(config.apb2_pre);
     });
-
     RCC.cfgr3().modify(|w| {
-        w.set_ppre3(config.apb3_pre.into());
+        w.set_ppre3(config.apb3_pre);
     });
 
-    let ahb_freq: u32 = match config.ahb_pre {
+    let ahb_freq = sys_clk / config.ahb_pre;
-        AHBPrescaler::DIV1 => sys_clk,
-        pre => {
-            let pre: u8 = pre.into();
-            let pre = 1 << (pre as u32 - 7);
-            sys_clk / pre
-        }
-    };
 
     let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: u8 = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
         }
     };
 
     let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: u8 = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
         }
     };
 
     let (apb3_freq, _apb3_tim_freq) = match config.apb3_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: u8 = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
         }
     };
 
+    let rtc = config.ls.init();
+
     set_freqs(Clocks {
-        sys: Hertz(sys_clk),
+        sys: sys_clk,
-        ahb1: Hertz(ahb_freq),
+        ahb1: ahb_freq,
-        ahb2: Hertz(ahb_freq),
+        ahb2: ahb_freq,
-        ahb3: Hertz(ahb_freq),
+        ahb3: ahb_freq,
-        apb1: Hertz(apb1_freq),
+        apb1: apb1_freq,
-        apb2: Hertz(apb2_freq),
+        apb2: apb2_freq,
-        apb3: Hertz(apb3_freq),
+        apb3: apb3_freq,
-        apb1_tim: Hertz(apb1_tim_freq),
+        apb1_tim: apb1_tim_freq,
-        apb2_tim: Hertz(apb2_tim_freq),
+        apb2_tim: apb2_tim_freq,
+        rtc,
     });
 }
+
+fn msirange_to_hertz(range: Msirange) -> Hertz {
+    match range {
+        Msirange::RANGE_48MHZ => Hertz(48_000_000),
+        Msirange::RANGE_24MHZ => Hertz(24_000_000),
+        Msirange::RANGE_16MHZ => Hertz(16_000_000),
+        Msirange::RANGE_12MHZ => Hertz(12_000_000),
+        Msirange::RANGE_4MHZ => Hertz(4_000_000),
+        Msirange::RANGE_2MHZ => Hertz(2_000_000),
+        Msirange::RANGE_1_33MHZ => Hertz(1_330_000),
+        Msirange::RANGE_1MHZ => Hertz(1_000_000),
+        Msirange::RANGE_3_072MHZ => Hertz(3_072_000),
+        Msirange::RANGE_1_536MHZ => Hertz(1_536_000),
+        Msirange::RANGE_1_024MHZ => Hertz(1_024_000),
+        Msirange::RANGE_768KHZ => Hertz(768_000),
+        Msirange::RANGE_400KHZ => Hertz(400_000),
+        Msirange::RANGE_200KHZ => Hertz(200_000),
+        Msirange::RANGE_133KHZ => Hertz(133_000),
+        Msirange::RANGE_100KHZ => Hertz(100_000),
+    }
+}

embassy-stm32/src/rcc/wb.rs

@@ -1,118 +1,45 @@
-pub use super::bus::{AHBPrescaler, APBPrescaler};
+pub use crate::pac::rcc::vals::{
-use crate::rcc::bd::{BackupDomain, RtcClockSource};
+    Hpre as AHBPrescaler, Hsepre as HsePrescaler, Pllm, Plln, Pllp, Pllq, Pllr, Pllsrc as PllSource,
-use crate::rcc::Clocks;
+    Ppre as APBPrescaler, Sw as Sysclk,
-use crate::time::{khz, mhz, Hertz};
+};
-
+use crate::rcc::{set_freqs, Clocks};
-/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
+use crate::time::{mhz, Hertz};
-/// and with the addition of the init function to configure a system clock.
-
-/// Only the basic setup using the HSE and HSI clocks are supported as of now.
 
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
-#[derive(Clone, Copy)]
-pub enum HsePrescaler {
-    NotDivided,
-    Div2,
-}
-
-impl From<HsePrescaler> for bool {
-    fn from(value: HsePrescaler) -> Self {
-        match value {
-            HsePrescaler::NotDivided => false,
-            HsePrescaler::Div2 => true,
-        }
-    }
-}
-
 pub struct Hse {
     pub prediv: HsePrescaler,
 
     pub frequency: Hertz,
 }
 
-/// System clock mux source
-#[derive(Clone, Copy, PartialEq)]
-pub enum Sysclk {
-    /// MSI selected as sysclk
-    MSI,
-    /// HSI selected as sysclk
-    HSI,
-    /// HSE selected as sysclk
-    HSE,
-    /// PLL selected as sysclk
-    Pll,
-}
-
-impl From<Sysclk> for u8 {
-    fn from(value: Sysclk) -> Self {
-        match value {
-            Sysclk::MSI => 0b00,
-            Sysclk::HSI => 0b01,
-            Sysclk::HSE => 0b10,
-            Sysclk::Pll => 0b11,
-        }
-    }
-}
-
-#[derive(Clone, Copy, PartialEq)]
-pub enum PllSource {
-    Hsi,
-    Msi,
-    Hse,
-}
-
-impl From<PllSource> for u8 {
-    fn from(value: PllSource) -> Self {
-        match value {
-            PllSource::Msi => 0b01,
-            PllSource::Hsi => 0b10,
-            PllSource::Hse => 0b11,
-        }
-    }
-}
-
-pub enum Pll48Source {
-    PllSai,
-    Pll,
-    Msi,
-    Hsi48,
-}
-
 pub struct PllMux {
     /// Source clock selection.
     pub source: PllSource,
 
     /// PLL pre-divider (DIVM). Must be between 1 and 63.
-    pub prediv: u8,
+    pub prediv: Pllm,
 }
 
 pub struct Pll {
     /// PLL multiplication factor. Must be between 4 and 512.
-    pub mul: u16,
+    pub mul: Plln,
 
     /// PLL P division factor. If None, PLL P output is disabled. Must be between 1 and 128.
     /// On PLL1, it must be even (in particular, it cannot be 1.)
-    pub divp: Option<u16>,
+    pub divp: Option<Pllp>,
     /// PLL Q division factor. If None, PLL Q output is disabled. Must be between 1 and 128.
-    pub divq: Option<u16>,
+    pub divq: Option<Pllq>,
     /// PLL R division factor. If None, PLL R output is disabled. Must be between 1 and 128.
-    pub divr: Option<u16>,
+    pub divr: Option<Pllr>,
 }
 
 /// Clocks configutation
 pub struct Config {
     pub hse: Option<Hse>,
-    pub lse: Option<Hertz>,
-    pub lsi: bool,
     pub sys: Sysclk,
     pub mux: Option<PllMux>,
-    pub pll48: Option<Pll48Source>,
-    pub rtc: Option<RtcClockSource>,
 
     pub pll: Option<Pll>,
     pub pllsai: Option<Pll>,
@@ -122,28 +49,28 @@ pub struct Config {
     pub ahb3_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
+
+    pub ls: super::LsConfig,
 }
 
 pub const WPAN_DEFAULT: Config = Config {
     hse: Some(Hse {
         frequency: mhz(32),
-        prediv: HsePrescaler::NotDivided,
+        prediv: HsePrescaler::DIV1,
     }),
-    lse: Some(khz(32)),
+    sys: Sysclk::PLL,
-    sys: Sysclk::Pll,
     mux: Some(PllMux {
-        source: PllSource::Hse,
+        source: PllSource::HSE,
-        prediv: 2,
+        prediv: Pllm::DIV2,
     }),
-    pll48: None,
+
-    rtc: Some(RtcClockSource::LSE),
+    ls: super::LsConfig::default_lse(),
-    lsi: false,
 
     pll: Some(Pll {
-        mul: 12,
+        mul: Plln::MUL12,
-        divp: Some(3),
+        divp: Some(Pllp::DIV3),
-        divq: Some(4),
+        divq: Some(Pllq::DIV4),
-        divr: Some(3),
+        divr: Some(Pllr::DIV3),
     }),
     pllsai: None,
 
@@ -159,14 +86,12 @@ impl Default for Config {
     fn default() -> Config {
         Config {
             hse: None,
-            lse: None,
+            sys: Sysclk::HSI16,
-            sys: Sysclk::HSI,
             mux: None,
-            pll48: None,
             pll: None,
             pllsai: None,
-            rtc: None,
+
-            lsi: false,
+            ls: Default::default(),
 
             ahb1_pre: AHBPrescaler::DIV1,
             ahb2_pre: AHBPrescaler::DIV1,
@@ -177,16 +102,15 @@ impl Default for Config {
     }
 }
 
-pub(crate) fn compute_clocks(config: &Config) -> Clocks {
+#[cfg(stm32wb)]
-    let hse_clk = config.hse.as_ref().map(|hse| match hse.prediv {
+/// RCC initialization function
-        HsePrescaler::NotDivided => hse.frequency,
+pub(crate) unsafe fn init(config: Config) {
-        HsePrescaler::Div2 => hse.frequency / 2u32,
+    let hse_clk = config.hse.as_ref().map(|hse| hse.frequency / hse.prediv);
-    });
 
     let mux_clk = config.mux.as_ref().map(|pll_mux| {
         (match pll_mux.source {
-            PllSource::Hse => hse_clk.unwrap(),
+            PllSource::HSE => hse_clk.unwrap(),
-            PllSource::Hsi => HSI_FREQ,
+            PllSource::HSI16 => HSI_FREQ,
             _ => unreachable!(),
         } / pll_mux.prediv)
     });
@@ -206,44 +130,19 @@ pub(crate) fn compute_clocks(config: &Config) -> Clocks {
 
     let sys_clk = match config.sys {
         Sysclk::HSE => hse_clk.unwrap(),
-        Sysclk::HSI => HSI_FREQ,
+        Sysclk::HSI16 => HSI_FREQ,
-        Sysclk::Pll => pll_r.unwrap(),
+        Sysclk::PLL => pll_r.unwrap(),
         _ => unreachable!(),
     };
 
-    let ahb1_clk = match config.ahb1_pre {
+    let ahb1_clk = sys_clk / config.ahb1_pre;
-        AHBPrescaler::DIV1 => sys_clk,
+    let ahb2_clk = sys_clk / config.ahb2_pre;
-        pre => {
+    let ahb3_clk = sys_clk / config.ahb3_pre;
-            let pre: u8 = pre.into();
-            let pre = 1u32 << (pre as u32 - 7);
-            sys_clk / pre
-        }
-    };
-
-    let ahb2_clk = match config.ahb2_pre {
-        AHBPrescaler::DIV1 => sys_clk,
-        pre => {
-            let pre: u8 = pre.into();
-            let pre = 1u32 << (pre as u32 - 7);
-            sys_clk / pre
-        }
-    };
-
-    let ahb3_clk = match config.ahb3_pre {
-        AHBPrescaler::DIV1 => sys_clk,
-        pre => {
-            let pre: u8 = pre.into();
-            let pre = 1u32 << (pre as u32 - 7);
-            sys_clk / pre
-        }
-    };
 
     let (apb1_clk, apb1_tim_clk) = match config.apb1_pre {
         APBPrescaler::DIV1 => (ahb1_clk, ahb1_clk),
         pre => {
-            let pre: u8 = pre.into();
+            let freq = ahb1_clk / pre;
-            let pre: u8 = 1 << (pre - 3);
-            let freq = ahb1_clk / pre as u32;
             (freq, freq * 2u32)
         }
     };
@@ -251,43 +150,20 @@ pub(crate) fn compute_clocks(config: &Config) -> Clocks {
     let (apb2_clk, apb2_tim_clk) = match config.apb2_pre {
         APBPrescaler::DIV1 => (ahb1_clk, ahb1_clk),
         pre => {
-            let pre: u8 = pre.into();
+            let freq = ahb1_clk / pre;
-            let pre: u8 = 1 << (pre - 3);
-            let freq = ahb1_clk / pre as u32;
             (freq, freq * 2u32)
         }
     };
 
-    let rtc_clk = match config.rtc {
-        Some(RtcClockSource::LSI) => Some(LSI_FREQ),
-        Some(RtcClockSource::LSE) => Some(config.lse.unwrap()),
-        _ => None,
-    };
-
-    Clocks {
-        sys: sys_clk,
-        ahb1: ahb1_clk,
-        ahb2: ahb2_clk,
-        ahb3: ahb3_clk,
-        apb1: apb1_clk,
-        apb2: apb2_clk,
-        apb1_tim: apb1_tim_clk,
-        apb2_tim: apb2_tim_clk,
-        rtc: rtc_clk,
-        rtc_hse: None,
-    }
-}
-
-pub(crate) fn configure_clocks(config: &Config) {
     let rcc = crate::pac::RCC;
 
     let needs_hsi = if let Some(pll_mux) = &config.mux {
-        pll_mux.source == PllSource::Hsi
+        pll_mux.source == PllSource::HSI16
     } else {
         false
     };
 
-    if needs_hsi || config.sys == Sysclk::HSI {
+    if needs_hsi || config.sys == Sysclk::HSI16 {
         rcc.cr().modify(|w| {
             w.set_hsion(true);
         });
@@ -297,16 +173,12 @@ pub(crate) fn configure_clocks(config: &Config) {
 
     rcc.cfgr().modify(|w| w.set_stopwuck(true));
 
-    BackupDomain::configure_ls(
+    let rtc = config.ls.init();
-        config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
-        config.lsi,
-        config.lse.map(|_| Default::default()),
-    );
 
     match &config.hse {
         Some(hse) => {
             rcc.cr().modify(|w| {
-                w.set_hsepre(hse.prediv.into());
+                w.set_hsepre(hse.prediv);
                 w.set_hseon(true);
             });
 
@@ -328,18 +200,18 @@ pub(crate) fn configure_clocks(config: &Config) {
     match &config.pll {
         Some(pll) => {
             rcc.pllcfgr().modify(|w| {
-                w.set_plln(pll.mul as u8);
+                w.set_plln(pll.mul);
                 pll.divp.map(|divp| {
                     w.set_pllpen(true);
-                    w.set_pllp((divp - 1) as u8)
+                    w.set_pllp(divp)
                 });
                 pll.divq.map(|divq| {
                     w.set_pllqen(true);
-                    w.set_pllq((divq - 1) as u8)
+                    w.set_pllq(divq)
                 });
                 pll.divr.map(|divr| {
-                    // w.set_pllren(true);
+                    w.set_pllren(true);
-                    w.set_pllr((divr - 1) as u8);
+                    w.set_pllr(divr);
                 });
             });
 
@@ -352,13 +224,25 @@ pub(crate) fn configure_clocks(config: &Config) {
 
     rcc.cfgr().modify(|w| {
         w.set_sw(config.sys.into());
-        w.set_hpre(config.ahb1_pre.into());
+        w.set_hpre(config.ahb1_pre);
-        w.set_ppre1(config.apb1_pre.into());
+        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre.into());
+        w.set_ppre2(config.apb2_pre);
     });
 
     rcc.extcfgr().modify(|w| {
-        w.set_c2hpre(config.ahb2_pre.into());
+        w.set_c2hpre(config.ahb2_pre);
-        w.set_shdhpre(config.ahb3_pre.into());
+        w.set_shdhpre(config.ahb3_pre);
     });
+
+    set_freqs(Clocks {
+        sys: sys_clk,
+        ahb1: ahb1_clk,
+        ahb2: ahb2_clk,
+        ahb3: ahb3_clk,
+        apb1: apb1_clk,
+        apb2: apb2_clk,
+        apb1_tim: apb1_tim_clk,
+        apb2_tim: apb2_tim_clk,
+        rtc,
+    })
 }

embassy-stm32/src/rcc/wba.rs

@@ -7,9 +7,6 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
 pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
 
@@ -28,7 +25,7 @@ pub enum PllSrc {
 impl Into<Pllsrc> for PllSrc {
     fn into(self) -> Pllsrc {
         match self {
-            PllSrc::HSE(..) => Pllsrc::HSE32,
+            PllSrc::HSE(..) => Pllsrc::HSE,
             PllSrc::HSI16 => Pllsrc::HSI16,
         }
     }
@@ -37,19 +34,19 @@ impl Into<Pllsrc> for PllSrc {
 impl Into<Sw> for ClockSrc {
     fn into(self) -> Sw {
         match self {
-            ClockSrc::HSE(..) => Sw::HSE32,
+            ClockSrc::HSE(..) => Sw::HSE,
             ClockSrc::HSI16 => Sw::HSI16,
         }
     }
 }
 
-#[derive(Copy, Clone)]
 pub struct Config {
     pub mux: ClockSrc,
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
     pub apb7_pre: APBPrescaler,
+    pub ls: super::LsConfig,
 }
 
 impl Default for Config {
@@ -60,6 +57,7 @@ impl Default for Config {
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
             apb7_pre: APBPrescaler::DIV1,
+            ls: Default::default(),
         }
     }
 }
@@ -108,13 +106,13 @@ pub(crate) unsafe fn init(config: Config) {
     });
 
     RCC.cfgr2().modify(|w| {
-        w.set_hpre(config.ahb_pre.into());
+        w.set_hpre(config.ahb_pre);
-        w.set_ppre1(config.apb1_pre.into());
+        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre.into());
+        w.set_ppre2(config.apb2_pre);
     });
 
     RCC.cfgr3().modify(|w| {
-        w.set_ppre7(config.apb7_pre.into());
+        w.set_ppre7(config.apb7_pre);
     });
 
     let ahb_freq = sys_clk / config.ahb_pre;
@@ -140,6 +138,8 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
+    let rtc = config.ls.init();
+
     set_freqs(Clocks {
         sys: sys_clk,
         ahb1: ahb_freq,
@@ -150,5 +150,6 @@ pub(crate) unsafe fn init(config: Config) {
         apb7: apb7_freq,
         apb1_tim: apb1_tim_freq,
         apb2_tim: apb2_tim_freq,
+        rtc,
     });
 }

embassy-stm32/src/rcc/wl.rs

@@ -1,136 +1,27 @@
-pub use super::bus::{AHBPrescaler, APBPrescaler};
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
-use crate::pac::rcc::vals::Adcsel;
+use crate::pac::rcc::vals::Sw;
+pub use crate::pac::rcc::vals::{
+    Adcsel as AdcClockSource, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm, Plln, Pllp, Pllq, Pllr,
+    Pllsrc as PllSource, Ppre as APBPrescaler,
+};
 use crate::pac::{FLASH, RCC};
-use crate::rcc::bd::{BackupDomain, RtcClockSource};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
 
-/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
-/// and with the addition of the init function to configure a system clock.
-
-/// Only the basic setup using the HSE and HSI clocks are supported as of now.
-
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// LSI speed
+/// HSE speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
+pub const HSE_FREQ: Hertz = Hertz(32_000_000);
-
-/// HSE32 speed
-pub const HSE32_FREQ: Hertz = Hertz(32_000_000);
 
 /// System clock mux source
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
     MSI(MSIRange),
-    HSE32,
+    HSE,
     HSI16,
 }
 
-#[derive(Clone, Copy, PartialOrd, PartialEq)]
-pub enum MSIRange {
-    /// Around 100 kHz
-    Range0,
-    /// Around 200 kHz
-    Range1,
-    /// Around 400 kHz
-    Range2,
-    /// Around 800 kHz
-    Range3,
-    /// Around 1 MHz
-    Range4,
-    /// Around 2 MHz
-    Range5,
-    /// Around 4 MHz (reset value)
-    Range6,
-    /// Around 8 MHz
-    Range7,
-    /// Around 16 MHz
-    Range8,
-    /// Around 24 MHz
-    Range9,
-    /// Around 32 MHz
-    Range10,
-    /// Around 48 MHz
-    Range11,
-}
-
-impl MSIRange {
-    fn freq(&self) -> u32 {
-        match self {
-            MSIRange::Range0 => 100_000,
-            MSIRange::Range1 => 200_000,
-            MSIRange::Range2 => 400_000,
-            MSIRange::Range3 => 800_000,
-            MSIRange::Range4 => 1_000_000,
-            MSIRange::Range5 => 2_000_000,
-            MSIRange::Range6 => 4_000_000,
-            MSIRange::Range7 => 8_000_000,
-            MSIRange::Range8 => 16_000_000,
-            MSIRange::Range9 => 24_000_000,
-            MSIRange::Range10 => 32_000_000,
-            MSIRange::Range11 => 48_000_000,
-        }
-    }
-
-    fn vos(&self) -> VoltageScale {
-        if self > &MSIRange::Range8 {
-            VoltageScale::RANGE1
-        } else {
-            VoltageScale::RANGE2
-        }
-    }
-}
-
-impl Default for MSIRange {
-    fn default() -> MSIRange {
-        MSIRange::Range6
-    }
-}
-
-impl Into<u8> for MSIRange {
-    fn into(self) -> u8 {
-        match self {
-            MSIRange::Range0 => 0b0000,
-            MSIRange::Range1 => 0b0001,
-            MSIRange::Range2 => 0b0010,
-            MSIRange::Range3 => 0b0011,
-            MSIRange::Range4 => 0b0100,
-            MSIRange::Range5 => 0b0101,
-            MSIRange::Range6 => 0b0110,
-            MSIRange::Range7 => 0b0111,
-            MSIRange::Range8 => 0b1000,
-            MSIRange::Range9 => 0b1001,
-            MSIRange::Range10 => 0b1010,
-            MSIRange::Range11 => 0b1011,
-        }
-    }
-}
-
-#[derive(Clone, Copy)]
-pub enum AdcClockSource {
-    HSI16,
-    PLLPCLK,
-    SYSCLK,
-}
-
-impl AdcClockSource {
-    pub fn adcsel(&self) -> Adcsel {
-        match self {
-            AdcClockSource::HSI16 => Adcsel::HSI16,
-            AdcClockSource::PLLPCLK => Adcsel::PLLPCLK,
-            AdcClockSource::SYSCLK => Adcsel::SYSCLK,
-        }
-    }
-}
-
-impl Default for AdcClockSource {
-    fn default() -> Self {
-        Self::HSI16
-    }
-}
-
 /// Clocks configutation
 pub struct Config {
     pub mux: ClockSrc,
@@ -138,91 +29,60 @@ pub struct Config {
     pub shd_ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
-    pub rtc_mux: RtcClockSource,
-    pub lse: Option<Hertz>,
-    pub lsi: bool,
     pub adc_clock_source: AdcClockSource,
+    pub ls: super::LsConfig,
 }
 
 impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            mux: ClockSrc::MSI(MSIRange::default()),
+            mux: ClockSrc::MSI(MSIRange::RANGE4M),
             ahb_pre: AHBPrescaler::DIV1,
             shd_ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
-            rtc_mux: RtcClockSource::LSI,
+            adc_clock_source: AdcClockSource::HSI16,
-            lsi: true,
+            ls: Default::default(),
-            lse: None,
-            adc_clock_source: AdcClockSource::default(),
         }
     }
 }
 
-#[repr(u8)]
-pub enum Lsedrv {
-    Low = 0,
-    MediumLow = 1,
-    MediumHigh = 2,
-    High = 3,
-}
-
 pub(crate) unsafe fn init(config: Config) {
     let (sys_clk, sw, vos) = match config.mux {
-        ClockSrc::HSI16 => (HSI_FREQ.0, 0x01, VoltageScale::RANGE2),
+        ClockSrc::HSI16 => (HSI_FREQ, Sw::HSI16, VoltageScale::RANGE2),
-        ClockSrc::HSE32 => (HSE32_FREQ.0, 0x02, VoltageScale::RANGE1),
+        ClockSrc::HSE => (HSE_FREQ, Sw::HSE, VoltageScale::RANGE1),
-        ClockSrc::MSI(range) => (range.freq(), 0x00, range.vos()),
+        ClockSrc::MSI(range) => (msirange_to_hertz(range), Sw::MSI, msirange_to_vos(range)),
     };
 
-    let ahb_freq: u32 = match config.ahb_pre {
+    let ahb_freq = sys_clk / config.ahb_pre;
-        AHBPrescaler::DIV1 => sys_clk,
+    let shd_ahb_freq = sys_clk / config.shd_ahb_pre;
-        pre => {
-            let pre: u8 = pre.into();
-            let pre = 1 << (pre as u32 - 7);
-            sys_clk / pre
-        }
-    };
-
-    let shd_ahb_freq: u32 = match config.shd_ahb_pre {
-        AHBPrescaler::DIV1 => sys_clk,
-        pre => {
-            let pre: u8 = pre.into();
-            let pre = 1 << (pre as u32 - 7);
-            sys_clk / pre
-        }
-    };
 
     let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: u8 = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
         }
     };
 
     let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
         APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
         pre => {
-            let pre: u8 = pre.into();
+            let freq = ahb_freq / pre;
-            let pre: u8 = 1 << (pre - 3);
+            (freq, freq * 2u32)
-            let freq = ahb_freq / pre as u32;
-            (freq, freq * 2)
         }
     };
 
     // Adjust flash latency
-    let flash_clk_src_freq: u32 = shd_ahb_freq;
+    let flash_clk_src_freq = shd_ahb_freq;
     let ws = match vos {
-        VoltageScale::RANGE1 => match flash_clk_src_freq {
+        VoltageScale::RANGE1 => match flash_clk_src_freq.0 {
             0..=18_000_000 => 0b000,
             18_000_001..=36_000_000 => 0b001,
             _ => 0b010,
         },
-        VoltageScale::RANGE2 => match flash_clk_src_freq {
+        VoltageScale::RANGE2 => match flash_clk_src_freq.0 {
             0..=6_000_000 => 0b000,
             6_000_001..=12_000_000 => 0b001,
             _ => 0b010,
@@ -236,17 +96,14 @@ pub(crate) unsafe fn init(config: Config) {
 
     while FLASH.acr().read().latency() != ws {}
 
-    // Enables the LSI if configured
-    BackupDomain::configure_ls(config.rtc_mux, config.lsi, config.lse.map(|_| Default::default()));
-
     match config.mux {
         ClockSrc::HSI16 => {
             // Enable HSI16
             RCC.cr().write(|w| w.set_hsion(true));
             while !RCC.cr().read().hsirdy() {}
         }
-        ClockSrc::HSE32 => {
+        ClockSrc::HSE => {
-            // Enable HSE32
+            // Enable HSE
             RCC.cr().write(|w| {
                 w.set_hsebyppwr(true);
                 w.set_hseon(true);
@@ -258,49 +115,70 @@ pub(crate) unsafe fn init(config: Config) {
             assert!(!cr.msion() || cr.msirdy());
             RCC.cr().write(|w| {
                 w.set_msirgsel(true);
-                w.set_msirange(range.into());
+                w.set_msirange(range);
                 w.set_msion(true);
 
-                if let RtcClockSource::LSE = config.rtc_mux {
+                // If LSE is enabled, enable calibration of MSI
-                    // If LSE is enabled, enable calibration of MSI
+                w.set_msipllen(config.ls.lse.is_some());
-                    w.set_msipllen(true);
-                } else {
-                    w.set_msipllen(false);
-                }
             });
             while !RCC.cr().read().msirdy() {}
         }
     }
 
     RCC.extcfgr().modify(|w| {
-        if config.shd_ahb_pre == AHBPrescaler::DIV1 {
+        w.set_shdhpre(config.shd_ahb_pre);
-            w.set_shdhpre(0);
-        } else {
-            w.set_shdhpre(config.shd_ahb_pre.into());
-        }
     });
 
     RCC.cfgr().modify(|w| {
         w.set_sw(sw.into());
         w.set_hpre(config.ahb_pre);
-        w.set_ppre1(config.apb1_pre.into());
+        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre.into());
+        w.set_ppre2(config.apb2_pre);
     });
 
     // ADC clock MUX
-    RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source.adcsel()));
+    RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source));
 
     // TODO: switch voltage range
 
+    let rtc = config.ls.init();
+
     set_freqs(Clocks {
-        sys: Hertz(sys_clk),
+        sys: sys_clk,
-        ahb1: Hertz(ahb_freq),
+        ahb1: ahb_freq,
-        ahb2: Hertz(ahb_freq),
+        ahb2: ahb_freq,
-        ahb3: Hertz(shd_ahb_freq),
+        ahb3: shd_ahb_freq,
-        apb1: Hertz(apb1_freq),
+        apb1: apb1_freq,
-        apb2: Hertz(apb2_freq),
+        apb2: apb2_freq,
-        apb3: Hertz(shd_ahb_freq),
+        apb3: shd_ahb_freq,
-        apb1_tim: Hertz(apb1_tim_freq),
+        apb1_tim: apb1_tim_freq,
-        apb2_tim: Hertz(apb2_tim_freq),
+        apb2_tim: apb2_tim_freq,
+        rtc,
     });
 }
+
+fn msirange_to_hertz(range: MSIRange) -> Hertz {
+    match range {
+        MSIRange::RANGE100K => Hertz(100_000),
+        MSIRange::RANGE200K => Hertz(200_000),
+        MSIRange::RANGE400K => Hertz(400_000),
+        MSIRange::RANGE800K => Hertz(800_000),
+        MSIRange::RANGE1M => Hertz(1_000_000),
+        MSIRange::RANGE2M => Hertz(2_000_000),
+        MSIRange::RANGE4M => Hertz(4_000_000),
+        MSIRange::RANGE8M => Hertz(8_000_000),
+        MSIRange::RANGE16M => Hertz(16_000_000),
+        MSIRange::RANGE24M => Hertz(24_000_000),
+        MSIRange::RANGE32M => Hertz(32_000_000),
+        MSIRange::RANGE48M => Hertz(48_000_000),
+        _ => unreachable!(),
+    }
+}
+
+fn msirange_to_vos(range: MSIRange) -> VoltageScale {
+    if range.to_bits() > MSIRange::RANGE16M.to_bits() {
+        VoltageScale::RANGE1
+    } else {
+        VoltageScale::RANGE2
+    }
+}

embassy-stm32/src/rng.rs

@@ -13,6 +13,7 @@ use crate::{interrupt, pac, peripherals, Peripheral};
 
 static RNG_WAKER: AtomicWaker = AtomicWaker::new();
 
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
     SeedError,

embassy-stm32/src/rtc/mod.rs

@@ -10,7 +10,6 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::blocking_mutex::Mutex;
 
 pub use self::datetime::{DateTime, DayOfWeek, Error as DateTimeError};
-pub use crate::rcc::RtcClockSource;
 use crate::time::Hertz;
 
 /// refer to AN4759 to compare features of RTC2 and RTC3
@@ -93,21 +92,50 @@ impl RtcTimeProvider {
     ///
     /// Will return an `RtcError::InvalidDateTime` if the stored value in the system is not a valid [`DayOfWeek`].
     pub fn now(&self) -> Result<DateTime, RtcError> {
-        let r = RTC::regs();
+        // For RM0433 we use BYPSHAD=1 to work around errata ES0392 2.19.1
-        let tr = r.tr().read();
+        #[cfg(rcc_h7rm0433)]
-        let second = bcd2_to_byte((tr.st(), tr.su()));
+        loop {
-        let minute = bcd2_to_byte((tr.mnt(), tr.mnu()));
+            let r = RTC::regs();
-        let hour = bcd2_to_byte((tr.ht(), tr.hu()));
+            let ss = r.ssr().read().ss();
-        // Reading either RTC_SSR or RTC_TR locks the values in the higher-order
+            let dr = r.dr().read();
-        // calendar shadow registers until RTC_DR is read.
+            let tr = r.tr().read();
-        let dr = r.dr().read();
 
-        let weekday = dr.wdu();
+            // If an RTCCLK edge occurs during read we may see inconsistent values
-        let day = bcd2_to_byte((dr.dt(), dr.du()));
+            // so read ssr again and see if it has changed. (see RM0433 Rev 7 46.3.9)
-        let month = bcd2_to_byte((dr.mt() as u8, dr.mu()));
+            let ss_after = r.ssr().read().ss();
-        let year = bcd2_to_byte((dr.yt(), dr.yu())) as u16 + 1970_u16;
+            if ss == ss_after {
+                let second = bcd2_to_byte((tr.st(), tr.su()));
+                let minute = bcd2_to_byte((tr.mnt(), tr.mnu()));
+                let hour = bcd2_to_byte((tr.ht(), tr.hu()));
 
-        self::datetime::datetime(year, month, day, weekday, hour, minute, second).map_err(RtcError::InvalidDateTime)
+                let weekday = dr.wdu();
+                let day = bcd2_to_byte((dr.dt(), dr.du()));
+                let month = bcd2_to_byte((dr.mt() as u8, dr.mu()));
+                let year = bcd2_to_byte((dr.yt(), dr.yu())) as u16 + 1970_u16;
+
+                return self::datetime::datetime(year, month, day, weekday, hour, minute, second)
+                    .map_err(RtcError::InvalidDateTime);
+            }
+        }
+
+        #[cfg(not(rcc_h7rm0433))]
+        {
+            let r = RTC::regs();
+            let tr = r.tr().read();
+            let second = bcd2_to_byte((tr.st(), tr.su()));
+            let minute = bcd2_to_byte((tr.mnt(), tr.mnu()));
+            let hour = bcd2_to_byte((tr.ht(), tr.hu()));
+            // Reading either RTC_SSR or RTC_TR locks the values in the higher-order
+            // calendar shadow registers until RTC_DR is read.
+            let dr = r.dr().read();
+
+            let weekday = dr.wdu();
+            let day = bcd2_to_byte((dr.dt(), dr.du()));
+            let month = bcd2_to_byte((dr.mt() as u8, dr.mu()));
+            let year = bcd2_to_byte((dr.yt(), dr.yu())) as u16 + 1970_u16;
+
+            self::datetime::datetime(year, month, day, weekday, hour, minute, second).map_err(RtcError::InvalidDateTime)
+        }
     }
 }
 
@@ -155,7 +183,7 @@ impl Default for RtcCalibrationCyclePeriod {
 
 impl Rtc {
     pub fn new(_rtc: impl Peripheral<P = RTC>, rtc_config: RtcConfig) -> Self {
-        #[cfg(any(rcc_wle, rcc_wl5, rcc_g4, rcc_g0, rtc_v2l4, rtc_v2wb))]
+        #[cfg(not(any(stm32l0, stm32f3, stm32l1, stm32f0, stm32f2)))]
         <RTC as crate::rcc::sealed::RccPeripheral>::enable();
 
         let mut this = Self {
@@ -175,19 +203,8 @@ impl Rtc {
     }
 
     fn frequency() -> Hertz {
-        #[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
         let freqs = unsafe { crate::rcc::get_freqs() };
-
+        freqs.rtc.unwrap()
-        // Load the clock frequency from the rcc mod, if supported
-        #[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
-        match freqs.rtc {
-            Some(hertz) => hertz,
-            None => freqs.rtc_hse.unwrap(),
-        }
-
-        // Assume the  default value, if not supported
-        #[cfg(not(any(rcc_wb, rcc_f4, rcc_f410)))]
-        Hertz(32_768)
     }
 
     /// Acquire a [`RtcTimeProvider`] instance.

embassy-stm32/src/rtc/v2.rs

@@ -157,6 +157,8 @@ impl super::Rtc {
                 w.set_fmt(stm32_metapac::rtc::vals::Fmt::TWENTY_FOUR_HOUR);
                 w.set_osel(Osel::DISABLED);
                 w.set_pol(Pol::HIGH);
+                #[cfg(rcc_h7rm0433)]
+                w.set_bypshad(true);
             });
 
             rtc.prer().modify(|w| {

embassy-stm32/src/sai/mod.rs

@@ -11,7 +11,7 @@ use crate::pac::sai::{vals, Sai as Regs};
 use crate::rcc::RccPeripheral;
 use crate::{peripherals, Peripheral};
 
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
     NotATransmitter,

embassy-stm32/src/spi/mod.rs

@@ -15,7 +15,7 @@ use crate::rcc::RccPeripheral;
 use crate::time::Hertz;
 use crate::{peripherals, Peripheral};
 
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
     Framing,

embassy-stm32/src/time.rs

@@ -77,3 +77,10 @@ impl Div<u8> for Hertz {
         self / (rhs as u32)
     }
 }
+
+impl Div<Hertz> for Hertz {
+    type Output = u32;
+    fn div(self, rhs: Hertz) -> Self::Output {
+        self.0 / rhs.0
+    }
+}

embassy-stm32/src/timer/complementary_pwm.rs

@@ -122,6 +122,46 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
     }
 }
 
+impl<'d, T: ComplementaryCaptureCompare16bitInstance> embedded_hal_02::Pwm for ComplementaryPwm<'d, T> {
+    type Channel = Channel;
+    type Time = Hertz;
+    type Duty = u16;
+
+    fn disable(&mut self, channel: Self::Channel) {
+        self.inner.enable_complementary_channel(channel, false);
+        self.inner.enable_channel(channel, false);
+    }
+
+    fn enable(&mut self, channel: Self::Channel) {
+        self.inner.enable_channel(channel, true);
+        self.inner.enable_complementary_channel(channel, true);
+    }
+
+    fn get_period(&self) -> Self::Time {
+        self.inner.get_frequency().into()
+    }
+
+    fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
+        self.inner.get_compare_value(channel)
+    }
+
+    fn get_max_duty(&self) -> Self::Duty {
+        self.inner.get_max_compare_value() + 1
+    }
+
+    fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
+        assert!(duty <= self.get_max_duty());
+        self.inner.set_compare_value(channel, duty)
+    }
+
+    fn set_period<P>(&mut self, period: P)
+    where
+        P: Into<Self::Time>,
+    {
+        self.inner.set_frequency(period.into());
+    }
+}
+
 fn compute_dead_time_value(value: u16) -> (Ckd, u8) {
     /*
         Dead-time = T_clk * T_dts * T_dtg

embassy-stm32/src/timer/mod.rs

@@ -70,6 +70,16 @@ pub(crate) mod sealed {
         fn set_autoreload_preload(&mut self, enable: vals::Arpe) {
             Self::regs().cr1().modify(|r| r.set_arpe(enable));
         }
+
+        fn get_frequency(&self) -> Hertz {
+            let timer_f = Self::frequency();
+
+            let regs = Self::regs();
+            let arr = regs.arr().read().arr();
+            let psc = regs.psc().read().psc();
+
+            timer_f / arr / (psc + 1)
+        }
     }
 
     pub trait GeneralPurpose16bitInstance: Basic16bitInstance {
@@ -103,6 +113,16 @@ pub(crate) mod sealed {
             regs.egr().write(|r| r.set_ug(true));
             regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT));
         }
+
+        fn get_frequency(&self) -> Hertz {
+            let timer_f = Self::frequency();
+
+            let regs = Self::regs_gp32();
+            let arr = regs.arr().read().arr();
+            let psc = regs.psc().read().psc();
+
+            timer_f / arr / (psc + 1)
+        }
     }
 
     pub trait AdvancedControlInstance: GeneralPurpose16bitInstance {
@@ -183,6 +203,10 @@ pub(crate) mod sealed {
         fn get_max_compare_value(&self) -> u16 {
             Self::regs_gp16().arr().read().arr()
         }
+
+        fn get_compare_value(&self, channel: Channel) -> u16 {
+            Self::regs_gp16().ccr(channel.raw()).read().ccr()
+        }
     }
 
     pub trait ComplementaryCaptureCompare16bitInstance: CaptureCompare16bitInstance + AdvancedControlInstance {
@@ -219,6 +243,10 @@ pub(crate) mod sealed {
         fn get_max_compare_value(&self) -> u32 {
             Self::regs_gp32().arr().read().arr()
         }
+
+        fn get_compare_value(&self, channel: Channel) -> u32 {
+            Self::regs_gp32().ccr(channel.raw()).read().ccr()
+        }
     }
 }
 

embassy-stm32/src/timer/simple_pwm.rs

@@ -109,3 +109,41 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
         self.inner.set_output_polarity(channel, polarity);
     }
 }
+
+impl<'d, T: CaptureCompare16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d, T> {
+    type Channel = Channel;
+    type Time = Hertz;
+    type Duty = u16;
+
+    fn disable(&mut self, channel: Self::Channel) {
+        self.inner.enable_channel(channel, false);
+    }
+
+    fn enable(&mut self, channel: Self::Channel) {
+        self.inner.enable_channel(channel, true);
+    }
+
+    fn get_period(&self) -> Self::Time {
+        self.inner.get_frequency().into()
+    }
+
+    fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
+        self.inner.get_compare_value(channel)
+    }
+
+    fn get_max_duty(&self) -> Self::Duty {
+        self.inner.get_max_compare_value() + 1
+    }
+
+    fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
+        assert!(duty <= self.get_max_duty());
+        self.inner.set_compare_value(channel, duty)
+    }
+
+    fn set_period<P>(&mut self, period: P)
+    where
+        P: Into<Self::Time>,
+    {
+        self.inner.set_frequency(period.into());
+    }
+}

embassy-sync/Cargo.toml

@@ -35,7 +35,7 @@ futures-util = { version = "0.3.17", default-features = false }
 critical-section = "1.1"
 heapless = "0.7.5"
 cfg-if = "1.0.0"
-embedded-io-async = { version = "0.5.0", optional = true }
+embedded-io-async = { version = "0.6.0", optional = true }
 
 [dev-dependencies]
 futures-executor = { version = "0.3.17", features = [ "thread-pool" ] }

examples/nrf52840/Cargo.toml

@@ -35,8 +35,8 @@ embassy-time = { version = "0.1.3", path = "../../embassy-time", features = ["de
 embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 embassy-net = { version = "0.1.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet"], optional = true }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt", "msos-descriptor",], optional = true }
-embedded-io = { version = "0.5.0", features = ["defmt-03"]  }
+embedded-io = { version = "0.6.0", features = ["defmt-03"]  }
-embedded-io-async = { version = "0.5.0", optional = true, features = ["defmt-03"] }
+embedded-io-async = { version = "0.6.0", optional = true, features = ["defmt-03"] }
 embassy-lora = { version = "0.1.0", path = "../../embassy-lora", features = ["time", "defmt"], optional = true }
 lora-phy = { version = "2", optional = true }
 lorawan-device = { version = "0.11.0", default-features = false, features = ["async", "external-lora-phy"], optional = true }

examples/nrf5340/Cargo.toml

@@ -37,7 +37,7 @@ embassy-net = { version = "0.1.0", path = "../../embassy-net", features = [
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = [
     "defmt",
 ] }
-embedded-io-async = { version = "0.5.0" }
+embedded-io-async = { version = "0.6.0" }
 
 defmt = "0.3"
 defmt-rtt = "0.4"

examples/rp/Cargo.toml

@@ -45,7 +45,7 @@ usbd-hid = "0.6.1"
 embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }
 embedded-hal-async = "1.0.0-rc.1"
 embedded-hal-bus = { version = "0.1.0-rc.1", features = ["async"] }
-embedded-io-async = { version = "0.5.0", features = ["defmt-03"] }
+embedded-io-async = { version = "0.6.0", features = ["defmt-03"] }
 embedded-storage = { version = "0.3" }
 static_cell = { version = "1.1", features = ["nightly"]}
 log = "0.4"

examples/std/Cargo.toml

@@ -11,8 +11,8 @@ embassy-time = { version = "0.1.3", path = "../../embassy-time", features = ["lo
 embassy-net = { version = "0.1.0", path = "../../embassy-net", features=[ "std", "nightly", "log", "medium-ethernet", "medium-ip", "tcp", "udp", "dns", "dhcpv4", "proto-ipv6"] }
 embassy-net-tuntap = { version = "0.1.0", path = "../../embassy-net-tuntap" }
 embassy-net-ppp = { version = "0.1.0", path = "../../embassy-net-ppp", features = ["log"]}
-embedded-io-async = { version = "0.5.0" }
+embedded-io-async = { version = "0.6.0" }
-embedded-io-adapters = { version = "0.5.0", features = ["futures-03"] }
+embedded-io-adapters = { version = "0.6.0", features = ["futures-03"] }
 critical-section = { version = "1.1", features = ["std"] }
 smoltcp = { version = "0.10.0", features = ["dns-max-server-count-4"] }
 

examples/stm32f2/src/bin/pll.rs

@@ -7,7 +7,7 @@ use core::convert::TryFrom;
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::rcc::{
-    APBPrescaler, ClockSrc, HSEConfig, HSESrc, PLL48Div, PLLConfig, PLLMainDiv, PLLMul, PLLPreDiv, PLLSrc,
+    APBPrescaler, ClockSrc, HSEConfig, HSESrc, PLLConfig, PLLMul, PLLPDiv, PLLPreDiv, PLLQDiv, PLLSrc,
 };
 use embassy_stm32::time::Hertz;
 use embassy_stm32::Config;
@@ -32,9 +32,9 @@ async fn main(_spawner: Spawner) {
         // 1 MHz PLL input * 240 = 240 MHz PLL VCO
         mul: unwrap!(PLLMul::try_from(240)),
         // 240 MHz PLL VCO / 2 = 120 MHz main PLL output
-        main_div: PLLMainDiv::Div2,
+        p_div: PLLPDiv::DIV2,
         // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
-        pll48_div: unwrap!(PLL48Div::try_from(5)),
+        q_div: PLLQDiv::DIV5,
     };
     // System clock comes from PLL (= the 120 MHz main PLL output)
     config.rcc.mux = ClockSrc::PLL;

examples/stm32f334/src/bin/adc.rs

@@ -6,7 +6,7 @@ use defmt::info;
 use embassy_executor::Spawner;
 use embassy_stm32::adc::{Adc, SampleTime};
 use embassy_stm32::peripherals::ADC1;
-use embassy_stm32::rcc::AdcClockSource;
+use embassy_stm32::rcc::{AdcClockSource, Adcpres};
 use embassy_stm32::time::mhz;
 use embassy_stm32::{adc, bind_interrupts, Config};
 use embassy_time::{Delay, Duration, Timer};
@@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) -> ! {
     config.rcc.hclk = Some(mhz(64));
     config.rcc.pclk1 = Some(mhz(32));
     config.rcc.pclk2 = Some(mhz(64));
-    config.rcc.adc = Some(AdcClockSource::PllDiv1);
+    config.rcc.adc = Some(AdcClockSource::Pll(Adcpres::DIV1));
 
     let mut p = embassy_stm32::init(config);
 

examples/stm32f334/src/bin/opamp.rs

@@ -5,9 +5,9 @@
 use defmt::info;
 use embassy_executor::Spawner;
 use embassy_stm32::adc::{Adc, SampleTime};
-use embassy_stm32::opamp::OpAmp;
+use embassy_stm32::opamp::{OpAmp, OpAmpGain};
 use embassy_stm32::peripherals::ADC2;
-use embassy_stm32::rcc::AdcClockSource;
+use embassy_stm32::rcc::{AdcClockSource, Adcpres};
 use embassy_stm32::time::mhz;
 use embassy_stm32::{adc, bind_interrupts, Config};
 use embassy_time::{Delay, Duration, Timer};
@@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) -> ! {
     config.rcc.hclk = Some(mhz(64));
     config.rcc.pclk1 = Some(mhz(32));
     config.rcc.pclk2 = Some(mhz(64));
-    config.rcc.adc = Some(AdcClockSource::PllDiv1);
+    config.rcc.adc = Some(AdcClockSource::Pll(Adcpres::DIV1));
 
     let mut p = embassy_stm32::init(config);
 
@@ -39,7 +39,7 @@ async fn main(_spawner: Spawner) -> ! {
 
     let mut vrefint = adc.enable_vref(&mut Delay);
     let mut temperature = adc.enable_temperature();
-    let mut buffer = opamp.buffer_for(&mut p.PA7);
+    let mut buffer = opamp.buffer_for(&mut p.PA7, OpAmpGain::Mul1);
 
     loop {
         let vref = adc.read(&mut vrefint).await;

examples/stm32f4/Cargo.toml

@@ -19,8 +19,8 @@ defmt-rtt = "0.4"
 cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
 cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
-embedded-io = { version = "0.5.0" }
+embedded-io = { version = "0.6.0" }
-embedded-io-async = { version = "0.5.0" }
+embedded-io-async = { version = "0.6.0" }
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
 heapless = { version = "0.7.5", default-features = false }

examples/stm32f4/src/bin/eth.rs

@@ -58,9 +58,8 @@ async fn main(spawner: Spawner) -> ! {
         p.PG13,
         p.PB13,
         p.PG11,
-        GenericSMI::new(),
+        GenericSMI::new(0),
         mac_addr,
-        0,
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());

examples/stm32f4/src/bin/mco.rs

@@ -5,7 +5,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::gpio::{Level, Output, Speed};
-use embassy_stm32::rcc::{Mco, Mco1Source, Mco2Source, McoClock};
+use embassy_stm32::rcc::{Mco, Mco1Source, Mco2Source, McoPrescaler};
 use embassy_time::{Duration, Timer};
 use {defmt_rtt as _, panic_probe as _};
 
@@ -14,8 +14,8 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let _mco1 = Mco::new(p.MCO1, p.PA8, Mco1Source::Hsi, McoClock::DIV1);
+    let _mco1 = Mco::new(p.MCO1, p.PA8, Mco1Source::HSI, McoPrescaler::DIV1);
-    let _mco2 = Mco::new(p.MCO2, p.PC9, Mco2Source::Pll, McoClock::DIV4);
+    let _mco2 = Mco::new(p.MCO2, p.PC9, Mco2Source::PLL, McoPrescaler::DIV4);
     let mut led = Output::new(p.PB7, Level::High, Speed::Low);
 
     loop {

examples/stm32f4/src/bin/rtc.rs

@@ -5,16 +5,14 @@
 use chrono::{NaiveDate, NaiveDateTime};
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rtc::{Rtc, RtcClockSource, RtcConfig};
+use embassy_stm32::rtc::{Rtc, RtcConfig};
 use embassy_stm32::Config;
 use embassy_time::{Duration, Timer};
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
-    let mut config = Config::default();
+    let config = Config::default();
-    config.rcc.lsi = true;
-    config.rcc.rtc = Option::Some(RtcClockSource::LSI);
     let p = embassy_stm32::init(config);
 
     info!("Hello World!");

examples/stm32f7/Cargo.toml

@@ -11,7 +11,7 @@ embassy-sync = { version = "0.3.0", path = "../../embassy-sync", features = ["de
 embassy-executor = { version = "0.3.0", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.3", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet"] }
-embedded-io-async = { version = "0.5.0" }
+embedded-io-async = { version = "0.6.0" }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
 
 defmt = "0.3"

examples/stm32f7/src/bin/eth.rs

@@ -59,9 +59,8 @@ async fn main(spawner: Spawner) -> ! {
         p.PG13,
         p.PB13,
         p.PG11,
-        GenericSMI::new(),
+        GenericSMI::new(0),
         mac_addr,
-        0,
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());

examples/stm32g4/src/bin/adc.rs

@@ -16,15 +16,15 @@ async fn main(_spawner: Spawner) {
 
     config.rcc.pll = Some(Pll {
         source: PllSrc::HSI16,
-        prediv_m: PllM::Div4,
+        prediv_m: PllM::DIV4,
-        mul_n: PllN::Mul85,
+        mul_n: PllN::MUL85,
         div_p: None,
         div_q: None,
         // Main system clock at 170 MHz
-        div_r: Some(PllR::Div2),
+        div_r: Some(PllR::DIV2),
     });
 
-    config.rcc.adc12_clock_source = AdcClockSource::SysClk;
+    config.rcc.adc12_clock_source = AdcClockSource::SYSCLK;
     config.rcc.mux = ClockSrc::PLL;
 
     let mut p = embassy_stm32::init(config);

examples/stm32g4/src/bin/pll.rs

@@ -15,12 +15,12 @@ async fn main(_spawner: Spawner) {
 
     config.rcc.pll = Some(Pll {
         source: PllSrc::HSI16,
-        prediv_m: PllM::Div4,
+        prediv_m: PllM::DIV4,
-        mul_n: PllN::Mul85,
+        mul_n: PllN::MUL85,
         div_p: None,
         div_q: None,
         // Main system clock at 170 MHz
-        div_r: Some(PllR::Div2),
+        div_r: Some(PllR::DIV2),
     });
 
     config.rcc.mux = ClockSrc::PLL;

examples/stm32g4/src/bin/usb_serial.rs

@@ -25,16 +25,16 @@ async fn main(_spawner: Spawner) {
     // Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE.
     const USE_HSI48: bool = true;
 
-    let pllq_div = if USE_HSI48 { None } else { Some(PllQ::Div6) };
+    let pllq_div = if USE_HSI48 { None } else { Some(PllQ::DIV6) };
 
     config.rcc.pll = Some(Pll {
         source: PllSrc::HSE(Hertz(8_000_000)),
-        prediv_m: PllM::Div2,
+        prediv_m: PllM::DIV2,
-        mul_n: PllN::Mul72,
+        mul_n: PllN::MUL72,
         div_p: None,
         div_q: pllq_div,
         // Main system clock at 144 MHz
-        div_r: Some(PllR::Div2),
+        div_r: Some(PllR::DIV2),
     });
 
     config.rcc.mux = ClockSrc::PLL;

examples/stm32h5/Cargo.toml

@@ -11,7 +11,7 @@ embassy-sync = { version = "0.3.0", path = "../../embassy-sync", features = ["de
 embassy-executor = { version = "0.3.0", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.3", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "unstable-traits", "tick-hz-32_768"] }
 embassy-net = { path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6"] }
-embedded-io-async = { version = "0.5.0" }
+embedded-io-async = { version = "0.6.0" }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
 
 defmt = "0.3"
@@ -22,7 +22,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }
 embedded-hal-async = { version = "=1.0.0-rc.1" }
-embedded-nal-async = { version = "0.5.0" }
+embedded-nal-async = { version = "0.6.0" }
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
 heapless = { version = "0.7.5", default-features = false }

examples/stm32h5/src/bin/eth.rs

@@ -9,7 +9,9 @@ use embassy_net::{Ipv4Address, Stack, StackResources};
 use embassy_stm32::eth::generic_smi::GenericSMI;
 use embassy_stm32::eth::{Ethernet, PacketQueue};
 use embassy_stm32::peripherals::ETH;
-use embassy_stm32::rcc::{AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllSource, Sysclk, VoltageScale};
+use embassy_stm32::rcc::{
+    AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk, VoltageScale,
+};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::time::Hertz;
 use embassy_stm32::{bind_interrupts, eth, peripherals, rng, Config};
@@ -42,10 +44,10 @@ async fn main(spawner: Spawner) -> ! {
     });
     config.rcc.pll1 = Some(Pll {
         source: PllSource::Hse,
-        prediv: 2,
+        prediv: PllPreDiv::DIV2,
-        mul: 125,
+        mul: PllMul::MUL125,
-        divp: Some(2),
+        divp: Some(PllDiv::DIV2),
-        divq: Some(2),
+        divq: Some(PllDiv::DIV2),
         divr: None,
     });
     config.rcc.ahb_pre = AHBPrescaler::DIV1;
@@ -78,9 +80,8 @@ async fn main(spawner: Spawner) -> ! {
         p.PG13,
         p.PB15,
         p.PG11,
-        GenericSMI::new(),
+        GenericSMI::new(0),
         mac_addr,
-        0,
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());

examples/stm32h5/src/bin/usb_serial.rs

@@ -4,7 +4,9 @@
 
 use defmt::{panic, *};
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllSource, Sysclk, VoltageScale};
+use embassy_stm32::rcc::{
+    AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk, VoltageScale,
+};
 use embassy_stm32::time::Hertz;
 use embassy_stm32::usb::{Driver, Instance};
 use embassy_stm32::{bind_interrupts, pac, peripherals, usb, Config};
@@ -29,9 +31,9 @@ async fn main(_spawner: Spawner) {
     });
     config.rcc.pll1 = Some(Pll {
         source: PllSource::Hse,
-        prediv: 2,
+        prediv: PllPreDiv::DIV2,
-        mul: 125,
+        mul: PllMul::MUL125,
-        divp: Some(2), // 250mhz
+        divp: Some(PllDiv::DIV2), // 250mhz
         divq: None,
         divr: None,
     });

examples/stm32h7/Cargo.toml

@@ -6,12 +6,12 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 # Change stm32h743bi to your chip name, if necessary.
-embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32h743bi", "time-driver-any", "exti", "memory-x", "unstable-pac", "unstable-traits"] }
+embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32h743bi", "time-driver-any", "exti", "memory-x", "unstable-pac", "unstable-traits", "chrono"] }
 embassy-sync = { version = "0.3.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.3.0", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.3", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "unstable-traits", "tick-hz-32_768"] }
 embassy-net = { path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6"] }
-embedded-io-async = { version = "0.5.0" }
+embedded-io-async = { version = "0.6.0" }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
 
 defmt = "0.3"
@@ -22,7 +22,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }
 embedded-hal-async = { version = "=1.0.0-rc.1" }
-embedded-nal-async = { version = "0.5.0" }
+embedded-nal-async = { version = "0.6.0" }
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
 heapless = { version = "0.7.5", default-features = false }
@@ -32,6 +32,7 @@ micromath = "2.0.0"
 stm32-fmc = "0.3.0"
 embedded-storage = "0.3.0"
 static_cell = { version = "1.1", features = ["nightly"]}
+chrono = { version = "^0.4", default-features = false }
 
 # cargo build/run
 [profile.dev]

examples/stm32h7/src/bin/adc.rs

@@ -18,16 +18,16 @@ async fn main(_spawner: Spawner) {
         config.rcc.csi = true;
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
-            divq: Some(8), // SPI1 cksel defaults to pll1_q
+            divq: Some(PllDiv::DIV8), // SPI1 cksel defaults to pll1_q
             divr: None,
         });
         config.rcc.pll2 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(8), // 100mhz
+            divp: Some(PllDiv::DIV8), // 100mhz
             divq: None,
             divr: None,
         });

examples/stm32h7/src/bin/camera.rs

@@ -6,7 +6,7 @@ use embassy_executor::Spawner;
 use embassy_stm32::dcmi::{self, *};
 use embassy_stm32::gpio::{Level, Output, Speed};
 use embassy_stm32::i2c::I2c;
-use embassy_stm32::rcc::{Mco, Mco1Source};
+use embassy_stm32::rcc::{Mco, Mco1Source, McoPrescaler};
 use embassy_stm32::time::khz;
 use embassy_stm32::{bind_interrupts, i2c, peripherals, Config};
 use embassy_time::{Duration, Timer};
@@ -32,10 +32,10 @@ async fn main(_spawner: Spawner) {
         config.rcc.csi = true;
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
-            divq: Some(8), // 100mhz
+            divq: Some(PllDiv::DIV8), // 100mhz
             divr: None,
         });
         config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
@@ -49,7 +49,7 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(config);
 
     defmt::info!("Hello World!");
-    let mco = Mco::new(p.MCO1, p.PA8, Mco1Source::HSI, 3);
+    let mco = Mco::new(p.MCO1, p.PA8, Mco1Source::HSI, McoPrescaler::DIV3);
 
     let mut led = Output::new(p.PE3, Level::High, Speed::Low);
     let cam_i2c = I2c::new(
@@ -184,7 +184,7 @@ mod ov7725 {
 
     const CAM_ADDR: u8 = 0x21;
 
-    #[derive(Format)]
+    #[derive(Format, PartialEq, Eq)]
     pub enum Error<I2cError: Format> {
         I2c(I2cError),
     }

examples/stm32h7/src/bin/dac.rs

@@ -20,16 +20,16 @@ fn main() -> ! {
         config.rcc.csi = true;
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
-            divq: Some(8), // SPI1 cksel defaults to pll1_q
+            divq: Some(PllDiv::DIV8), // 100mhz
             divr: None,
         });
         config.rcc.pll2 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(8), // 100mhz
+            divp: Some(PllDiv::DIV8), // 100mhz
             divq: None,
             divr: None,
         });

examples/stm32h7/src/bin/dac_dma.rs

@@ -28,16 +28,16 @@ async fn main(spawner: Spawner) {
         config.rcc.csi = true;
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
-            divq: Some(8), // SPI1 cksel defaults to pll1_q
+            divq: Some(PllDiv::DIV8), // 100mhz
             divr: None,
         });
         config.rcc.pll2 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(8), // 100mhz
+            divp: Some(PllDiv::DIV8), // 100mhz
             divq: None,
             divr: None,
         });

examples/stm32h7/src/bin/eth.rs

@@ -39,9 +39,9 @@ async fn main(spawner: Spawner) -> ! {
         config.rcc.hsi48 = true; // needed for RNG
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
             divq: None,
             divr: None,
         });
@@ -77,9 +77,8 @@ async fn main(spawner: Spawner) -> ! {
         p.PG13,
         p.PB13,
         p.PG11,
-        GenericSMI::new(),
+        GenericSMI::new(0),
         mac_addr,
-        0,
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());

examples/stm32h7/src/bin/eth_client.rs

@@ -40,9 +40,9 @@ async fn main(spawner: Spawner) -> ! {
         config.rcc.hsi48 = true; // needed for RNG
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
             divq: None,
             divr: None,
         });
@@ -78,9 +78,8 @@ async fn main(spawner: Spawner) -> ! {
         p.PG13,
         p.PB13,
         p.PG11,
-        GenericSMI::new(),
+        GenericSMI::new(0),
         mac_addr,
-        0,
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());

examples/stm32h7/src/bin/fmc.rs

@@ -18,10 +18,10 @@ async fn main(_spawner: Spawner) {
         config.rcc.csi = true;
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
-            divq: Some(8), // 100mhz
+            divq: Some(PllDiv::DIV8), // 100mhz
             divr: None,
         });
         config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

examples/stm32h7/src/bin/low_level_timer_api.rs

@@ -22,10 +22,10 @@ async fn main(_spawner: Spawner) {
         config.rcc.hsi48 = true; // needed for RNG
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
-            divq: Some(8), // 100 Mhz
+            divq: Some(PllDiv::DIV8), // 100mhz
             divr: None,
         });
         config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

examples/stm32h7/src/bin/mco.rs

@@ -5,7 +5,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::gpio::{Level, Output, Speed};
-use embassy_stm32::rcc::{Mco, Mco1Source};
+use embassy_stm32::rcc::{Mco, Mco1Source, McoPrescaler};
 use embassy_time::{Duration, Timer};
 use {defmt_rtt as _, panic_probe as _};
 
@@ -16,7 +16,7 @@ async fn main(_spawner: Spawner) {
 
     let mut led = Output::new(p.PB14, Level::High, Speed::Low);
 
-    let _mco = Mco::new(p.MCO1, p.PA8, Mco1Source::HSI, 8);
+    let _mco = Mco::new(p.MCO1, p.PA8, Mco1Source::HSI, McoPrescaler::DIV8);
 
     loop {
         info!("high");

examples/stm32h7/src/bin/pwm.rs

@@ -21,9 +21,9 @@ async fn main(_spawner: Spawner) {
         config.rcc.csi = true;
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
             divq: None,
             divr: None,
         });

examples/stm32h7/src/bin/rtc.rs

@@ -0,0 +1,37 @@
+#![no_std]
+#![no_main]
+#![feature(type_alias_impl_trait)]
+
+use chrono::{NaiveDate, NaiveDateTime};
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::rcc::LsConfig;
+use embassy_stm32::rtc::{Rtc, RtcConfig};
+use embassy_stm32::Config;
+use embassy_time::{Duration, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.rcc.ls = LsConfig::default_lse();
+
+    let p = embassy_stm32::init(config);
+    info!("Hello World!");
+
+    let now = NaiveDate::from_ymd_opt(2020, 5, 15)
+        .unwrap()
+        .and_hms_opt(10, 30, 15)
+        .unwrap();
+
+    let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
+    info!("Got RTC! {:?}", now.timestamp());
+
+    rtc.set_datetime(now.into()).expect("datetime not set");
+
+    // In reality the delay would be much longer
+    Timer::after(Duration::from_millis(20000)).await;
+
+    let then: NaiveDateTime = rtc.now().unwrap().into();
+    info!("Got RTC! {:?}", then.timestamp());
+}

examples/stm32h7/src/bin/sdmmc.rs

@@ -22,10 +22,10 @@ async fn main(_spawner: Spawner) -> ! {
         config.rcc.csi = true;
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
-            divq: Some(4), // default clock chosen by SDMMCSEL. 200 Mhz
+            divq: Some(PllDiv::DIV4), // default clock chosen by SDMMCSEL. 200 Mhz
             divr: None,
         });
         config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

examples/stm32h7/src/bin/spi.rs

@@ -44,10 +44,10 @@ fn main() -> ! {
         config.rcc.csi = true;
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
-            divq: Some(4), // used by SPI3. 100Mhz.
+            divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
             divr: None,
         });
         config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

examples/stm32h7/src/bin/spi_dma.rs

@@ -40,10 +40,10 @@ fn main() -> ! {
         config.rcc.csi = true;
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
-            divq: Some(4), // used by SPI3. 100Mhz.
+            divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
             divr: None,
         });
         config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

examples/stm32h7/src/bin/usb_serial.rs

@@ -28,9 +28,9 @@ async fn main(_spawner: Spawner) {
         config.rcc.hsi48 = true; // needed for USB
         config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
-            prediv: 4,
+            prediv: PllPreDiv::DIV4,
-            mul: 50,
+            mul: PllMul::MUL50,
-            divp: Some(2),
+            divp: Some(PllDiv::DIV2),
             divq: None,
             divr: None,
         });

examples/stm32l0/Cargo.toml

@@ -24,8 +24,8 @@ defmt = "0.3"
 defmt-rtt = "0.4"
 
 embedded-storage = "0.3.0"
-embedded-io = { version = "0.5.0" }
+embedded-io = { version = "0.6.0" }
-embedded-io-async = { version = "0.5.0", optional = true }
+embedded-io-async = { version = "0.6.0", optional = true }
 
 cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
 cortex-m-rt = "0.7.0"

examples/stm32l4/Cargo.toml

@@ -15,8 +15,8 @@ embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defm
 embassy-net-adin1110 = { version = "0.2.0", path = "../../embassy-net-adin1110" }
 embassy-net = { version = "0.1.0", path = "../../embassy-net", features = ["defmt", "nightly", "udp", "tcp", "dhcpv4", "medium-ethernet"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
-embedded-io-async = { version = "0.5.0", features = ["defmt-03"] }
+embedded-io-async = { version = "0.6.0", features = ["defmt-03"] }
-embedded-io = { version = "0.5.0", features = ["defmt-03"] }
+embedded-io = { version = "0.6.0", features = ["defmt-03"] }
 
 defmt = "0.3"
 defmt-rtt = "0.4"