400 lines
9.6 KiB
Rust
400 lines
9.6 KiB
Rust
use crate::rcc::Clocks;
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use crate::time::{khz, mhz, Hertz};
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/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
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/// and with the addition of the init function to configure a system clock.
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/// Only the basic setup using the HSE and HSI clocks are supported as of now.
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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#[derive(Clone, Copy)]
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pub enum HsePrescaler {
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NotDivided,
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Div2,
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}
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impl From<HsePrescaler> for bool {
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fn from(value: HsePrescaler) -> Self {
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match value {
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HsePrescaler::NotDivided => false,
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HsePrescaler::Div2 => true,
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}
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}
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}
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pub struct Hse {
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pub prediv: HsePrescaler,
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pub frequency: Hertz,
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}
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/// System clock mux source
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#[derive(Clone, Copy, PartialEq)]
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pub enum Sysclk {
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/// MSI selected as sysclk
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MSI,
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/// HSI selected as sysclk
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HSI,
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/// HSE selected as sysclk
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HSE,
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/// PLL selected as sysclk
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Pll,
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}
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impl From<Sysclk> for u8 {
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fn from(value: Sysclk) -> Self {
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match value {
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Sysclk::MSI => 0b00,
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Sysclk::HSI => 0b01,
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Sysclk::HSE => 0b10,
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Sysclk::Pll => 0b11,
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}
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}
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}
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#[derive(Clone, Copy, PartialEq)]
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pub enum PllSource {
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Hsi,
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Msi,
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Hse,
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}
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impl From<PllSource> for u8 {
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fn from(value: PllSource) -> Self {
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match value {
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PllSource::Msi => 0b01,
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PllSource::Hsi => 0b10,
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PllSource::Hse => 0b11,
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}
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}
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}
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pub enum Pll48Source {
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PllSai,
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Pll,
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Msi,
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Hsi48,
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}
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pub struct PllMux {
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/// Source clock selection.
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pub source: PllSource,
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/// PLL pre-divider (DIVM). Must be between 1 and 63.
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pub prediv: u8,
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}
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pub struct Pll {
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/// PLL multiplication factor. Must be between 4 and 512.
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pub mul: u16,
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/// PLL P division factor. If None, PLL P output is disabled. Must be between 1 and 128.
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/// On PLL1, it must be even (in particular, it cannot be 1.)
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pub divp: Option<u16>,
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/// PLL Q division factor. If None, PLL Q output is disabled. Must be between 1 and 128.
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pub divq: Option<u16>,
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/// PLL R division factor. If None, PLL R output is disabled. Must be between 1 and 128.
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pub divr: Option<u16>,
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}
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/// AHB prescaler
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#[derive(Clone, Copy, PartialEq)]
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pub enum AHBPrescaler {
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NotDivided,
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Div2,
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Div3,
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Div4,
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Div5,
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Div6,
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Div8,
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Div10,
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Div16,
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Div32,
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Div64,
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Div128,
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Div256,
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Div512,
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum APBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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}
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impl Into<u8> for APBPrescaler {
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fn into(self) -> u8 {
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match self {
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APBPrescaler::NotDivided => 1,
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APBPrescaler::Div2 => 0x04,
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APBPrescaler::Div4 => 0x05,
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APBPrescaler::Div8 => 0x06,
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APBPrescaler::Div16 => 0x07,
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}
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}
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}
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impl Into<u8> for AHBPrescaler {
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fn into(self) -> u8 {
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match self {
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AHBPrescaler::NotDivided => 0x0,
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AHBPrescaler::Div2 => 0x08,
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AHBPrescaler::Div3 => 0x01,
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AHBPrescaler::Div4 => 0x09,
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AHBPrescaler::Div5 => 0x02,
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AHBPrescaler::Div6 => 0x05,
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AHBPrescaler::Div8 => 0x0a,
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AHBPrescaler::Div10 => 0x06,
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AHBPrescaler::Div16 => 0x0b,
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AHBPrescaler::Div32 => 0x07,
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AHBPrescaler::Div64 => 0x0c,
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AHBPrescaler::Div128 => 0x0d,
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AHBPrescaler::Div256 => 0x0e,
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AHBPrescaler::Div512 => 0x0f,
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}
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}
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}
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/// Clocks configutation
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pub struct Config {
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pub hse: Option<Hse>,
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pub lse: Option<Hertz>,
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pub sys: Sysclk,
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pub mux: Option<PllMux>,
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pub pll48: Option<Pll48Source>,
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pub pll: Option<Pll>,
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pub pllsai: Option<Pll>,
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pub ahb1_pre: AHBPrescaler,
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pub ahb2_pre: AHBPrescaler,
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pub ahb3_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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hse: Some(Hse {
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frequency: mhz(32),
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prediv: HsePrescaler::NotDivided,
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}),
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lse: Some(khz(32)),
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sys: Sysclk::Pll,
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mux: Some(PllMux {
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source: PllSource::Hse,
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prediv: 2,
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}),
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pll48: None,
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pll: Some(Pll {
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mul: 12,
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divp: Some(3),
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divq: Some(4),
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divr: Some(3),
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}),
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pllsai: None,
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ahb1_pre: AHBPrescaler::NotDivided,
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ahb2_pre: AHBPrescaler::Div2,
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ahb3_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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}
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}
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}
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pub(crate) fn compute_clocks(config: &Config) -> Clocks {
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let hse_clk = config.hse.as_ref().map(|hse| match hse.prediv {
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HsePrescaler::NotDivided => hse.frequency,
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HsePrescaler::Div2 => hse.frequency / 2u32,
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});
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let mux_clk = config.mux.as_ref().map(|pll_mux| {
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(match pll_mux.source {
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PllSource::Hse => hse_clk.unwrap(),
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PllSource::Hsi => HSI_FREQ,
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_ => unreachable!(),
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} / pll_mux.prediv)
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});
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let (pll_r, _pll_q, _pll_p) = match &config.pll {
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Some(pll) => {
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let pll_vco = mux_clk.unwrap() * pll.mul as u32;
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(
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pll.divr.map(|divr| pll_vco / divr),
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pll.divq.map(|divq| pll_vco / divq),
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pll.divp.map(|divp| pll_vco / divp),
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)
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}
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None => (None, None, None),
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};
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let sys_clk = match config.sys {
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Sysclk::HSE => hse_clk.unwrap(),
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Sysclk::HSI => HSI_FREQ,
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Sysclk::Pll => pll_r.unwrap(),
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_ => unreachable!(),
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};
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let ahb1_clk = match config.ahb1_pre {
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AHBPrescaler::NotDivided => sys_clk,
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pre => {
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let pre: u8 = pre.into();
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let pre = 1u32 << (pre as u32 - 7);
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sys_clk / pre
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}
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};
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let ahb2_clk = match config.ahb2_pre {
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AHBPrescaler::NotDivided => sys_clk,
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pre => {
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let pre: u8 = pre.into();
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let pre = 1u32 << (pre as u32 - 7);
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sys_clk / pre
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}
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};
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let ahb3_clk = match config.ahb3_pre {
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AHBPrescaler::NotDivided => sys_clk,
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pre => {
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let pre: u8 = pre.into();
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let pre = 1u32 << (pre as u32 - 7);
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sys_clk / pre
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}
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};
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let (apb1_clk, apb1_tim_clk) = match config.apb1_pre {
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APBPrescaler::NotDivided => (ahb1_clk, ahb1_clk),
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pre => {
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let pre: u8 = pre.into();
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let pre: u8 = 1 << (pre - 3);
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let freq = ahb1_clk / pre as u32;
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(freq, freq * 2u32)
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}
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};
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let (apb2_clk, apb2_tim_clk) = match config.apb2_pre {
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APBPrescaler::NotDivided => (ahb1_clk, ahb1_clk),
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pre => {
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let pre: u8 = pre.into();
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let pre: u8 = 1 << (pre - 3);
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let freq = ahb1_clk / pre as u32;
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(freq, freq * 2u32)
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}
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};
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Clocks {
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sys: sys_clk,
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ahb1: ahb1_clk,
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ahb2: ahb2_clk,
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ahb3: ahb3_clk,
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apb1: apb1_clk,
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apb2: apb2_clk,
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apb1_tim: apb1_tim_clk,
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apb2_tim: apb2_tim_clk,
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}
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}
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pub(crate) fn configure_clocks(config: &Config) {
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let pwr = crate::pac::PWR;
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let rcc = crate::pac::RCC;
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let needs_hsi = if let Some(pll_mux) = &config.mux {
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pll_mux.source == PllSource::Hsi
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} else {
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false
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};
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if needs_hsi || config.sys == Sysclk::HSI {
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rcc.cr().modify(|w| {
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w.set_hsion(true);
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});
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while !rcc.cr().read().hsirdy() {}
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}
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match &config.lse {
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Some(_) => {
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rcc.cfgr().modify(|w| w.set_stopwuck(true));
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pwr.cr1().modify(|w| w.set_dbp(true));
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pwr.cr1().modify(|w| w.set_dbp(true));
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rcc.bdcr().modify(|w| w.set_lseon(true));
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}
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_ => {}
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}
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match &config.hse {
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Some(hse) => {
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rcc.cr().modify(|w| {
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w.set_hsepre(hse.prediv.into());
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w.set_hseon(true);
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});
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while !rcc.cr().read().hserdy() {}
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}
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_ => {}
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}
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match &config.mux {
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Some(pll_mux) => {
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rcc.pllcfgr().modify(|w| {
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w.set_pllm(pll_mux.prediv);
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w.set_pllsrc(pll_mux.source.into());
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});
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}
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_ => {}
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};
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match &config.pll {
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Some(pll) => {
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rcc.pllcfgr().modify(|w| {
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w.set_plln(pll.mul as u8);
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pll.divp.map(|divp| {
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w.set_pllpen(true);
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w.set_pllp((divp - 1) as u8)
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});
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pll.divq.map(|divq| {
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w.set_pllqen(true);
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w.set_pllq((divq - 1) as u8)
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});
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pll.divr.map(|divr| {
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// w.set_pllren(true);
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w.set_pllr((divr - 1) as u8);
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});
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});
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rcc.cr().modify(|w| w.set_pllon(true));
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while !rcc.cr().read().pllrdy() {}
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}
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_ => {}
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}
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rcc.cfgr().modify(|w| {
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w.set_sw(config.sys.into());
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w.set_hpre(config.ahb1_pre.into());
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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});
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rcc.extcfgr().modify(|w| {
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w.set_c2hpre(config.ahb2_pre.into());
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w.set_shdhpre(config.ahb3_pre.into());
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});
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}
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