stm32/rcc: fix minor issues
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bd60f003e0
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1425dda0a7
@ -191,7 +191,7 @@ impl Default for Config {
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prediv: HsePrescaler::NotDivided,
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}),
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lse: Some(khz(32)),
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sys: Sysclk::HSI,
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sys: Sysclk::Pll,
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mux: Some(PllMux {
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source: PllSource::Hse,
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prediv: 2,
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@ -363,7 +363,7 @@ pub(crate) fn configure_clocks(config: &Config) {
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match &config.pll {
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Some(pll) => {
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rcc.pllcfgr().modify(|w| {
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w.set_plln((pll.mul - 1) as u8);
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w.set_plln(pll.mul as u8);
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pll.divp.map(|divp| {
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w.set_pllpen(true);
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w.set_pllp((divp - 1) as u8)
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@ -372,7 +372,10 @@ pub(crate) fn configure_clocks(config: &Config) {
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w.set_pllqen(true);
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w.set_pllq((divq - 1) as u8)
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});
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pll.divr.map(|divr| w.set_pllr((divr - 1) as u8));
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pll.divr.map(|divr| {
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// w.set_pllren(true);
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w.set_pllr((divr - 1) as u8);
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});
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});
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rcc.cr().modify(|w| w.set_pllon(true));
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@ -387,9 +390,6 @@ pub(crate) fn configure_clocks(config: &Config) {
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w.set_hpre(config.ahb1_pre.into());
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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});
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rcc.extcfgr().modify(|w| {
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