1321 lines
37 KiB
Rust
1321 lines
37 KiB
Rust
//! GPIO driver.
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#![macro_use]
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use core::convert::Infallible;
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use core::future::Future;
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use core::pin::Pin as FuturePin;
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use core::task::{Context, Poll};
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use embassy_hal_internal::{impl_peripheral, into_ref, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use crate::interrupt::InterruptExt;
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use crate::pac::common::{Reg, RW};
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use crate::pac::SIO;
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use crate::{interrupt, pac, peripherals, Peripheral, RegExt};
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const NEW_AW: AtomicWaker = AtomicWaker::new();
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const BANK0_PIN_COUNT: usize = 30;
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static BANK0_WAKERS: [AtomicWaker; BANK0_PIN_COUNT] = [NEW_AW; BANK0_PIN_COUNT];
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#[cfg(feature = "qspi-as-gpio")]
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const QSPI_PIN_COUNT: usize = 6;
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#[cfg(feature = "qspi-as-gpio")]
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static QSPI_WAKERS: [AtomicWaker; QSPI_PIN_COUNT] = [NEW_AW; QSPI_PIN_COUNT];
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/// Represents a digital input or output level.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Level {
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/// Logical low.
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Low,
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/// Logical high.
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High,
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}
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impl From<bool> for Level {
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fn from(val: bool) -> Self {
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match val {
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true => Self::High,
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false => Self::Low,
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}
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}
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}
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impl From<Level> for bool {
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fn from(level: Level) -> bool {
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match level {
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Level::Low => false,
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Level::High => true,
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}
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}
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}
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/// Represents a pull setting for an input.
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#[derive(Debug, Clone, Copy, Eq, PartialEq)]
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pub enum Pull {
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/// No pull.
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None,
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/// Internal pull-up resistor.
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Up,
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/// Internal pull-down resistor.
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Down,
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}
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/// Drive strength of an output
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#[derive(Debug, Eq, PartialEq)]
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pub enum Drive {
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/// 2 mA drive.
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_2mA,
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/// 4 mA drive.
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_4mA,
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/// 8 mA drive.
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_8mA,
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/// 1 2mA drive.
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_12mA,
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}
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/// Slew rate of an output
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#[derive(Debug, Eq, PartialEq)]
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pub enum SlewRate {
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/// Fast slew rate.
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Fast,
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/// Slow slew rate.
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Slow,
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}
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/// A GPIO bank with up to 32 pins.
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#[derive(Debug, Eq, PartialEq)]
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pub enum Bank {
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/// Bank 0.
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Bank0 = 0,
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/// QSPI.
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#[cfg(feature = "qspi-as-gpio")]
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Qspi = 1,
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}
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/// Dormant mode config.
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#[derive(Debug, Eq, PartialEq, Copy, Clone, Default)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct DormantWakeConfig {
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/// Wake on edge high.
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pub edge_high: bool,
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/// Wake on edge low.
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pub edge_low: bool,
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/// Wake on level high.
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pub level_high: bool,
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/// Wake on level low.
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pub level_low: bool,
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}
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/// GPIO input driver.
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pub struct Input<'d, T: Pin> {
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pin: Flex<'d, T>,
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}
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impl<'d, T: Pin> Input<'d, T> {
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/// Create GPIO input driver for a [Pin] with the provided [Pull] configuration.
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#[inline]
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pub fn new(pin: impl Peripheral<P = T> + 'd, pull: Pull) -> Self {
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let mut pin = Flex::new(pin);
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pin.set_as_input();
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pin.set_pull(pull);
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Self { pin }
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}
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/// Set the pin's Schmitt trigger.
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#[inline]
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pub fn set_schmitt(&mut self, enable: bool) {
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self.pin.set_schmitt(enable)
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}
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/// Get whether the pin input level is high.
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#[inline]
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pub fn is_high(&mut self) -> bool {
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self.pin.is_high()
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}
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/// Get whether the pin input level is low.
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#[inline]
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pub fn is_low(&mut self) -> bool {
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self.pin.is_low()
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}
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/// Returns current pin level
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#[inline]
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pub fn get_level(&mut self) -> Level {
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self.pin.get_level()
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}
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/// Wait until the pin is high. If it is already high, return immediately.
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#[inline]
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pub async fn wait_for_high(&mut self) {
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self.pin.wait_for_high().await;
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}
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/// Wait until the pin is low. If it is already low, return immediately.
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#[inline]
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pub async fn wait_for_low(&mut self) {
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self.pin.wait_for_low().await;
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}
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/// Wait for the pin to undergo a transition from low to high.
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#[inline]
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pub async fn wait_for_rising_edge(&mut self) {
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self.pin.wait_for_rising_edge().await;
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}
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/// Wait for the pin to undergo a transition from high to low.
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#[inline]
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pub async fn wait_for_falling_edge(&mut self) {
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self.pin.wait_for_falling_edge().await;
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}
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/// Wait for the pin to undergo any transition, i.e low to high OR high to low.
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#[inline]
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pub async fn wait_for_any_edge(&mut self) {
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self.pin.wait_for_any_edge().await;
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}
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/// Configure dormant wake.
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#[inline]
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pub fn dormant_wake(&mut self, cfg: DormantWakeConfig) -> DormantWake<T> {
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self.pin.dormant_wake(cfg)
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}
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}
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/// Interrupt trigger levels.
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#[derive(Debug, Eq, PartialEq, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum InterruptTrigger {
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/// Trigger on pin low.
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LevelLow,
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/// Trigger on pin high.
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LevelHigh,
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/// Trigger on high to low transition.
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EdgeLow,
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/// Trigger on low to high transition.
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EdgeHigh,
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/// Trigger on any transition.
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AnyEdge,
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}
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pub(crate) unsafe fn init() {
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interrupt::IO_IRQ_BANK0.disable();
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interrupt::IO_IRQ_BANK0.set_priority(interrupt::Priority::P3);
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interrupt::IO_IRQ_BANK0.enable();
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#[cfg(feature = "qspi-as-gpio")]
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{
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interrupt::IO_IRQ_QSPI.disable();
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interrupt::IO_IRQ_QSPI.set_priority(interrupt::Priority::P3);
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interrupt::IO_IRQ_QSPI.enable();
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}
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}
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#[cfg(feature = "rt")]
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fn irq_handler<const N: usize>(bank: pac::io::Io, wakers: &[AtomicWaker; N]) {
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let cpu = SIO.cpuid().read() as usize;
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// There are two sets of interrupt registers, one for cpu0 and one for cpu1
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// and here we are selecting the set that belongs to the currently executing
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// cpu.
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let proc_intx: pac::io::Int = bank.int_proc(cpu);
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for pin in 0..N {
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// There are 4 raw interrupt status registers, PROCx_INTS0, PROCx_INTS1,
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// PROCx_INTS2, and PROCx_INTS3, and we are selecting the one that the
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// current pin belongs to.
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let intsx = proc_intx.ints(pin / 8);
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// The status register is divided into groups of four, one group for
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// each pin. Each group consists of four trigger levels LEVEL_LOW,
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// LEVEL_HIGH, EDGE_LOW, and EDGE_HIGH for each pin.
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let pin_group = (pin % 8) as usize;
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let event = (intsx.read().0 >> pin_group * 4) & 0xf as u32;
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// no more than one event can be awaited per pin at any given time, so
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// we can just clear all interrupt enables for that pin without having
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// to check which event was signalled.
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if event != 0 {
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proc_intx.inte(pin / 8).write_clear(|w| {
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w.set_edge_high(pin_group, true);
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w.set_edge_low(pin_group, true);
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w.set_level_high(pin_group, true);
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w.set_level_low(pin_group, true);
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});
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wakers[pin as usize].wake();
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}
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}
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}
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#[cfg(feature = "rt")]
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#[interrupt]
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fn IO_IRQ_BANK0() {
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irq_handler(pac::IO_BANK0, &BANK0_WAKERS);
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}
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#[cfg(all(feature = "rt", feature = "qspi-as-gpio"))]
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#[interrupt]
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fn IO_IRQ_QSPI() {
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irq_handler(pac::IO_QSPI, &QSPI_WAKERS);
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}
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#[must_use = "futures do nothing unless you `.await` or poll them"]
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struct InputFuture<'a, T: Pin> {
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pin: PeripheralRef<'a, T>,
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}
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impl<'d, T: Pin> InputFuture<'d, T> {
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/// Create a new future wiating for input trigger.
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pub fn new(pin: impl Peripheral<P = T> + 'd, level: InterruptTrigger) -> Self {
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into_ref!(pin);
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let pin_group = (pin.pin() % 8) as usize;
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// first, clear the INTR register bits. without this INTR will still
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// contain reports of previous edges, causing the IRQ to fire early
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// on stale state. clearing these means that we can only detect edges
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// that occur *after* the clear happened, but since both this and the
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// alternative are fundamentally racy it's probably fine.
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// (the alternative being checking the current level and waiting for
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// its inverse, but that requires reading the current level and thus
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// missing anything that happened before the level was read.)
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pin.io().intr(pin.pin() as usize / 8).write(|w| {
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w.set_edge_high(pin_group, true);
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w.set_edge_low(pin_group, true);
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});
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// Each INTR register is divided into 8 groups, one group for each
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// pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW,
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// and EGDE_HIGH.
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pin.int_proc()
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.inte((pin.pin() / 8) as usize)
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.write_set(|w| match level {
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InterruptTrigger::LevelHigh => {
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w.set_level_high(pin_group, true);
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}
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InterruptTrigger::LevelLow => {
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w.set_level_low(pin_group, true);
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}
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InterruptTrigger::EdgeHigh => {
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w.set_edge_high(pin_group, true);
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}
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InterruptTrigger::EdgeLow => {
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w.set_edge_low(pin_group, true);
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}
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InterruptTrigger::AnyEdge => {
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w.set_edge_high(pin_group, true);
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w.set_edge_low(pin_group, true);
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}
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});
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Self { pin }
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}
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}
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impl<'d, T: Pin> Future for InputFuture<'d, T> {
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type Output = ();
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fn poll(self: FuturePin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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// We need to register/re-register the waker for each poll because any
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// calls to wake will deregister the waker.
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let waker = match self.pin.bank() {
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Bank::Bank0 => &BANK0_WAKERS[self.pin.pin() as usize],
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#[cfg(feature = "qspi-as-gpio")]
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Bank::Qspi => &QSPI_WAKERS[self.pin.pin() as usize],
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};
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waker.register(cx.waker());
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// self.int_proc() will get the register offset for the current cpu,
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// then we want to access the interrupt enable register for our
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// pin (there are 4 of these PROC0_INTE0, PROC0_INTE1, PROC0_INTE2, and
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// PROC0_INTE3 per cpu).
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let inte: pac::io::regs::Int = self.pin.int_proc().inte((self.pin.pin() / 8) as usize).read();
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// The register is divided into groups of four, one group for
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// each pin. Each group consists of four trigger levels LEVEL_LOW,
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// LEVEL_HIGH, EDGE_LOW, and EDGE_HIGH for each pin.
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let pin_group = (self.pin.pin() % 8) as usize;
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// since the interrupt handler clears all INTE flags we'll check that
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// all have been cleared and unconditionally return Ready(()) if so.
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// we don't need further handshaking since only a single event wait
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// is possible for any given pin at any given time.
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if !inte.edge_high(pin_group)
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&& !inte.edge_low(pin_group)
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&& !inte.level_high(pin_group)
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&& !inte.level_low(pin_group)
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{
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return Poll::Ready(());
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}
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Poll::Pending
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}
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}
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/// GPIO output driver.
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pub struct Output<'d, T: Pin> {
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pin: Flex<'d, T>,
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}
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impl<'d, T: Pin> Output<'d, T> {
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/// Create GPIO output driver for a [Pin] with the provided [Level].
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#[inline]
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pub fn new(pin: impl Peripheral<P = T> + 'd, initial_output: Level) -> Self {
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let mut pin = Flex::new(pin);
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match initial_output {
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Level::High => pin.set_high(),
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Level::Low => pin.set_low(),
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}
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pin.set_as_output();
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Self { pin }
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}
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/// Set the pin's drive strength.
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#[inline]
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pub fn set_drive_strength(&mut self, strength: Drive) {
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self.pin.set_drive_strength(strength)
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}
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/// Set the pin's slew rate.
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#[inline]
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pub fn set_slew_rate(&mut self, slew_rate: SlewRate) {
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self.pin.set_slew_rate(slew_rate)
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}
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/// Set the output as high.
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#[inline]
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pub fn set_high(&mut self) {
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self.pin.set_high()
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}
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/// Set the output as low.
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#[inline]
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pub fn set_low(&mut self) {
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self.pin.set_low()
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}
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/// Set the output level.
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#[inline]
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pub fn set_level(&mut self, level: Level) {
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self.pin.set_level(level)
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}
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/// Is the output pin set as high?
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#[inline]
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pub fn is_set_high(&mut self) -> bool {
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self.pin.is_set_high()
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}
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/// Is the output pin set as low?
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#[inline]
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pub fn is_set_low(&mut self) -> bool {
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self.pin.is_set_low()
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}
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/// What level output is set to
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#[inline]
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pub fn get_output_level(&mut self) -> Level {
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self.pin.get_output_level()
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}
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/// Toggle pin output
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#[inline]
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pub fn toggle(&mut self) {
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self.pin.toggle()
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}
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}
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/// GPIO output open-drain.
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pub struct OutputOpenDrain<'d, T: Pin> {
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pin: Flex<'d, T>,
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}
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impl<'d, T: Pin> OutputOpenDrain<'d, T> {
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/// Create GPIO output driver for a [Pin] in open drain mode with the provided [Level].
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#[inline]
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pub fn new(pin: impl Peripheral<P = T> + 'd, initial_output: Level) -> Self {
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let mut pin = Flex::new(pin);
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pin.set_low();
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match initial_output {
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Level::High => pin.set_as_input(),
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Level::Low => pin.set_as_output(),
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}
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Self { pin }
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}
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/// Set the pin's drive strength.
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#[inline]
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pub fn set_drive_strength(&mut self, strength: Drive) {
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self.pin.set_drive_strength(strength)
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}
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/// Set the pin's slew rate.
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#[inline]
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pub fn set_slew_rate(&mut self, slew_rate: SlewRate) {
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self.pin.set_slew_rate(slew_rate)
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}
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/// Set the output as high.
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#[inline]
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pub fn set_high(&mut self) {
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// For Open Drain High, disable the output pin.
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self.pin.set_as_input()
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}
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/// Set the output as low.
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#[inline]
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pub fn set_low(&mut self) {
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// For Open Drain Low, enable the output pin.
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self.pin.set_as_output()
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}
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/// Set the output level.
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#[inline]
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pub fn set_level(&mut self, level: Level) {
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match level {
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Level::Low => self.set_low(),
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Level::High => self.set_high(),
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}
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}
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/// Is the output level high?
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#[inline]
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pub fn is_set_high(&mut self) -> bool {
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!self.is_set_low()
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}
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/// Is the output level low?
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#[inline]
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pub fn is_set_low(&mut self) -> bool {
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self.pin.is_set_as_output()
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}
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/// What level output is set to
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#[inline]
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pub fn get_output_level(&mut self) -> Level {
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self.is_set_high().into()
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}
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/// Toggle pin output
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#[inline]
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pub fn toggle(&mut self) {
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self.pin.toggle_set_as_output()
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}
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/// Get whether the pin input level is high.
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#[inline]
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pub fn is_high(&mut self) -> bool {
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self.pin.is_high()
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}
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/// Get whether the pin input level is low.
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#[inline]
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pub fn is_low(&mut self) -> bool {
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self.pin.is_low()
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}
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/// Returns current pin level
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#[inline]
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pub fn get_level(&mut self) -> Level {
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self.is_high().into()
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}
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/// Wait until the pin is high. If it is already high, return immediately.
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#[inline]
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pub async fn wait_for_high(&mut self) {
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self.pin.wait_for_high().await;
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}
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/// Wait until the pin is low. If it is already low, return immediately.
|
|
#[inline]
|
|
pub async fn wait_for_low(&mut self) {
|
|
self.pin.wait_for_low().await;
|
|
}
|
|
|
|
/// Wait for the pin to undergo a transition from low to high.
|
|
#[inline]
|
|
pub async fn wait_for_rising_edge(&mut self) {
|
|
self.pin.wait_for_rising_edge().await;
|
|
}
|
|
|
|
/// Wait for the pin to undergo a transition from high to low.
|
|
#[inline]
|
|
pub async fn wait_for_falling_edge(&mut self) {
|
|
self.pin.wait_for_falling_edge().await;
|
|
}
|
|
|
|
/// Wait for the pin to undergo any transition, i.e low to high OR high to low.
|
|
#[inline]
|
|
pub async fn wait_for_any_edge(&mut self) {
|
|
self.pin.wait_for_any_edge().await;
|
|
}
|
|
}
|
|
|
|
/// GPIO flexible pin.
|
|
///
|
|
/// This pin can be either an input or output pin. The output level register bit will remain
|
|
/// set while not in output mode, so the pin's level will be 'remembered' when it is not in output
|
|
/// mode.
|
|
pub struct Flex<'d, T: Pin> {
|
|
pin: PeripheralRef<'d, T>,
|
|
}
|
|
|
|
impl<'d, T: Pin> Flex<'d, T> {
|
|
/// Wrap the pin in a `Flex`.
|
|
///
|
|
/// The pin remains disconnected. The initial output level is unspecified, but can be changed
|
|
/// before the pin is put into output mode.
|
|
#[inline]
|
|
pub fn new(pin: impl Peripheral<P = T> + 'd) -> Self {
|
|
into_ref!(pin);
|
|
|
|
pin.pad_ctrl().write(|w| {
|
|
w.set_ie(true);
|
|
});
|
|
|
|
pin.gpio().ctrl().write(|w| {
|
|
w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0 as _);
|
|
});
|
|
|
|
Self { pin }
|
|
}
|
|
|
|
#[inline]
|
|
fn bit(&self) -> u32 {
|
|
1 << self.pin.pin()
|
|
}
|
|
|
|
/// Set the pin's pull.
|
|
#[inline]
|
|
pub fn set_pull(&mut self, pull: Pull) {
|
|
self.pin.pad_ctrl().modify(|w| {
|
|
w.set_ie(true);
|
|
let (pu, pd) = match pull {
|
|
Pull::Up => (true, false),
|
|
Pull::Down => (false, true),
|
|
Pull::None => (false, false),
|
|
};
|
|
w.set_pue(pu);
|
|
w.set_pde(pd);
|
|
});
|
|
}
|
|
|
|
/// Set the pin's drive strength.
|
|
#[inline]
|
|
pub fn set_drive_strength(&mut self, strength: Drive) {
|
|
self.pin.pad_ctrl().modify(|w| {
|
|
w.set_drive(match strength {
|
|
Drive::_2mA => pac::pads::vals::Drive::_2MA,
|
|
Drive::_4mA => pac::pads::vals::Drive::_4MA,
|
|
Drive::_8mA => pac::pads::vals::Drive::_8MA,
|
|
Drive::_12mA => pac::pads::vals::Drive::_12MA,
|
|
});
|
|
});
|
|
}
|
|
|
|
/// Set the pin's slew rate.
|
|
#[inline]
|
|
pub fn set_slew_rate(&mut self, slew_rate: SlewRate) {
|
|
self.pin.pad_ctrl().modify(|w| {
|
|
w.set_slewfast(slew_rate == SlewRate::Fast);
|
|
});
|
|
}
|
|
|
|
/// Set the pin's Schmitt trigger.
|
|
#[inline]
|
|
pub fn set_schmitt(&mut self, enable: bool) {
|
|
self.pin.pad_ctrl().modify(|w| {
|
|
w.set_schmitt(enable);
|
|
});
|
|
}
|
|
|
|
/// Put the pin into input mode.
|
|
///
|
|
/// The pull setting is left unchanged.
|
|
#[inline]
|
|
pub fn set_as_input(&mut self) {
|
|
self.pin.sio_oe().value_clr().write_value(self.bit())
|
|
}
|
|
|
|
/// Put the pin into output mode.
|
|
///
|
|
/// The pin level will be whatever was set before (or low by default). If you want it to begin
|
|
/// at a specific level, call `set_high`/`set_low` on the pin first.
|
|
#[inline]
|
|
pub fn set_as_output(&mut self) {
|
|
self.pin.sio_oe().value_set().write_value(self.bit())
|
|
}
|
|
|
|
/// Set as output pin.
|
|
#[inline]
|
|
pub fn is_set_as_output(&mut self) -> bool {
|
|
self.ref_is_set_as_output()
|
|
}
|
|
|
|
#[inline]
|
|
pub(crate) fn ref_is_set_as_output(&self) -> bool {
|
|
(self.pin.sio_oe().value().read() & self.bit()) != 0
|
|
}
|
|
|
|
/// Toggle output pin.
|
|
#[inline]
|
|
pub fn toggle_set_as_output(&mut self) {
|
|
self.pin.sio_oe().value_xor().write_value(self.bit())
|
|
}
|
|
|
|
/// Get whether the pin input level is high.
|
|
#[inline]
|
|
pub fn is_high(&mut self) -> bool {
|
|
!self.is_low()
|
|
}
|
|
/// Get whether the pin input level is low.
|
|
|
|
#[inline]
|
|
pub fn is_low(&mut self) -> bool {
|
|
self.ref_is_low()
|
|
}
|
|
|
|
#[inline]
|
|
pub(crate) fn ref_is_low(&self) -> bool {
|
|
self.pin.sio_in().read() & self.bit() == 0
|
|
}
|
|
|
|
/// Returns current pin level
|
|
#[inline]
|
|
pub fn get_level(&mut self) -> Level {
|
|
self.is_high().into()
|
|
}
|
|
|
|
/// Set the output as high.
|
|
#[inline]
|
|
pub fn set_high(&mut self) {
|
|
self.pin.sio_out().value_set().write_value(self.bit())
|
|
}
|
|
|
|
/// Set the output as low.
|
|
#[inline]
|
|
pub fn set_low(&mut self) {
|
|
self.pin.sio_out().value_clr().write_value(self.bit())
|
|
}
|
|
|
|
/// Set the output level.
|
|
#[inline]
|
|
pub fn set_level(&mut self, level: Level) {
|
|
match level {
|
|
Level::Low => self.set_low(),
|
|
Level::High => self.set_high(),
|
|
}
|
|
}
|
|
|
|
/// Is the output level high?
|
|
#[inline]
|
|
pub fn is_set_high(&mut self) -> bool {
|
|
!self.is_set_low()
|
|
}
|
|
|
|
/// Is the output level low?
|
|
#[inline]
|
|
pub fn is_set_low(&mut self) -> bool {
|
|
self.ref_is_set_low()
|
|
}
|
|
|
|
#[inline]
|
|
pub(crate) fn ref_is_set_low(&self) -> bool {
|
|
(self.pin.sio_out().value().read() & self.bit()) == 0
|
|
}
|
|
|
|
/// What level output is set to
|
|
#[inline]
|
|
pub fn get_output_level(&mut self) -> Level {
|
|
self.is_set_high().into()
|
|
}
|
|
|
|
/// Toggle pin output
|
|
#[inline]
|
|
pub fn toggle(&mut self) {
|
|
self.pin.sio_out().value_xor().write_value(self.bit())
|
|
}
|
|
|
|
/// Wait until the pin is high. If it is already high, return immediately.
|
|
#[inline]
|
|
pub async fn wait_for_high(&mut self) {
|
|
InputFuture::new(&mut self.pin, InterruptTrigger::LevelHigh).await;
|
|
}
|
|
|
|
/// Wait until the pin is low. If it is already low, return immediately.
|
|
#[inline]
|
|
pub async fn wait_for_low(&mut self) {
|
|
InputFuture::new(&mut self.pin, InterruptTrigger::LevelLow).await;
|
|
}
|
|
|
|
/// Wait for the pin to undergo a transition from low to high.
|
|
#[inline]
|
|
pub async fn wait_for_rising_edge(&mut self) {
|
|
InputFuture::new(&mut self.pin, InterruptTrigger::EdgeHigh).await;
|
|
}
|
|
|
|
/// Wait for the pin to undergo a transition from high to low.
|
|
#[inline]
|
|
pub async fn wait_for_falling_edge(&mut self) {
|
|
InputFuture::new(&mut self.pin, InterruptTrigger::EdgeLow).await;
|
|
}
|
|
|
|
/// Wait for the pin to undergo any transition, i.e low to high OR high to low.
|
|
#[inline]
|
|
pub async fn wait_for_any_edge(&mut self) {
|
|
InputFuture::new(&mut self.pin, InterruptTrigger::AnyEdge).await;
|
|
}
|
|
|
|
/// Configure dormant wake.
|
|
#[inline]
|
|
pub fn dormant_wake(&mut self, cfg: DormantWakeConfig) -> DormantWake<T> {
|
|
let idx = self.pin._pin() as usize;
|
|
self.pin.io().intr(idx / 8).write(|w| {
|
|
w.set_edge_high(idx % 8, cfg.edge_high);
|
|
w.set_edge_low(idx % 8, cfg.edge_low);
|
|
});
|
|
self.pin.io().int_dormant_wake().inte(idx / 8).write_set(|w| {
|
|
w.set_edge_high(idx % 8, cfg.edge_high);
|
|
w.set_edge_low(idx % 8, cfg.edge_low);
|
|
w.set_level_high(idx % 8, cfg.level_high);
|
|
w.set_level_low(idx % 8, cfg.level_low);
|
|
});
|
|
DormantWake {
|
|
pin: self.pin.reborrow(),
|
|
cfg,
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> Drop for Flex<'d, T> {
|
|
#[inline]
|
|
fn drop(&mut self) {
|
|
let idx = self.pin._pin() as usize;
|
|
self.pin.pad_ctrl().write(|_| {});
|
|
self.pin.gpio().ctrl().write(|w| {
|
|
w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _);
|
|
});
|
|
self.pin.io().int_dormant_wake().inte(idx / 8).write_clear(|w| {
|
|
w.set_edge_high(idx % 8, true);
|
|
w.set_edge_low(idx % 8, true);
|
|
w.set_level_high(idx % 8, true);
|
|
w.set_level_low(idx % 8, true);
|
|
});
|
|
}
|
|
}
|
|
|
|
/// Dormant wake driver.
|
|
pub struct DormantWake<'w, T: Pin> {
|
|
pin: PeripheralRef<'w, T>,
|
|
cfg: DormantWakeConfig,
|
|
}
|
|
|
|
impl<'w, T: Pin> Drop for DormantWake<'w, T> {
|
|
fn drop(&mut self) {
|
|
let idx = self.pin._pin() as usize;
|
|
self.pin.io().intr(idx / 8).write(|w| {
|
|
w.set_edge_high(idx % 8, self.cfg.edge_high);
|
|
w.set_edge_low(idx % 8, self.cfg.edge_low);
|
|
});
|
|
self.pin.io().int_dormant_wake().inte(idx / 8).write_clear(|w| {
|
|
w.set_edge_high(idx % 8, true);
|
|
w.set_edge_low(idx % 8, true);
|
|
w.set_level_high(idx % 8, true);
|
|
w.set_level_low(idx % 8, true);
|
|
});
|
|
}
|
|
}
|
|
|
|
pub(crate) mod sealed {
|
|
use super::*;
|
|
|
|
pub trait Pin: Sized {
|
|
fn pin_bank(&self) -> u8;
|
|
|
|
#[inline]
|
|
fn _pin(&self) -> u8 {
|
|
self.pin_bank() & 0x1f
|
|
}
|
|
|
|
#[inline]
|
|
fn _bank(&self) -> Bank {
|
|
match self.pin_bank() & 0x20 {
|
|
#[cfg(feature = "qspi-as-gpio")]
|
|
1 => Bank::Qspi,
|
|
_ => Bank::Bank0,
|
|
}
|
|
}
|
|
|
|
fn io(&self) -> pac::io::Io {
|
|
match self._bank() {
|
|
Bank::Bank0 => crate::pac::IO_BANK0,
|
|
#[cfg(feature = "qspi-as-gpio")]
|
|
Bank::Qspi => crate::pac::IO_QSPI,
|
|
}
|
|
}
|
|
|
|
fn gpio(&self) -> pac::io::Gpio {
|
|
self.io().gpio(self._pin() as _)
|
|
}
|
|
|
|
fn pad_ctrl(&self) -> Reg<pac::pads::regs::GpioCtrl, RW> {
|
|
let block = match self._bank() {
|
|
Bank::Bank0 => crate::pac::PADS_BANK0,
|
|
#[cfg(feature = "qspi-as-gpio")]
|
|
Bank::Qspi => crate::pac::PADS_QSPI,
|
|
};
|
|
block.gpio(self._pin() as _)
|
|
}
|
|
|
|
fn sio_out(&self) -> pac::sio::Gpio {
|
|
SIO.gpio_out(self._bank() as _)
|
|
}
|
|
|
|
fn sio_oe(&self) -> pac::sio::Gpio {
|
|
SIO.gpio_oe(self._bank() as _)
|
|
}
|
|
|
|
fn sio_in(&self) -> Reg<u32, RW> {
|
|
SIO.gpio_in(self._bank() as _)
|
|
}
|
|
|
|
fn int_proc(&self) -> pac::io::Int {
|
|
let proc = SIO.cpuid().read();
|
|
self.io().int_proc(proc as _)
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Interface for a Pin that can be configured by an [Input] or [Output] driver, or converted to an [AnyPin].
|
|
pub trait Pin: Peripheral<P = Self> + Into<AnyPin> + sealed::Pin + Sized + 'static {
|
|
/// Degrade to a generic pin struct
|
|
fn degrade(self) -> AnyPin {
|
|
AnyPin {
|
|
pin_bank: self.pin_bank(),
|
|
}
|
|
}
|
|
|
|
/// Returns the pin number within a bank
|
|
#[inline]
|
|
fn pin(&self) -> u8 {
|
|
self._pin()
|
|
}
|
|
|
|
/// Returns the bank of this pin
|
|
#[inline]
|
|
fn bank(&self) -> Bank {
|
|
self._bank()
|
|
}
|
|
}
|
|
|
|
/// Type-erased GPIO pin
|
|
pub struct AnyPin {
|
|
pin_bank: u8,
|
|
}
|
|
|
|
impl_peripheral!(AnyPin);
|
|
|
|
impl Pin for AnyPin {}
|
|
impl sealed::Pin for AnyPin {
|
|
fn pin_bank(&self) -> u8 {
|
|
self.pin_bank
|
|
}
|
|
}
|
|
|
|
// ==========================
|
|
|
|
macro_rules! impl_pin {
|
|
($name:ident, $bank:expr, $pin_num:expr) => {
|
|
impl Pin for peripherals::$name {}
|
|
impl sealed::Pin for peripherals::$name {
|
|
#[inline]
|
|
fn pin_bank(&self) -> u8 {
|
|
($bank as u8) * 32 + $pin_num
|
|
}
|
|
}
|
|
|
|
impl From<peripherals::$name> for crate::gpio::AnyPin {
|
|
fn from(val: peripherals::$name) -> Self {
|
|
crate::gpio::Pin::degrade(val)
|
|
}
|
|
}
|
|
};
|
|
}
|
|
|
|
impl_pin!(PIN_0, Bank::Bank0, 0);
|
|
impl_pin!(PIN_1, Bank::Bank0, 1);
|
|
impl_pin!(PIN_2, Bank::Bank0, 2);
|
|
impl_pin!(PIN_3, Bank::Bank0, 3);
|
|
impl_pin!(PIN_4, Bank::Bank0, 4);
|
|
impl_pin!(PIN_5, Bank::Bank0, 5);
|
|
impl_pin!(PIN_6, Bank::Bank0, 6);
|
|
impl_pin!(PIN_7, Bank::Bank0, 7);
|
|
impl_pin!(PIN_8, Bank::Bank0, 8);
|
|
impl_pin!(PIN_9, Bank::Bank0, 9);
|
|
impl_pin!(PIN_10, Bank::Bank0, 10);
|
|
impl_pin!(PIN_11, Bank::Bank0, 11);
|
|
impl_pin!(PIN_12, Bank::Bank0, 12);
|
|
impl_pin!(PIN_13, Bank::Bank0, 13);
|
|
impl_pin!(PIN_14, Bank::Bank0, 14);
|
|
impl_pin!(PIN_15, Bank::Bank0, 15);
|
|
impl_pin!(PIN_16, Bank::Bank0, 16);
|
|
impl_pin!(PIN_17, Bank::Bank0, 17);
|
|
impl_pin!(PIN_18, Bank::Bank0, 18);
|
|
impl_pin!(PIN_19, Bank::Bank0, 19);
|
|
impl_pin!(PIN_20, Bank::Bank0, 20);
|
|
impl_pin!(PIN_21, Bank::Bank0, 21);
|
|
impl_pin!(PIN_22, Bank::Bank0, 22);
|
|
impl_pin!(PIN_23, Bank::Bank0, 23);
|
|
impl_pin!(PIN_24, Bank::Bank0, 24);
|
|
impl_pin!(PIN_25, Bank::Bank0, 25);
|
|
impl_pin!(PIN_26, Bank::Bank0, 26);
|
|
impl_pin!(PIN_27, Bank::Bank0, 27);
|
|
impl_pin!(PIN_28, Bank::Bank0, 28);
|
|
impl_pin!(PIN_29, Bank::Bank0, 29);
|
|
|
|
#[cfg(feature = "qspi-as-gpio")]
|
|
impl_pin!(PIN_QSPI_SCLK, Bank::Qspi, 0);
|
|
#[cfg(feature = "qspi-as-gpio")]
|
|
impl_pin!(PIN_QSPI_SS, Bank::Qspi, 1);
|
|
#[cfg(feature = "qspi-as-gpio")]
|
|
impl_pin!(PIN_QSPI_SD0, Bank::Qspi, 2);
|
|
#[cfg(feature = "qspi-as-gpio")]
|
|
impl_pin!(PIN_QSPI_SD1, Bank::Qspi, 3);
|
|
#[cfg(feature = "qspi-as-gpio")]
|
|
impl_pin!(PIN_QSPI_SD2, Bank::Qspi, 4);
|
|
#[cfg(feature = "qspi-as-gpio")]
|
|
impl_pin!(PIN_QSPI_SD3, Bank::Qspi, 5);
|
|
|
|
// ====================
|
|
|
|
mod eh02 {
|
|
use core::convert::Infallible;
|
|
|
|
use super::*;
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Input<'d, T> {
|
|
type Error = Infallible;
|
|
|
|
fn is_high(&self) -> Result<bool, Self::Error> {
|
|
Ok(!self.pin.ref_is_low())
|
|
}
|
|
|
|
fn is_low(&self) -> Result<bool, Self::Error> {
|
|
Ok(self.pin.ref_is_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Output<'d, T> {
|
|
type Error = Infallible;
|
|
|
|
fn set_high(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_high())
|
|
}
|
|
|
|
fn set_low(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Output<'d, T> {
|
|
fn is_set_high(&self) -> Result<bool, Self::Error> {
|
|
Ok(!self.pin.ref_is_set_low())
|
|
}
|
|
|
|
fn is_set_low(&self) -> Result<bool, Self::Error> {
|
|
Ok(self.pin.ref_is_set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Output<'d, T> {
|
|
type Error = Infallible;
|
|
#[inline]
|
|
fn toggle(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.toggle())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for OutputOpenDrain<'d, T> {
|
|
type Error = Infallible;
|
|
|
|
fn is_high(&self) -> Result<bool, Self::Error> {
|
|
Ok(!self.pin.ref_is_low())
|
|
}
|
|
|
|
fn is_low(&self) -> Result<bool, Self::Error> {
|
|
Ok(self.pin.ref_is_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for OutputOpenDrain<'d, T> {
|
|
type Error = Infallible;
|
|
|
|
#[inline]
|
|
fn set_high(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_high())
|
|
}
|
|
|
|
#[inline]
|
|
fn set_low(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for OutputOpenDrain<'d, T> {
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|
fn is_set_high(&self) -> Result<bool, Self::Error> {
|
|
Ok(!self.pin.ref_is_set_as_output())
|
|
}
|
|
|
|
fn is_set_low(&self) -> Result<bool, Self::Error> {
|
|
Ok(self.pin.ref_is_set_as_output())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for OutputOpenDrain<'d, T> {
|
|
type Error = Infallible;
|
|
#[inline]
|
|
fn toggle(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.toggle())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Flex<'d, T> {
|
|
type Error = Infallible;
|
|
|
|
fn is_high(&self) -> Result<bool, Self::Error> {
|
|
Ok(!self.ref_is_low())
|
|
}
|
|
|
|
fn is_low(&self) -> Result<bool, Self::Error> {
|
|
Ok(self.ref_is_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Flex<'d, T> {
|
|
type Error = Infallible;
|
|
|
|
fn set_high(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_high())
|
|
}
|
|
|
|
fn set_low(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'d, T> {
|
|
fn is_set_high(&self) -> Result<bool, Self::Error> {
|
|
Ok(!self.ref_is_set_low())
|
|
}
|
|
|
|
fn is_set_low(&self) -> Result<bool, Self::Error> {
|
|
Ok(self.ref_is_set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'d, T> {
|
|
type Error = Infallible;
|
|
#[inline]
|
|
fn toggle(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.toggle())
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Input<'d, T> {
|
|
type Error = Infallible;
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Input<'d, T> {
|
|
fn is_high(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_high())
|
|
}
|
|
|
|
fn is_low(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Output<'d, T> {
|
|
type Error = Infallible;
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Output<'d, T> {
|
|
fn set_high(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_high())
|
|
}
|
|
|
|
fn set_low(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Output<'d, T> {
|
|
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_set_high())
|
|
}
|
|
|
|
fn is_set_low(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::ToggleableOutputPin for Output<'d, T> {
|
|
fn toggle(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.toggle())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for OutputOpenDrain<'d, T> {
|
|
type Error = Infallible;
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for OutputOpenDrain<'d, T> {
|
|
fn set_high(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_high())
|
|
}
|
|
|
|
fn set_low(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for OutputOpenDrain<'d, T> {
|
|
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_set_high())
|
|
}
|
|
|
|
fn is_set_low(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::ToggleableOutputPin for OutputOpenDrain<'d, T> {
|
|
fn toggle(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.toggle())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::InputPin for OutputOpenDrain<'d, T> {
|
|
fn is_high(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_high())
|
|
}
|
|
|
|
fn is_low(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Flex<'d, T> {
|
|
type Error = Infallible;
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Flex<'d, T> {
|
|
fn is_high(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_high())
|
|
}
|
|
|
|
fn is_low(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Flex<'d, T> {
|
|
fn set_high(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_high())
|
|
}
|
|
|
|
fn set_low(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Flex<'d, T> {
|
|
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_set_high())
|
|
}
|
|
|
|
fn is_set_low(&mut self) -> Result<bool, Self::Error> {
|
|
Ok(self.is_set_low())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_1::digital::ToggleableOutputPin for Flex<'d, T> {
|
|
fn toggle(&mut self) -> Result<(), Self::Error> {
|
|
Ok(self.toggle())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_async::digital::Wait for Flex<'d, T> {
|
|
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_high().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_low().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_rising_edge().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_falling_edge().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_any_edge().await;
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_async::digital::Wait for Input<'d, T> {
|
|
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_high().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_low().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_rising_edge().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_falling_edge().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_any_edge().await;
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Pin> embedded_hal_async::digital::Wait for OutputOpenDrain<'d, T> {
|
|
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_high().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_low().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_rising_edge().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_falling_edge().await;
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
|
|
self.wait_for_any_edge().await;
|
|
Ok(())
|
|
}
|
|
}
|