526 lines
15 KiB
Rust
526 lines
15 KiB
Rust
use crate::pac::rcc::regs::Cfgr;
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
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#[cfg(any(stm32wb, stm32wl))]
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pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
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pub use crate::pac::rcc::vals::{
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Adcsel as AdcClockSource, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul,
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Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
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};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1)
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Bypass,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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/// HSE prescaler
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#[cfg(any(stm32wb, stm32wl))]
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pub prescaler: HsePrescaler,
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}
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#[derive(Clone, Copy)]
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pub struct Pll {
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/// PLL source
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pub source: PLLSource,
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/// PLL pre-divider (DIVM).
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pub prediv: PllPreDiv,
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/// PLL multiplication factor.
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pub mul: PllMul,
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/// PLL P division factor. If None, PLL P output is disabled.
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pub divp: Option<PllPDiv>,
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/// PLL Q division factor. If None, PLL Q output is disabled.
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pub divq: Option<PllQDiv>,
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/// PLL R division factor. If None, PLL R output is disabled.
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pub divr: Option<PllRDiv>,
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}
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/// Clocks configuration
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pub struct Config {
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// base clock sources
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pub msi: Option<MSIRange>,
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pub hsi: bool,
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pub hse: Option<Hse>,
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#[cfg(crs)]
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pub hsi48: Option<super::Hsi48Config>,
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// pll
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pub pll: Option<Pll>,
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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pub pllsai1: Option<Pll>,
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#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
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pub pllsai2: Option<Pll>,
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// sysclk, buses.
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pub mux: ClockSrc,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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#[cfg(any(stm32wl5x, stm32wb))]
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pub core2_ahb_pre: AHBPrescaler,
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#[cfg(any(stm32wl, stm32wb))]
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pub shared_ahb_pre: AHBPrescaler,
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// muxes
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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pub clk48_src: Clk48Src,
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// low speed LSI/LSE/RTC
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pub ls: super::LsConfig,
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pub adc_clock_source: AdcClockSource,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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hse: None,
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hsi: false,
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msi: Some(MSIRange::RANGE4M),
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mux: ClockSrc::MSI,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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#[cfg(any(stm32wl5x, stm32wb))]
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core2_ahb_pre: AHBPrescaler::DIV1,
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#[cfg(any(stm32wl, stm32wb))]
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shared_ahb_pre: AHBPrescaler::DIV1,
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pll: None,
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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pllsai1: None,
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#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
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pllsai2: None,
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#[cfg(crs)]
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hsi48: Some(Default::default()),
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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clk48_src: Clk48Src::HSI48,
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ls: Default::default(),
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adc_clock_source: AdcClockSource::SYS,
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}
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}
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}
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#[cfg(stm32wb)]
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pub const WPAN_DEFAULT: Config = Config {
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hse: Some(Hse {
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freq: Hertz(32_000_000),
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mode: HseMode::Oscillator,
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prescaler: HsePrescaler::DIV1,
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}),
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mux: ClockSrc::PLL1_R,
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#[cfg(crs)]
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hsi48: Some(super::Hsi48Config { sync_from_usb: false }),
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msi: None,
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hsi: false,
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clk48_src: Clk48Src::PLL1_Q,
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ls: super::LsConfig::default_lse(),
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pll: Some(Pll {
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source: PLLSource::HSE,
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prediv: PllPreDiv::DIV2,
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mul: PllMul::MUL12,
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divp: Some(PllPDiv::DIV3), // 32 / 2 * 12 / 3 = 64Mhz
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divq: Some(PllQDiv::DIV4), // 32 / 2 * 12 / 4 = 48Mhz
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divr: Some(PllRDiv::DIV3), // 32 / 2 * 12 / 3 = 64Mhz
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}),
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pllsai1: None,
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ahb_pre: AHBPrescaler::DIV1,
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core2_ahb_pre: AHBPrescaler::DIV2,
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shared_ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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adc_clock_source: AdcClockSource::SYS,
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};
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pub(crate) unsafe fn init(config: Config) {
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// Switch to MSI to prevent problems with PLL configuration.
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if !RCC.cr().read().msion() {
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// Turn on MSI and configure it to 4MHz.
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RCC.cr().modify(|w| {
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#[cfg(not(stm32wb))]
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w.set_msirgsel(crate::pac::rcc::vals::Msirgsel::CR);
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w.set_msirange(MSIRange::RANGE4M);
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w.set_msipllen(false);
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w.set_msion(true)
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});
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// Wait until MSI is running
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while !RCC.cr().read().msirdy() {}
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}
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if RCC.cfgr().read().sws() != ClockSrc::MSI {
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// Set MSI as a clock source, reset prescalers.
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RCC.cfgr().write_value(Cfgr::default());
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// Wait for clock switch status bits to change.
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while RCC.cfgr().read().sws() != ClockSrc::MSI {}
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}
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#[cfg(stm32l5)]
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crate::pac::PWR.cr1().modify(|w| {
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w.set_vos(crate::pac::pwr::vals::Vos::RANGE0);
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});
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let rtc = config.ls.init();
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let msi = config.msi.map(|range| {
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// Enable MSI
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RCC.cr().modify(|w| {
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#[cfg(not(stm32wb))]
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w.set_msirgsel(crate::pac::rcc::vals::Msirgsel::CR);
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w.set_msirange(range);
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w.set_msion(true);
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// If LSE is enabled, enable calibration of MSI
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w.set_msipllen(config.ls.lse.is_some());
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});
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while !RCC.cr().read().msirdy() {}
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msirange_to_hertz(range)
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});
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let hsi = config.hsi.then(|| {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ
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});
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let hse = config.hse.map(|hse| {
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RCC.cr().modify(|w| {
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#[cfg(stm32wl)]
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w.set_hsebyppwr(hse.mode == HseMode::Bypass);
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#[cfg(not(stm32wl))]
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w.set_hsebyp(hse.mode == HseMode::Bypass);
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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hse.freq
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});
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#[cfg(crs)]
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let _hsi48 = config.hsi48.map(super::init_hsi48);
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#[cfg(not(crs))]
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let _hsi48: Option<Hertz> = None;
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let _plls = [
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&config.pll,
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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&config.pllsai1,
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#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
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&config.pllsai2,
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];
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// L4 has shared PLLSRC, PLLM, check it's equal in all PLLs.
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#[cfg(all(stm32l4, not(rcc_l4plus)))]
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match super::util::get_equal(_plls.into_iter().flatten().map(|p| (p.source, p.prediv))) {
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Err(()) => panic!("Source must be equal across all enabled PLLs."),
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Ok(None) => {}
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Ok(Some((source, prediv))) => RCC.pllcfgr().write(|w| {
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w.set_pllm(prediv);
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w.set_pllsrc(source);
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}),
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};
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// L4+, WL has shared PLLSRC, check it's equal in all PLLs.
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#[cfg(any(rcc_l4plus, stm32wl))]
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match super::util::get_equal(_plls.into_iter().flatten().map(|p| p.source)) {
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Err(()) => panic!("Source must be equal across all enabled PLLs."),
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Ok(None) => {}
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Ok(Some(source)) => RCC.pllcfgr().write(|w| {
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w.set_pllsrc(source);
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}),
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};
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let pll_input = PllInput { hse, hsi, msi };
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let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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let pllsai1 = init_pll(PllInstance::Pllsai1, config.pllsai1, &pll_input);
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#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
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let _pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input);
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let sys_clk = match config.mux {
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ClockSrc::HSE => hse.unwrap(),
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ClockSrc::HSI => hsi.unwrap(),
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ClockSrc::MSI => msi.unwrap(),
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ClockSrc::PLL1_R => pll.r.unwrap(),
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};
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#[cfg(stm32l4)]
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RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src));
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#[cfg(stm32l5)]
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RCC.ccipr1().modify(|w| w.set_clk48sel(config.clk48_src));
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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let _clk48 = match config.clk48_src {
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Clk48Src::HSI48 => _hsi48,
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Clk48Src::MSI => msi,
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Clk48Src::PLLSAI1_Q => pllsai1.q,
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Clk48Src::PLL1_Q => pll.q,
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};
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#[cfg(rcc_l4plus)]
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assert!(sys_clk.0 <= 120_000_000);
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#[cfg(all(stm32l4, not(rcc_l4plus)))]
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assert!(sys_clk.0 <= 80_000_000);
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let hclk1 = sys_clk / config.ahb_pre;
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let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk1, config.apb1_pre);
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let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk1, config.apb2_pre);
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#[cfg(not(any(stm32wl5x, stm32wb)))]
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let hclk2 = hclk1;
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#[cfg(any(stm32wl5x, stm32wb))]
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let hclk2 = sys_clk / config.core2_ahb_pre;
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#[cfg(not(any(stm32wl, stm32wb)))]
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let hclk3 = hclk1;
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#[cfg(any(stm32wl, stm32wb))]
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let hclk3 = sys_clk / config.shared_ahb_pre;
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// Set flash wait states
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#[cfg(stm32l4)]
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let latency = match hclk1.0 {
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0..=16_000_000 => 0,
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0..=32_000_000 => 1,
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0..=48_000_000 => 2,
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0..=64_000_000 => 3,
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_ => 4,
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};
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#[cfg(stm32l5)]
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let latency = match hclk1.0 {
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// VCORE Range 0 (performance), others TODO
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0..=20_000_000 => 0,
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0..=40_000_000 => 1,
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0..=60_000_000 => 2,
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0..=80_000_000 => 3,
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0..=100_000_000 => 4,
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_ => 5,
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};
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#[cfg(stm32wl)]
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let latency = match hclk3.0 {
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// VOS RANGE1, others TODO.
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..=18_000_000 => 0,
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..=36_000_000 => 1,
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_ => 2,
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};
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#[cfg(stm32wb)]
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let latency = match hclk3.0 {
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// VOS RANGE1, others TODO.
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..=18_000_000 => 0,
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..=36_000_000 => 1,
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..=54_000_000 => 2,
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..=64_000_000 => 3,
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_ => 4,
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};
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FLASH.acr().modify(|w| w.set_latency(latency));
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while FLASH.acr().read().latency() != latency {}
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RCC.cfgr().modify(|w| {
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w.set_sw(config.mux);
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w.set_hpre(config.ahb_pre);
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w.set_ppre1(config.apb1_pre);
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w.set_ppre2(config.apb2_pre);
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});
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while RCC.cfgr().read().sws() != config.mux {}
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#[cfg(stm32l5)]
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RCC.ccipr1().modify(|w| w.set_adcsel(config.adc_clock_source));
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#[cfg(not(stm32l5))]
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RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source));
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#[cfg(any(stm32wl, stm32wb))]
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{
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RCC.extcfgr().modify(|w| {
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w.set_shdhpre(config.shared_ahb_pre);
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#[cfg(any(stm32wl5x, stm32wb))]
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w.set_c2hpre(config.core2_ahb_pre);
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});
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while !RCC.extcfgr().read().shdhpref() {}
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#[cfg(any(stm32wl5x, stm32wb))]
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while !RCC.extcfgr().read().c2hpref() {}
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}
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set_freqs(Clocks {
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sys: sys_clk,
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hclk1,
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hclk2,
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hclk3,
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pclk1,
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pclk2,
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pclk1_tim,
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pclk2_tim,
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#[cfg(stm32wl)]
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pclk3: hclk3,
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#[cfg(rcc_l4)]
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hsi: None,
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#[cfg(rcc_l4)]
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lse: None,
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#[cfg(rcc_l4)]
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pllsai1_p: None,
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#[cfg(rcc_l4)]
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pllsai2_p: None,
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#[cfg(rcc_l4)]
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pll1_p: None,
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#[cfg(rcc_l4)]
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pll1_q: None,
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#[cfg(rcc_l4)]
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sai1_extclk: None,
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#[cfg(rcc_l4)]
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sai2_extclk: None,
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rtc,
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});
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}
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fn msirange_to_hertz(range: MSIRange) -> Hertz {
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match range {
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MSIRange::RANGE100K => Hertz(100_000),
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MSIRange::RANGE200K => Hertz(200_000),
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MSIRange::RANGE400K => Hertz(400_000),
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MSIRange::RANGE800K => Hertz(800_000),
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MSIRange::RANGE1M => Hertz(1_000_000),
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MSIRange::RANGE2M => Hertz(2_000_000),
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MSIRange::RANGE4M => Hertz(4_000_000),
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MSIRange::RANGE8M => Hertz(8_000_000),
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MSIRange::RANGE16M => Hertz(16_000_000),
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MSIRange::RANGE24M => Hertz(24_000_000),
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MSIRange::RANGE32M => Hertz(32_000_000),
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MSIRange::RANGE48M => Hertz(48_000_000),
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_ => unreachable!(),
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}
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}
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struct PllInput {
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hsi: Option<Hertz>,
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hse: Option<Hertz>,
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msi: Option<Hertz>,
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}
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#[allow(unused)]
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#[derive(Default)]
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struct PllOutput {
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p: Option<Hertz>,
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q: Option<Hertz>,
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r: Option<Hertz>,
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}
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#[derive(PartialEq, Eq, Clone, Copy)]
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enum PllInstance {
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Pll,
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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Pllsai1,
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#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
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Pllsai2,
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}
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fn pll_enable(instance: PllInstance, enabled: bool) {
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match instance {
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PllInstance::Pll => {
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RCC.cr().modify(|w| w.set_pllon(enabled));
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while RCC.cr().read().pllrdy() != enabled {}
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}
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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PllInstance::Pllsai1 => {
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RCC.cr().modify(|w| w.set_pllsai1on(enabled));
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while RCC.cr().read().pllsai1rdy() != enabled {}
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}
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#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
|
|
PllInstance::Pllsai2 => {
|
|
RCC.cr().modify(|w| w.set_pllsai2on(enabled));
|
|
while RCC.cr().read().pllsai2rdy() != enabled {}
|
|
}
|
|
}
|
|
}
|
|
|
|
fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
|
|
// Disable PLL
|
|
pll_enable(instance, false);
|
|
|
|
let Some(pll) = config else { return PllOutput::default() };
|
|
|
|
let pll_src = match pll.source {
|
|
PLLSource::DISABLE => panic!("must not select PLL source as DISABLE"),
|
|
PLLSource::HSE => input.hse,
|
|
PLLSource::HSI => input.hsi,
|
|
PLLSource::MSI => input.msi,
|
|
};
|
|
|
|
let pll_src = pll_src.unwrap();
|
|
|
|
let vco_freq = pll_src / pll.prediv * pll.mul;
|
|
|
|
let p = pll.divp.map(|div| vco_freq / div);
|
|
let q = pll.divq.map(|div| vco_freq / div);
|
|
let r = pll.divr.map(|div| vco_freq / div);
|
|
|
|
#[cfg(stm32l5)]
|
|
if instance == PllInstance::Pllsai2 {
|
|
assert!(q.is_none(), "PLLSAI2_Q is not available on L5");
|
|
assert!(r.is_none(), "PLLSAI2_R is not available on L5");
|
|
}
|
|
|
|
macro_rules! write_fields {
|
|
($w:ident) => {
|
|
$w.set_plln(pll.mul);
|
|
if let Some(divp) = pll.divp {
|
|
$w.set_pllp(divp);
|
|
$w.set_pllpen(true);
|
|
}
|
|
if let Some(divq) = pll.divq {
|
|
$w.set_pllq(divq);
|
|
$w.set_pllqen(true);
|
|
}
|
|
if let Some(divr) = pll.divr {
|
|
$w.set_pllr(divr);
|
|
$w.set_pllren(true);
|
|
}
|
|
};
|
|
}
|
|
|
|
match instance {
|
|
PllInstance::Pll => RCC.pllcfgr().write(|w| {
|
|
w.set_pllm(pll.prediv);
|
|
w.set_pllsrc(pll.source);
|
|
write_fields!(w);
|
|
}),
|
|
#[cfg(any(stm32l4, stm32l5, stm32wb))]
|
|
PllInstance::Pllsai1 => RCC.pllsai1cfgr().write(|w| {
|
|
#[cfg(any(rcc_l4plus, stm32l5))]
|
|
w.set_pllm(pll.prediv);
|
|
#[cfg(stm32l5)]
|
|
w.set_pllsrc(pll.source);
|
|
write_fields!(w);
|
|
}),
|
|
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
|
|
PllInstance::Pllsai2 => RCC.pllsai2cfgr().write(|w| {
|
|
#[cfg(any(rcc_l4plus, stm32l5))]
|
|
w.set_pllm(pll.prediv);
|
|
#[cfg(stm32l5)]
|
|
w.set_pllsrc(pll.source);
|
|
write_fields!(w);
|
|
}),
|
|
}
|
|
|
|
// Enable PLL
|
|
pll_enable(instance, true);
|
|
|
|
PllOutput { p, q, r }
|
|
}
|