bors[bot] 01e5376b25

Merge #456 ...

456: Fix L4 clock setup for MSI and PLL to allow RNG operation r=Dirbaio a=lulf

Example is tested on STM32L475VG.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>

2021-10-26 11:59:14 +00:00

..

.cargo

Support for STM32L1

2021-09-21 14:50:23 +02:00

src

Merge #456

2021-10-26 11:59:14 +00:00

build.rs

Add blinky example.

2021-06-08 10:37:11 -04:00

Cargo.toml

Update lots of deps

2021-09-11 01:35:23 +02:00

memory.x

Initial examples for STM32L4+

2021-06-08 10:37:11 -04:00