159 lines
4.2 KiB
Rust
159 lines
4.2 KiB
Rust
use core::convert::TryInto;
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use core::ptr::write_volatile;
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use core::sync::atomic::{fence, Ordering};
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use super::{FlashRegion, FlashSector, BANK1_REGION, FLASH_REGIONS, WRITE_SIZE};
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use crate::flash::Error;
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use crate::pac;
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pub const fn is_default_layout() -> bool {
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true
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}
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const fn is_dual_bank() -> bool {
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FLASH_REGIONS.len() >= 2
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}
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pub fn get_flash_regions() -> &'static [&'static FlashRegion] {
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&FLASH_REGIONS
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}
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pub(crate) unsafe fn lock() {
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pac::FLASH.bank(0).cr().modify(|w| w.set_lock(true));
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if is_dual_bank() {
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pac::FLASH.bank(1).cr().modify(|w| w.set_lock(true));
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}
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}
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pub(crate) unsafe fn unlock() {
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pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0x4567_0123));
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pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
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if is_dual_bank() {
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pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0x4567_0123));
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pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
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}
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}
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pub(crate) unsafe fn enable_blocking_write() {
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assert_eq!(0, WRITE_SIZE % 4);
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}
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pub(crate) unsafe fn disable_blocking_write() {}
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pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
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// We cannot have the write setup sequence in begin_write as it depends on the address
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let bank = if start_address < BANK1_REGION.end() {
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pac::FLASH.bank(0)
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} else {
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pac::FLASH.bank(1)
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};
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bank.cr().write(|w| {
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w.set_pg(true);
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#[cfg(flash_h7)]
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w.set_psize(2); // 32 bits at once
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});
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cortex_m::asm::isb();
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cortex_m::asm::dsb();
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fence(Ordering::SeqCst);
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let mut res = None;
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let mut address = start_address;
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for val in buf.chunks(4) {
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write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
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address += val.len() as u32;
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res = Some(blocking_wait_ready(bank));
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bank.sr().modify(|w| {
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if w.eop() {
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w.set_eop(true);
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}
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});
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if res.unwrap().is_err() {
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break;
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}
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}
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bank.cr().write(|w| w.set_pg(false));
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cortex_m::asm::isb();
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cortex_m::asm::dsb();
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fence(Ordering::SeqCst);
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res.unwrap()
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}
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pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
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let bank = pac::FLASH.bank(sector.bank as usize);
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bank.cr().modify(|w| {
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w.set_ser(true);
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#[cfg(flash_h7)]
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w.set_snb(sector.index_in_bank);
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#[cfg(flash_h7ab)]
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w.set_ssn(sector.index_in_bank);
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});
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bank.cr().modify(|w| {
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w.set_start(true);
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});
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let ret: Result<(), Error> = blocking_wait_ready(bank);
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bank.cr().modify(|w| w.set_ser(false));
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bank_clear_all_err(bank);
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ret
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}
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pub(crate) unsafe fn clear_all_err() {
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bank_clear_all_err(pac::FLASH.bank(0));
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bank_clear_all_err(pac::FLASH.bank(1));
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}
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unsafe fn bank_clear_all_err(bank: pac::flash::Bank) {
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// read and write back the same value.
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// This clears all "write 0 to clear" bits.
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bank.sr().modify(|_| {});
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}
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unsafe fn blocking_wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
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loop {
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let sr = bank.sr().read();
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if !sr.bsy() && !sr.qw() {
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if sr.wrperr() {
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return Err(Error::Protected);
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}
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if sr.pgserr() {
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error!("pgserr");
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return Err(Error::Seq);
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}
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if sr.incerr() {
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// writing to a different address when programming 256 bit word was not finished
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error!("incerr");
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return Err(Error::Seq);
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}
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if sr.crcrderr() {
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error!("crcrderr");
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return Err(Error::Seq);
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}
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if sr.operr() {
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return Err(Error::Prog);
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}
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if sr.sneccerr1() {
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// single ECC error
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return Err(Error::Prog);
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}
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if sr.dbeccerr() {
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// double ECC error
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return Err(Error::Prog);
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}
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if sr.rdperr() {
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return Err(Error::Protected);
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}
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if sr.rdserr() {
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return Err(Error::Protected);
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}
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return Ok(());
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}
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}
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}
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