2021-05-13 20:28:53 +02:00
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#![macro_use]
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2022-01-19 17:29:47 +01:00
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use core::marker::PhantomData;
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use core::ptr;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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use self::sealed::WordSize;
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2021-12-07 05:45:40 +01:00
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use crate::dma::NoDma;
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2022-02-10 02:34:59 +01:00
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use crate::gpio::sealed::{AFType, Pin as _};
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2022-02-10 21:38:03 +01:00
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use crate::gpio::AnyPin;
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2021-12-07 02:12:34 +01:00
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use crate::pac::spi::{regs, vals};
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2021-12-06 21:47:50 +01:00
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use crate::peripherals;
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use crate::rcc::RccPeripheral;
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2021-12-06 22:19:24 +01:00
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use crate::time::Hertz;
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2022-01-19 17:29:47 +01:00
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2022-01-26 22:39:06 +01:00
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pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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2021-12-06 21:47:50 +01:00
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2021-07-21 20:12:50 +02:00
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#[cfg_attr(spi_v1, path = "v1.rs")]
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2021-10-06 21:02:15 +02:00
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#[cfg_attr(spi_f1, path = "v1.rs")]
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2021-07-21 22:50:38 +02:00
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#[cfg_attr(spi_v2, path = "v2.rs")]
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#[cfg_attr(spi_v3, path = "v3.rs")]
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2021-05-17 02:04:51 +02:00
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mod _version;
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2021-05-13 20:28:53 +02:00
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2021-12-07 07:48:44 +01:00
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type Regs = &'static crate::pac::spi::Spi;
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2021-08-31 14:32:48 +02:00
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#[derive(Debug)]
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2021-05-20 10:54:10 +02:00
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2021-05-14 16:11:43 +02:00
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pub enum Error {
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Framing,
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Crc,
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2021-05-27 23:05:42 +02:00
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ModeFault,
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2021-05-14 16:11:43 +02:00
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Overrun,
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}
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2021-05-13 20:28:53 +02:00
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// TODO move upwards in the tree
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2022-01-10 19:37:15 +01:00
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#[derive(Copy, Clone)]
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pub enum BitOrder {
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2021-05-13 20:28:53 +02:00
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LsbFirst,
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MsbFirst,
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}
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#[non_exhaustive]
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2022-01-10 19:37:15 +01:00
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#[derive(Copy, Clone)]
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2021-05-13 20:28:53 +02:00
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pub struct Config {
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pub mode: Mode,
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2022-01-10 19:37:15 +01:00
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pub bit_order: BitOrder,
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2021-05-13 20:28:53 +02:00
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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mode: MODE_0,
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2022-01-10 19:37:15 +01:00
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bit_order: BitOrder::MsbFirst,
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}
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}
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}
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impl Config {
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fn raw_phase(&self) -> vals::Cpha {
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match self.mode.phase {
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Phase::CaptureOnSecondTransition => vals::Cpha::SECONDEDGE,
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Phase::CaptureOnFirstTransition => vals::Cpha::FIRSTEDGE,
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}
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}
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fn raw_polarity(&self) -> vals::Cpol {
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match self.mode.polarity {
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Polarity::IdleHigh => vals::Cpol::IDLEHIGH,
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Polarity::IdleLow => vals::Cpol::IDLELOW,
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}
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}
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fn raw_byte_order(&self) -> vals::Lsbfirst {
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match self.bit_order {
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BitOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
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BitOrder::MsbFirst => vals::Lsbfirst::MSBFIRST,
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2021-05-13 20:28:53 +02:00
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}
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}
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}
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2021-05-14 16:11:43 +02:00
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2021-12-06 21:47:50 +01:00
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pub struct Spi<'d, T: Instance, Tx, Rx> {
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sck: Option<AnyPin>,
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mosi: Option<AnyPin>,
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miso: Option<AnyPin>,
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txdma: Tx,
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rxdma: Rx,
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current_word_size: WordSize,
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phantom: PhantomData<&'d mut T>,
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}
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2021-12-06 22:19:24 +01:00
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impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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pub fn new<F>(
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2022-02-10 02:34:59 +01:00
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peri: impl Unborrow<Target = T> + 'd,
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sck: impl Unborrow<Target = impl SckPin<T>> + 'd,
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mosi: impl Unborrow<Target = impl MosiPin<T>> + 'd,
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miso: impl Unborrow<Target = impl MisoPin<T>> + 'd,
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txdma: impl Unborrow<Target = Tx> + 'd,
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rxdma: impl Unborrow<Target = Rx> + 'd,
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2021-12-06 22:19:24 +01:00
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freq: F,
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config: Config,
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) -> Self
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where
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F: Into<Hertz>,
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{
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2022-02-10 02:34:59 +01:00
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unborrow!(sck, mosi, miso);
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unsafe {
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sck.set_as_af(sck.af_num(), AFType::OutputPushPull);
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#[cfg(any(spi_v2, spi_v3))]
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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mosi.set_as_af(mosi.af_num(), AFType::OutputPushPull);
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#[cfg(any(spi_v2, spi_v3))]
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mosi.set_speed(crate::gpio::Speed::VeryHigh);
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miso.set_as_af(miso.af_num(), AFType::Input);
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#[cfg(any(spi_v2, spi_v3))]
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miso.set_speed(crate::gpio::Speed::VeryHigh);
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}
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Self::new_inner(
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peri,
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Some(sck.degrade()),
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Some(mosi.degrade()),
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Some(miso.degrade()),
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txdma,
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rxdma,
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freq,
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config,
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)
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}
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2021-12-06 22:19:24 +01:00
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2022-02-10 02:34:59 +01:00
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pub fn new_rxonly<F>(
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peri: impl Unborrow<Target = T> + 'd,
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sck: impl Unborrow<Target = impl SckPin<T>> + 'd,
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miso: impl Unborrow<Target = impl MisoPin<T>> + 'd,
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txdma: impl Unborrow<Target = Tx> + 'd, // TODO remove
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rxdma: impl Unborrow<Target = Rx> + 'd,
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freq: F,
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config: Config,
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) -> Self
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where
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F: Into<Hertz>,
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{
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unborrow!(sck, miso);
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unsafe {
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sck.set_as_af(sck.af_num(), AFType::OutputPushPull);
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#[cfg(any(spi_v2, spi_v3))]
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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miso.set_as_af(miso.af_num(), AFType::Input);
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#[cfg(any(spi_v2, spi_v3))]
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miso.set_speed(crate::gpio::Speed::VeryHigh);
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}
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Self::new_inner(
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peri,
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Some(sck.degrade()),
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None,
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Some(miso.degrade()),
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txdma,
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rxdma,
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freq,
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config,
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)
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}
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2021-12-06 22:19:24 +01:00
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2022-02-10 02:34:59 +01:00
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pub fn new_txonly<F>(
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peri: impl Unborrow<Target = T> + 'd,
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sck: impl Unborrow<Target = impl SckPin<T>> + 'd,
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mosi: impl Unborrow<Target = impl MosiPin<T>> + 'd,
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txdma: impl Unborrow<Target = Tx> + 'd,
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rxdma: impl Unborrow<Target = Rx> + 'd, // TODO remove
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freq: F,
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config: Config,
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) -> Self
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where
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F: Into<Hertz>,
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{
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unborrow!(sck, mosi);
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2021-12-06 22:19:24 +01:00
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unsafe {
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2022-02-10 02:34:59 +01:00
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sck.set_as_af(sck.af_num(), AFType::OutputPushPull);
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#[cfg(any(spi_v2, spi_v3))]
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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mosi.set_as_af(mosi.af_num(), AFType::OutputPushPull);
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#[cfg(any(spi_v2, spi_v3))]
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mosi.set_speed(crate::gpio::Speed::VeryHigh);
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}
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Self::new_inner(
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peri,
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Some(sck.degrade()),
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Some(mosi.degrade()),
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None,
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txdma,
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rxdma,
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freq,
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config,
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)
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}
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fn new_inner<F>(
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_peri: impl Unborrow<Target = T> + 'd,
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sck: Option<AnyPin>,
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mosi: Option<AnyPin>,
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miso: Option<AnyPin>,
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2022-02-10 16:06:42 +01:00
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txdma: impl Unborrow<Target = Tx> + 'd,
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rxdma: impl Unborrow<Target = Rx> + 'd,
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2022-02-10 02:34:59 +01:00
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freq: F,
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config: Config,
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) -> Self
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where
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F: Into<Hertz>,
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{
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unborrow!(txdma, rxdma);
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2021-12-06 22:19:24 +01:00
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let pclk = T::frequency();
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2021-12-07 20:22:59 +01:00
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let br = compute_baud_rate(pclk, freq.into());
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2022-01-10 19:37:15 +01:00
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let cpha = config.raw_phase();
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let cpol = config.raw_polarity();
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2021-12-07 20:22:59 +01:00
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2022-01-10 19:37:15 +01:00
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let lsbfirst = config.raw_byte_order();
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2021-12-07 20:22:59 +01:00
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T::enable();
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T::reset();
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2021-12-06 22:19:24 +01:00
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#[cfg(any(spi_v1, spi_f1))]
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unsafe {
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T::regs().cr2().modify(|w| {
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w.set_ssoe(false);
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});
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T::regs().cr1().modify(|w| {
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2021-12-07 20:22:59 +01:00
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w.set_cpha(cpha);
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w.set_cpol(cpol);
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2021-12-06 22:19:24 +01:00
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w.set_mstr(vals::Mstr::MASTER);
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2021-12-07 20:22:59 +01:00
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w.set_br(br);
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2021-12-06 22:19:24 +01:00
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w.set_spe(true);
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2021-12-07 20:22:59 +01:00
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w.set_lsbfirst(lsbfirst);
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2021-12-06 22:19:24 +01:00
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w.set_ssi(true);
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w.set_ssm(true);
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w.set_crcen(false);
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w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
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if mosi.is_none() {
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w.set_rxonly(vals::Rxonly::OUTPUTDISABLED);
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}
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w.set_dff(WordSize::EightBit.dff())
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});
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}
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#[cfg(spi_v2)]
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unsafe {
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T::regs().cr2().modify(|w| {
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2021-12-07 05:36:53 +01:00
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w.set_frxth(WordSize::EightBit.frxth());
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w.set_ds(WordSize::EightBit.ds());
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2021-12-06 22:19:24 +01:00
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w.set_ssoe(false);
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});
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T::regs().cr1().modify(|w| {
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2021-12-07 20:22:59 +01:00
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w.set_cpha(cpha);
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w.set_cpol(cpol);
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2021-12-06 22:19:24 +01:00
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w.set_mstr(vals::Mstr::MASTER);
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2021-12-07 20:22:59 +01:00
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w.set_br(br);
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w.set_lsbfirst(lsbfirst);
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2021-12-06 22:19:24 +01:00
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w.set_ssi(true);
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w.set_ssm(true);
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w.set_crcen(false);
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w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
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w.set_spe(true);
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});
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}
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#[cfg(spi_v3)]
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unsafe {
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T::regs().ifcr().write(|w| w.0 = 0xffff_ffff);
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T::regs().cfg2().modify(|w| {
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//w.set_ssoe(true);
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w.set_ssoe(false);
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2021-12-07 20:22:59 +01:00
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w.set_cpha(cpha);
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w.set_cpol(cpol);
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2022-01-10 19:37:15 +01:00
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w.set_lsbfirst(lsbfirst);
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2021-12-06 22:19:24 +01:00
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w.set_ssm(true);
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w.set_master(vals::Master::MASTER);
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w.set_comm(vals::Comm::FULLDUPLEX);
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w.set_ssom(vals::Ssom::ASSERTED);
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w.set_midi(0);
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w.set_mssi(0);
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w.set_afcntr(vals::Afcntr::CONTROLLED);
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w.set_ssiop(vals::Ssiop::ACTIVEHIGH);
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});
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T::regs().cfg1().modify(|w| {
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w.set_crcen(false);
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2021-12-07 20:22:59 +01:00
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w.set_mbr(br);
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2021-12-06 22:19:24 +01:00
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w.set_dsize(WordSize::EightBit.dsize());
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});
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T::regs().cr2().modify(|w| {
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w.set_tsize(0);
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w.set_tser(0);
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});
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T::regs().cr1().modify(|w| {
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w.set_ssi(false);
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w.set_spe(true);
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});
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}
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Self {
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sck,
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mosi,
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miso,
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txdma,
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rxdma,
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current_word_size: WordSize::EightBit,
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phantom: PhantomData,
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}
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}
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2022-01-10 19:37:15 +01:00
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/// Reconfigures it with the supplied config.
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pub fn reconfigure(&mut self, config: Config) {
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let cpha = config.raw_phase();
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|
|
|
let cpol = config.raw_polarity();
|
|
|
|
|
|
|
|
let lsbfirst = config.raw_byte_order();
|
|
|
|
|
|
|
|
#[cfg(any(spi_v1, spi_f1, spi_v2))]
|
|
|
|
unsafe {
|
|
|
|
T::regs().cr1().modify(|w| {
|
|
|
|
w.set_cpha(cpha);
|
|
|
|
w.set_cpol(cpol);
|
|
|
|
w.set_lsbfirst(lsbfirst);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
unsafe {
|
|
|
|
T::regs().cfg2().modify(|w| {
|
|
|
|
w.set_cpha(cpha);
|
|
|
|
w.set_cpol(cpol);
|
|
|
|
w.set_lsbfirst(lsbfirst);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pub fn get_current_config(&self) -> Config {
|
|
|
|
#[cfg(any(spi_v1, spi_f1, spi_v2))]
|
|
|
|
let cfg = unsafe { T::regs().cr1().read() };
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
let cfg = unsafe { T::regs().cfg2().read() };
|
|
|
|
let polarity = if cfg.cpol() == vals::Cpol::IDLELOW {
|
|
|
|
Polarity::IdleLow
|
|
|
|
} else {
|
|
|
|
Polarity::IdleHigh
|
|
|
|
};
|
|
|
|
let phase = if cfg.cpha() == vals::Cpha::FIRSTEDGE {
|
|
|
|
Phase::CaptureOnFirstTransition
|
|
|
|
} else {
|
|
|
|
Phase::CaptureOnSecondTransition
|
|
|
|
};
|
|
|
|
|
|
|
|
let bit_order = if cfg.lsbfirst() == vals::Lsbfirst::LSBFIRST {
|
|
|
|
BitOrder::LsbFirst
|
|
|
|
} else {
|
|
|
|
BitOrder::MsbFirst
|
|
|
|
};
|
|
|
|
|
|
|
|
Config {
|
|
|
|
mode: Mode { polarity, phase },
|
|
|
|
bit_order,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-06 23:47:08 +01:00
|
|
|
fn set_word_size(&mut self, word_size: WordSize) {
|
|
|
|
if self.current_word_size == word_size {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(any(spi_v1, spi_f1))]
|
|
|
|
unsafe {
|
|
|
|
T::regs().cr1().modify(|reg| {
|
|
|
|
reg.set_spe(false);
|
|
|
|
reg.set_dff(word_size.dff())
|
|
|
|
});
|
|
|
|
T::regs().cr1().modify(|reg| {
|
|
|
|
reg.set_spe(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
#[cfg(spi_v2)]
|
|
|
|
unsafe {
|
|
|
|
T::regs().cr1().modify(|w| {
|
|
|
|
w.set_spe(false);
|
|
|
|
});
|
|
|
|
T::regs().cr2().modify(|w| {
|
|
|
|
w.set_frxth(word_size.frxth());
|
|
|
|
w.set_ds(word_size.ds());
|
|
|
|
});
|
|
|
|
T::regs().cr1().modify(|w| {
|
|
|
|
w.set_spe(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
unsafe {
|
|
|
|
T::regs().cr1().modify(|w| {
|
|
|
|
w.set_csusp(true);
|
|
|
|
});
|
|
|
|
while T::regs().sr().read().eot() {}
|
|
|
|
T::regs().cr1().modify(|w| {
|
|
|
|
w.set_spe(false);
|
|
|
|
});
|
|
|
|
T::regs().cfg1().modify(|w| {
|
|
|
|
w.set_dsize(word_size.dsize());
|
|
|
|
});
|
|
|
|
T::regs().cr1().modify(|w| {
|
|
|
|
w.set_csusp(false);
|
|
|
|
w.set_spe(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
self.current_word_size = word_size;
|
|
|
|
}
|
2022-01-19 17:29:47 +01:00
|
|
|
|
|
|
|
pub async fn write(&mut self, data: &[u8]) -> Result<(), Error>
|
|
|
|
where
|
2022-02-10 21:38:03 +01:00
|
|
|
Tx: TxDma<T>,
|
2022-01-19 17:29:47 +01:00
|
|
|
{
|
|
|
|
self.write_dma_u8(data).await
|
|
|
|
}
|
|
|
|
|
|
|
|
pub async fn read(&mut self, data: &mut [u8]) -> Result<(), Error>
|
|
|
|
where
|
2022-02-10 21:38:03 +01:00
|
|
|
Tx: TxDma<T>,
|
|
|
|
Rx: RxDma<T>,
|
2022-01-19 17:29:47 +01:00
|
|
|
{
|
|
|
|
self.read_dma_u8(data).await
|
|
|
|
}
|
|
|
|
|
|
|
|
pub async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error>
|
|
|
|
where
|
2022-02-10 21:38:03 +01:00
|
|
|
Tx: TxDma<T>,
|
|
|
|
Rx: RxDma<T>,
|
2022-01-19 17:29:47 +01:00
|
|
|
{
|
|
|
|
self.transfer_dma_u8(read, write).await
|
|
|
|
}
|
|
|
|
|
|
|
|
pub fn blocking_write<W: Word>(&mut self, words: &[W]) -> Result<(), Error> {
|
|
|
|
self.set_word_size(W::WORDSIZE);
|
|
|
|
let regs = T::regs();
|
|
|
|
for word in words.iter() {
|
|
|
|
let _ = transfer_word(regs, *word)?;
|
|
|
|
}
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
|
2022-02-16 03:54:39 +01:00
|
|
|
pub fn blocking_read<W: Word>(&mut self, words: &mut [W]) -> Result<(), Error> {
|
|
|
|
self.set_word_size(W::WORDSIZE);
|
|
|
|
let regs = T::regs();
|
|
|
|
for word in words.iter_mut() {
|
|
|
|
*word = transfer_word(regs, W::default())?;
|
|
|
|
}
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
|
2022-01-19 17:29:47 +01:00
|
|
|
pub fn blocking_transfer_in_place<W: Word>(&mut self, words: &mut [W]) -> Result<(), Error> {
|
|
|
|
self.set_word_size(W::WORDSIZE);
|
|
|
|
let regs = T::regs();
|
|
|
|
for word in words.iter_mut() {
|
|
|
|
*word = transfer_word(regs, *word)?;
|
|
|
|
}
|
|
|
|
Ok(())
|
|
|
|
}
|
2022-02-16 03:54:39 +01:00
|
|
|
|
|
|
|
pub fn blocking_transfer<W: Word>(&mut self, read: &mut [W], write: &[W]) -> Result<(), Error> {
|
|
|
|
self.set_word_size(W::WORDSIZE);
|
|
|
|
let regs = T::regs();
|
|
|
|
|
|
|
|
let len = read.len().max(write.len());
|
|
|
|
for i in 0..len {
|
|
|
|
let wb = write.get(i).copied().unwrap_or_default();
|
|
|
|
let rb = transfer_word(regs, wb)?;
|
|
|
|
if let Some(r) = read.get_mut(i) {
|
|
|
|
*r = rb;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
Ok(())
|
|
|
|
}
|
2021-12-06 22:19:24 +01:00
|
|
|
}
|
|
|
|
|
2021-12-06 23:51:10 +01:00
|
|
|
impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
|
|
|
|
fn drop(&mut self) {
|
|
|
|
unsafe {
|
2022-02-24 02:36:30 +01:00
|
|
|
self.sck.as_ref().map(|x| x.set_as_disconnected());
|
|
|
|
self.mosi.as_ref().map(|x| x.set_as_disconnected());
|
|
|
|
self.miso.as_ref().map(|x| x.set_as_disconnected());
|
2021-12-06 23:51:10 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-07 20:22:59 +01:00
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
use vals::Br;
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
use vals::Mbr as Br;
|
|
|
|
|
|
|
|
fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> Br {
|
|
|
|
let val = match clocks.0 / freq.0 {
|
|
|
|
0 => unreachable!(),
|
|
|
|
1..=2 => 0b000,
|
|
|
|
3..=5 => 0b001,
|
|
|
|
6..=11 => 0b010,
|
|
|
|
12..=23 => 0b011,
|
|
|
|
24..=39 => 0b100,
|
|
|
|
40..=95 => 0b101,
|
|
|
|
96..=191 => 0b110,
|
|
|
|
_ => 0b111,
|
|
|
|
};
|
|
|
|
|
|
|
|
Br(val)
|
|
|
|
}
|
|
|
|
|
2021-12-06 23:33:06 +01:00
|
|
|
trait RegsExt {
|
|
|
|
fn tx_ptr<W>(&self) -> *mut W;
|
|
|
|
fn rx_ptr<W>(&self) -> *mut W;
|
|
|
|
}
|
|
|
|
|
|
|
|
impl RegsExt for crate::pac::spi::Spi {
|
|
|
|
fn tx_ptr<W>(&self) -> *mut W {
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
let dr = self.dr();
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
let dr = self.txdr();
|
|
|
|
dr.ptr() as *mut W
|
|
|
|
}
|
|
|
|
|
|
|
|
fn rx_ptr<W>(&self) -> *mut W {
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
let dr = self.dr();
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
let dr = self.rxdr();
|
|
|
|
dr.ptr() as *mut W
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-07 02:12:34 +01:00
|
|
|
fn check_error_flags(sr: regs::Sr) -> Result<(), Error> {
|
|
|
|
if sr.ovr() {
|
|
|
|
return Err(Error::Overrun);
|
|
|
|
}
|
|
|
|
#[cfg(not(any(spi_f1, spi_v3)))]
|
|
|
|
if sr.fre() {
|
|
|
|
return Err(Error::Framing);
|
|
|
|
}
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
if sr.tifre() {
|
|
|
|
return Err(Error::Framing);
|
|
|
|
}
|
|
|
|
if sr.modf() {
|
|
|
|
return Err(Error::ModeFault);
|
|
|
|
}
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
if sr.crcerr() {
|
|
|
|
return Err(Error::Crc);
|
|
|
|
}
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
if sr.crce() {
|
|
|
|
return Err(Error::Crc);
|
|
|
|
}
|
|
|
|
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
|
2021-12-07 07:48:44 +01:00
|
|
|
fn spin_until_tx_ready(regs: Regs) -> Result<(), Error> {
|
2021-12-07 05:45:40 +01:00
|
|
|
loop {
|
|
|
|
let sr = unsafe { regs.sr().read() };
|
|
|
|
|
|
|
|
check_error_flags(sr)?;
|
|
|
|
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
if sr.txe() {
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
if sr.txp() {
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-07 07:48:44 +01:00
|
|
|
fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
|
2021-12-07 05:45:40 +01:00
|
|
|
loop {
|
|
|
|
let sr = unsafe { regs.sr().read() };
|
|
|
|
|
|
|
|
check_error_flags(sr)?;
|
|
|
|
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
if sr.rxne() {
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
if sr.rxp() {
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-14 23:05:39 +01:00
|
|
|
fn spin_until_idle(regs: Regs) {
|
|
|
|
#[cfg(any(spi_v1, spi_f1))]
|
|
|
|
unsafe {
|
|
|
|
while regs.sr().read().bsy() {}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(spi_v2)]
|
|
|
|
unsafe {
|
|
|
|
while regs.sr().read().ftlvl() > 0 {}
|
|
|
|
while regs.sr().read().frlvl() > 0 {}
|
|
|
|
while regs.sr().read().bsy() {}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
unsafe {
|
|
|
|
while !regs.sr().read().txc() {}
|
|
|
|
while regs.sr().read().rxplvl().0 > 0 {}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-03-14 21:10:56 +01:00
|
|
|
fn flush_rx_fifo(regs: Regs) {
|
|
|
|
unsafe {
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
while regs.sr().read().rxne() {
|
|
|
|
let _ = regs.dr().read();
|
|
|
|
}
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
while regs.sr().read().rxp() {
|
|
|
|
let _ = regs.rxdr().read();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-14 23:59:31 +01:00
|
|
|
fn finish_dma(regs: Regs) {
|
|
|
|
spin_until_idle(regs);
|
|
|
|
|
|
|
|
unsafe {
|
|
|
|
regs.cr1().modify(|w| {
|
|
|
|
w.set_spe(false);
|
|
|
|
});
|
|
|
|
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
regs.cr2().modify(|reg| {
|
|
|
|
reg.set_txdmaen(false);
|
|
|
|
reg.set_rxdmaen(false);
|
|
|
|
});
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
regs.cfg1().modify(|reg| {
|
|
|
|
reg.set_txdmaen(false);
|
|
|
|
reg.set_rxdmaen(false);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-07 07:48:44 +01:00
|
|
|
fn transfer_word<W: Word>(regs: Regs, tx_word: W) -> Result<W, Error> {
|
2021-12-07 05:45:40 +01:00
|
|
|
spin_until_tx_ready(regs)?;
|
|
|
|
|
|
|
|
unsafe {
|
|
|
|
ptr::write_volatile(regs.tx_ptr(), tx_word);
|
|
|
|
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
regs.cr1().modify(|reg| reg.set_cstart(true));
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_until_rx_ready(regs)?;
|
|
|
|
|
|
|
|
let rx_word = unsafe { ptr::read_volatile(regs.rx_ptr()) };
|
|
|
|
return Ok(rx_word);
|
|
|
|
}
|
|
|
|
|
2022-01-26 22:39:06 +01:00
|
|
|
mod eh02 {
|
|
|
|
use super::*;
|
2021-12-07 05:45:40 +01:00
|
|
|
|
2022-01-26 22:39:06 +01:00
|
|
|
// Note: It is not possible to impl these traits generically in embedded-hal 0.2 due to a conflict with
|
|
|
|
// some marker traits. For details, see https://github.com/rust-embedded/embedded-hal/pull/289
|
|
|
|
macro_rules! impl_blocking {
|
|
|
|
($w:ident) => {
|
|
|
|
impl<'d, T: Instance> embedded_hal_02::blocking::spi::Write<$w>
|
|
|
|
for Spi<'d, T, NoDma, NoDma>
|
|
|
|
{
|
|
|
|
type Error = Error;
|
|
|
|
|
|
|
|
fn write(&mut self, words: &[$w]) -> Result<(), Self::Error> {
|
|
|
|
self.blocking_write(words)
|
|
|
|
}
|
2021-12-07 06:29:16 +01:00
|
|
|
}
|
2021-12-07 05:45:40 +01:00
|
|
|
|
2022-01-26 22:39:06 +01:00
|
|
|
impl<'d, T: Instance> embedded_hal_02::blocking::spi::Transfer<$w>
|
|
|
|
for Spi<'d, T, NoDma, NoDma>
|
|
|
|
{
|
|
|
|
type Error = Error;
|
2021-12-07 05:45:40 +01:00
|
|
|
|
2022-01-26 22:39:06 +01:00
|
|
|
fn transfer<'w>(&mut self, words: &'w mut [$w]) -> Result<&'w [$w], Self::Error> {
|
|
|
|
self.blocking_transfer_in_place(words)?;
|
|
|
|
Ok(words)
|
|
|
|
}
|
2021-12-07 06:29:16 +01:00
|
|
|
}
|
2022-01-26 22:39:06 +01:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
impl_blocking!(u8);
|
|
|
|
impl_blocking!(u16);
|
2021-12-07 05:45:40 +01:00
|
|
|
}
|
|
|
|
|
2022-01-26 22:39:06 +01:00
|
|
|
#[cfg(feature = "unstable-traits")]
|
|
|
|
mod eh1 {
|
|
|
|
use super::*;
|
2021-12-07 05:45:40 +01:00
|
|
|
|
2022-01-26 22:39:06 +01:00
|
|
|
impl<'d, T: Instance, Tx, Rx> embedded_hal_1::spi::ErrorType for Spi<'d, T, Tx, Rx> {
|
|
|
|
type Error = Error;
|
|
|
|
}
|
2021-12-07 05:06:58 +01:00
|
|
|
|
2022-02-16 03:54:39 +01:00
|
|
|
impl<'d, T: Instance, Tx, Rx> embedded_hal_1::spi::blocking::SpiBusFlush for Spi<'d, T, Tx, Rx> {
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embedded_hal_1::spi::blocking::SpiBusRead<u8> for Spi<'d, T, NoDma, NoDma> {
|
|
|
|
fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
|
|
|
|
self.blocking_read(words)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embedded_hal_1::spi::blocking::SpiBusWrite<u8> for Spi<'d, T, NoDma, NoDma> {
|
|
|
|
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
|
|
|
|
self.blocking_write(words)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embedded_hal_1::spi::blocking::SpiBus<u8> for Spi<'d, T, NoDma, NoDma> {
|
|
|
|
fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
|
|
|
|
self.blocking_transfer(read, write)
|
|
|
|
}
|
|
|
|
|
|
|
|
fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
|
|
|
|
self.blocking_transfer_in_place(words)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-01-26 22:39:06 +01:00
|
|
|
impl embedded_hal_1::spi::Error for Error {
|
|
|
|
fn kind(&self) -> embedded_hal_1::spi::ErrorKind {
|
|
|
|
match *self {
|
|
|
|
Self::Framing => embedded_hal_1::spi::ErrorKind::FrameFormat,
|
|
|
|
Self::Crc => embedded_hal_1::spi::ErrorKind::Other,
|
|
|
|
Self::ModeFault => embedded_hal_1::spi::ErrorKind::ModeFault,
|
|
|
|
Self::Overrun => embedded_hal_1::spi::ErrorKind::Overrun,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2022-02-12 02:26:15 +01:00
|
|
|
}
|
|
|
|
|
2022-02-16 03:54:39 +01:00
|
|
|
cfg_if::cfg_if! {
|
|
|
|
if #[cfg(all(feature = "unstable-traits", feature = "nightly"))] {
|
|
|
|
use core::future::Future;
|
|
|
|
impl<'d, T: Instance, Tx, Rx> embedded_hal_async::spi::SpiBusFlush for Spi<'d, T, Tx, Rx> {
|
|
|
|
type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
|
|
|
|
fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
|
|
|
|
async { Ok(()) }
|
2022-01-26 22:39:06 +01:00
|
|
|
}
|
|
|
|
}
|
2021-12-07 05:06:58 +01:00
|
|
|
|
2022-02-16 03:54:39 +01:00
|
|
|
impl<'d, T: Instance, Tx: TxDma<T>, Rx> embedded_hal_async::spi::SpiBusWrite<u8>
|
|
|
|
for Spi<'d, T, Tx, Rx>
|
|
|
|
{
|
|
|
|
type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
|
|
|
|
fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
|
|
self.write(data)
|
2022-01-26 22:39:06 +01:00
|
|
|
}
|
|
|
|
}
|
2021-12-07 05:06:58 +01:00
|
|
|
|
2022-02-16 03:54:39 +01:00
|
|
|
impl<'d, T: Instance, Tx: TxDma<T>, Rx: RxDma<T>> embedded_hal_async::spi::SpiBusRead<u8>
|
|
|
|
for Spi<'d, T, Tx, Rx>
|
|
|
|
{
|
|
|
|
type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
|
|
|
|
fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
|
|
self.read(data)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance, Tx: TxDma<T>, Rx: RxDma<T>> embedded_hal_async::spi::SpiBus<u8>
|
|
|
|
for Spi<'d, T, Tx, Rx>
|
|
|
|
{
|
|
|
|
type TransferFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
|
|
|
|
fn transfer<'a>(&'a mut self, rx: &'a mut [u8], tx: &'a [u8]) -> Self::TransferFuture<'a> {
|
|
|
|
self.transfer(rx, tx)
|
|
|
|
}
|
|
|
|
|
|
|
|
type TransferInPlaceFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
|
|
|
|
fn transfer_in_place<'a>(
|
|
|
|
&'a mut self,
|
|
|
|
words: &'a mut [u8],
|
|
|
|
) -> Self::TransferInPlaceFuture<'a> {
|
|
|
|
// TODO: Implement async version
|
|
|
|
let result = self.blocking_transfer_in_place(words);
|
|
|
|
async move { result }
|
2022-01-26 22:39:06 +01:00
|
|
|
}
|
|
|
|
}
|
2021-12-07 05:06:58 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-14 16:11:43 +02:00
|
|
|
pub(crate) mod sealed {
|
|
|
|
use super::*;
|
|
|
|
|
|
|
|
pub trait Instance {
|
|
|
|
fn regs() -> &'static crate::pac::spi::Spi;
|
|
|
|
}
|
|
|
|
|
2022-01-19 17:29:47 +01:00
|
|
|
pub trait Word: Copy + 'static {
|
|
|
|
const WORDSIZE: WordSize;
|
|
|
|
}
|
|
|
|
|
|
|
|
impl Word for u8 {
|
|
|
|
const WORDSIZE: WordSize = WordSize::EightBit;
|
|
|
|
}
|
|
|
|
impl Word for u16 {
|
|
|
|
const WORDSIZE: WordSize = WordSize::SixteenBit;
|
|
|
|
}
|
|
|
|
|
|
|
|
#[derive(Copy, Clone, PartialOrd, PartialEq)]
|
|
|
|
pub enum WordSize {
|
|
|
|
EightBit,
|
|
|
|
SixteenBit,
|
|
|
|
}
|
|
|
|
|
|
|
|
impl WordSize {
|
|
|
|
#[cfg(any(spi_v1, spi_f1))]
|
|
|
|
pub fn dff(&self) -> vals::Dff {
|
|
|
|
match self {
|
|
|
|
WordSize::EightBit => vals::Dff::EIGHTBIT,
|
|
|
|
WordSize::SixteenBit => vals::Dff::SIXTEENBIT,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(spi_v2)]
|
|
|
|
pub fn ds(&self) -> vals::Ds {
|
|
|
|
match self {
|
|
|
|
WordSize::EightBit => vals::Ds::EIGHTBIT,
|
|
|
|
WordSize::SixteenBit => vals::Ds::SIXTEENBIT,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(spi_v2)]
|
|
|
|
pub fn frxth(&self) -> vals::Frxth {
|
|
|
|
match self {
|
|
|
|
WordSize::EightBit => vals::Frxth::QUARTER,
|
|
|
|
WordSize::SixteenBit => vals::Frxth::HALF,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
pub fn dsize(&self) -> u8 {
|
|
|
|
match self {
|
|
|
|
WordSize::EightBit => 0b0111,
|
|
|
|
WordSize::SixteenBit => 0b1111,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
pub fn _frxth(&self) -> vals::Fthlv {
|
|
|
|
match self {
|
|
|
|
WordSize::EightBit => vals::Fthlv::ONEFRAME,
|
|
|
|
WordSize::SixteenBit => vals::Fthlv::ONEFRAME,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2021-05-14 16:11:43 +02:00
|
|
|
}
|
|
|
|
|
2022-02-16 03:54:39 +01:00
|
|
|
pub trait Word: Copy + 'static + sealed::Word + Default {}
|
2022-01-19 17:29:47 +01:00
|
|
|
|
|
|
|
impl Word for u8 {}
|
|
|
|
impl Word for u16 {}
|
|
|
|
|
2021-07-20 19:38:44 +02:00
|
|
|
pub trait Instance: sealed::Instance + RccPeripheral {}
|
2022-02-10 21:38:03 +01:00
|
|
|
pin_trait!(SckPin, Instance);
|
|
|
|
pin_trait!(MosiPin, Instance);
|
|
|
|
pin_trait!(MisoPin, Instance);
|
|
|
|
dma_trait!(RxDma, Instance);
|
|
|
|
dma_trait!(TxDma, Instance);
|
2021-07-20 15:19:23 +02:00
|
|
|
|
2022-02-26 01:40:43 +01:00
|
|
|
foreach_peripheral!(
|
2021-06-03 17:09:29 +02:00
|
|
|
(spi, $inst:ident) => {
|
|
|
|
impl sealed::Instance for peripherals::$inst {
|
2021-05-14 16:11:43 +02:00
|
|
|
fn regs() -> &'static crate::pac::spi::Spi {
|
|
|
|
&crate::pac::$inst
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-06-03 17:09:29 +02:00
|
|
|
impl Instance for peripherals::$inst {}
|
2021-05-14 16:11:43 +02:00
|
|
|
};
|
2021-06-03 17:09:29 +02:00
|
|
|
);
|