2022-11-07 00:27:21 +01:00
|
|
|
use core::future::{poll_fn, Future};
|
|
|
|
use core::slice;
|
|
|
|
use core::task::Poll;
|
2022-08-26 09:05:12 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
|
|
|
|
use embassy_hal_common::atomic_ring_buffer::RingBuffer;
|
|
|
|
use embassy_sync::waitqueue::AtomicWaker;
|
2022-08-26 09:05:12 +02:00
|
|
|
|
|
|
|
use super::*;
|
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
pub struct State {
|
|
|
|
tx_waker: AtomicWaker,
|
|
|
|
tx_buf: RingBuffer,
|
|
|
|
rx_waker: AtomicWaker,
|
|
|
|
rx_buf: RingBuffer,
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
impl State {
|
2022-09-09 10:36:27 +02:00
|
|
|
pub const fn new() -> Self {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self {
|
|
|
|
rx_buf: RingBuffer::new(),
|
|
|
|
tx_buf: RingBuffer::new(),
|
|
|
|
rx_waker: AtomicWaker::new(),
|
|
|
|
tx_waker: AtomicWaker::new(),
|
|
|
|
}
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-08-26 09:05:12 +02:00
|
|
|
pub struct BufferedUart<'d, T: Instance> {
|
2022-11-07 00:27:21 +01:00
|
|
|
phantom: PhantomData<&'d mut T>,
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
pub struct BufferedUartRx<'d, T: Instance> {
|
2022-11-07 00:27:21 +01:00
|
|
|
phantom: PhantomData<&'d mut T>,
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
pub struct BufferedUartTx<'d, T: Instance> {
|
2022-11-07 00:27:21 +01:00
|
|
|
phantom: PhantomData<&'d mut T>,
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
|
2023-01-01 21:34:20 +01:00
|
|
|
fn init<'d, T: Instance + 'd>(
|
|
|
|
irq: PeripheralRef<'d, T::Interrupt>,
|
|
|
|
tx: Option<PeripheralRef<'d, AnyPin>>,
|
|
|
|
rx: Option<PeripheralRef<'d, AnyPin>>,
|
|
|
|
rts: Option<PeripheralRef<'d, AnyPin>>,
|
|
|
|
cts: Option<PeripheralRef<'d, AnyPin>>,
|
|
|
|
tx_buffer: &'d mut [u8],
|
|
|
|
rx_buffer: &'d mut [u8],
|
|
|
|
config: Config,
|
|
|
|
) {
|
|
|
|
let regs = T::regs();
|
|
|
|
unsafe {
|
|
|
|
regs.uartimsc().modify(|w| {
|
|
|
|
w.set_rxim(true);
|
|
|
|
w.set_rtim(true);
|
|
|
|
w.set_txim(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
super::Uart::<'d, T, Async>::init(tx, rx, rts, cts, config);
|
|
|
|
|
|
|
|
let state = T::state();
|
|
|
|
let len = tx_buffer.len();
|
|
|
|
unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
|
|
|
|
let len = rx_buffer.len();
|
|
|
|
unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
|
|
|
|
|
|
|
|
irq.set_handler(on_interrupt::<T>);
|
|
|
|
irq.unpend();
|
|
|
|
irq.enable();
|
|
|
|
}
|
|
|
|
|
2022-08-26 09:05:12 +02:00
|
|
|
impl<'d, T: Instance> BufferedUart<'d, T> {
|
2022-11-07 00:27:21 +01:00
|
|
|
pub fn new(
|
|
|
|
_uart: impl Peripheral<P = T> + 'd,
|
|
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
|
|
|
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
|
|
|
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
|
|
|
tx_buffer: &'d mut [u8],
|
|
|
|
rx_buffer: &'d mut [u8],
|
|
|
|
config: Config,
|
|
|
|
) -> Self {
|
2023-01-01 21:34:20 +01:00
|
|
|
into_ref!(irq, tx, rx);
|
|
|
|
init::<T>(
|
2022-11-07 00:27:21 +01:00
|
|
|
irq,
|
2023-01-01 21:34:20 +01:00
|
|
|
Some(tx.map_into()),
|
|
|
|
Some(rx.map_into()),
|
2022-11-07 00:27:21 +01:00
|
|
|
None,
|
|
|
|
None,
|
|
|
|
tx_buffer,
|
|
|
|
rx_buffer,
|
|
|
|
config,
|
2023-01-01 21:34:20 +01:00
|
|
|
);
|
|
|
|
Self { phantom: PhantomData }
|
2022-11-07 00:27:21 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
pub fn new_with_rtscts(
|
|
|
|
_uart: impl Peripheral<P = T> + 'd,
|
2022-08-26 09:05:12 +02:00
|
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
2022-11-07 00:27:21 +01:00
|
|
|
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
|
|
|
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
|
|
|
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
|
|
|
|
cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
|
2022-08-26 09:05:12 +02:00
|
|
|
tx_buffer: &'d mut [u8],
|
|
|
|
rx_buffer: &'d mut [u8],
|
2022-11-07 00:27:21 +01:00
|
|
|
config: Config,
|
|
|
|
) -> Self {
|
2023-01-01 21:34:20 +01:00
|
|
|
into_ref!(irq, tx, rx, cts, rts);
|
|
|
|
init::<T>(
|
2022-11-07 00:27:21 +01:00
|
|
|
irq,
|
2023-01-01 21:34:20 +01:00
|
|
|
Some(tx.map_into()),
|
|
|
|
Some(rx.map_into()),
|
2022-11-07 00:27:21 +01:00
|
|
|
Some(rts.map_into()),
|
|
|
|
Some(cts.map_into()),
|
|
|
|
tx_buffer,
|
|
|
|
rx_buffer,
|
|
|
|
config,
|
|
|
|
);
|
|
|
|
Self { phantom: PhantomData }
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
2022-12-22 23:03:05 +01:00
|
|
|
|
|
|
|
pub fn split(&mut self) -> (BufferedUartRx<'d, T>, BufferedUartTx<'d, T>) {
|
|
|
|
(
|
|
|
|
BufferedUartRx { phantom: PhantomData },
|
|
|
|
BufferedUartTx { phantom: PhantomData },
|
|
|
|
)
|
|
|
|
}
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance> BufferedUartRx<'d, T> {
|
2022-11-07 00:27:21 +01:00
|
|
|
pub fn new(
|
|
|
|
_uart: impl Peripheral<P = T> + 'd,
|
2022-09-09 10:36:27 +02:00
|
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
2022-11-07 00:27:21 +01:00
|
|
|
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
2022-09-09 10:36:27 +02:00
|
|
|
rx_buffer: &'d mut [u8],
|
2022-11-07 00:27:21 +01:00
|
|
|
config: Config,
|
|
|
|
) -> Self {
|
2023-01-01 21:34:20 +01:00
|
|
|
into_ref!(irq, rx);
|
|
|
|
init::<T>(irq, None, Some(rx.map_into()), None, None, &mut [], rx_buffer, config);
|
|
|
|
Self { phantom: PhantomData }
|
2022-11-07 00:27:21 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
pub fn new_with_rts(
|
|
|
|
_uart: impl Peripheral<P = T> + 'd,
|
|
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
|
|
|
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
|
|
|
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
|
|
|
|
rx_buffer: &'d mut [u8],
|
|
|
|
config: Config,
|
|
|
|
) -> Self {
|
2023-01-01 21:34:20 +01:00
|
|
|
into_ref!(irq, rx, rts);
|
|
|
|
init::<T>(
|
|
|
|
irq,
|
2022-11-07 00:27:21 +01:00
|
|
|
None,
|
2023-01-01 21:34:20 +01:00
|
|
|
Some(rx.map_into()),
|
|
|
|
Some(rts.map_into()),
|
2022-11-07 00:27:21 +01:00
|
|
|
None,
|
2023-01-01 21:34:20 +01:00
|
|
|
&mut [],
|
|
|
|
rx_buffer,
|
2022-11-07 00:27:21 +01:00
|
|
|
config,
|
|
|
|
);
|
|
|
|
Self { phantom: PhantomData }
|
|
|
|
}
|
|
|
|
|
|
|
|
fn read<'a>(buf: &'a mut [u8]) -> impl Future<Output = Result<usize, Error>> + 'a {
|
|
|
|
poll_fn(move |cx| {
|
|
|
|
let state = T::state();
|
|
|
|
let mut rx_reader = unsafe { state.rx_buf.reader() };
|
|
|
|
let n = rx_reader.pop(|data| {
|
|
|
|
let n = data.len().min(buf.len());
|
|
|
|
buf[..n].copy_from_slice(&data[..n]);
|
|
|
|
n
|
|
|
|
});
|
|
|
|
if n == 0 {
|
|
|
|
state.rx_waker.register(cx.waker());
|
|
|
|
return Poll::Pending;
|
|
|
|
}
|
|
|
|
|
|
|
|
Poll::Ready(Ok(n))
|
|
|
|
})
|
|
|
|
}
|
|
|
|
|
|
|
|
fn fill_buf<'a>() -> impl Future<Output = Result<&'a [u8], Error>> {
|
|
|
|
poll_fn(move |cx| {
|
|
|
|
let state = T::state();
|
|
|
|
let mut rx_reader = unsafe { state.rx_buf.reader() };
|
|
|
|
let (p, n) = rx_reader.pop_buf();
|
|
|
|
if n == 0 {
|
|
|
|
state.rx_waker.register(cx.waker());
|
|
|
|
return Poll::Pending;
|
|
|
|
}
|
|
|
|
|
|
|
|
let buf = unsafe { slice::from_raw_parts(p, n) };
|
|
|
|
Poll::Ready(Ok(buf))
|
|
|
|
})
|
|
|
|
}
|
|
|
|
|
|
|
|
fn consume(amt: usize) {
|
|
|
|
let state = T::state();
|
|
|
|
let mut rx_reader = unsafe { state.rx_buf.reader() };
|
2023-01-01 21:34:20 +01:00
|
|
|
rx_reader.pop_done(amt);
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance> BufferedUartTx<'d, T> {
|
2022-11-07 00:27:21 +01:00
|
|
|
pub fn new(
|
|
|
|
_uart: impl Peripheral<P = T> + 'd,
|
2022-09-09 10:36:27 +02:00
|
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
2022-11-07 00:27:21 +01:00
|
|
|
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
2022-09-09 10:36:27 +02:00
|
|
|
tx_buffer: &'d mut [u8],
|
2022-11-07 00:27:21 +01:00
|
|
|
config: Config,
|
|
|
|
) -> Self {
|
2023-01-01 21:34:20 +01:00
|
|
|
into_ref!(irq, tx);
|
|
|
|
init::<T>(irq, Some(tx.map_into()), None, None, None, tx_buffer, &mut [], config);
|
|
|
|
Self { phantom: PhantomData }
|
2022-11-07 00:27:21 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
pub fn new_with_cts(
|
|
|
|
_uart: impl Peripheral<P = T> + 'd,
|
|
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
|
|
|
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
|
|
|
cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
|
|
|
|
tx_buffer: &'d mut [u8],
|
|
|
|
config: Config,
|
|
|
|
) -> Self {
|
2023-01-01 21:34:20 +01:00
|
|
|
into_ref!(irq, tx, cts);
|
|
|
|
init::<T>(
|
|
|
|
irq,
|
|
|
|
Some(tx.map_into()),
|
2022-11-07 00:27:21 +01:00
|
|
|
None,
|
|
|
|
None,
|
2023-01-01 21:34:20 +01:00
|
|
|
Some(cts.map_into()),
|
|
|
|
tx_buffer,
|
|
|
|
&mut [],
|
2022-11-07 00:27:21 +01:00
|
|
|
config,
|
|
|
|
);
|
|
|
|
Self { phantom: PhantomData }
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
fn write<'a>(buf: &'a [u8]) -> impl Future<Output = Result<usize, Error>> + 'a {
|
|
|
|
poll_fn(move |cx| {
|
|
|
|
let state = T::state();
|
|
|
|
let mut tx_writer = unsafe { state.tx_buf.writer() };
|
|
|
|
let n = tx_writer.push(|data| {
|
|
|
|
let n = data.len().min(buf.len());
|
|
|
|
data[..n].copy_from_slice(&buf[..n]);
|
|
|
|
n
|
|
|
|
});
|
|
|
|
if n == 0 {
|
|
|
|
state.tx_waker.register(cx.waker());
|
|
|
|
return Poll::Pending;
|
|
|
|
}
|
|
|
|
|
2023-01-01 21:34:20 +01:00
|
|
|
unsafe { T::Interrupt::steal() }.pend();
|
2022-11-07 00:27:21 +01:00
|
|
|
Poll::Ready(Ok(n))
|
|
|
|
})
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
fn flush() -> impl Future<Output = Result<(), Error>> {
|
|
|
|
poll_fn(move |cx| {
|
|
|
|
let state = T::state();
|
|
|
|
if !state.tx_buf.is_empty() {
|
|
|
|
state.tx_waker.register(cx.waker());
|
|
|
|
return Poll::Pending;
|
2022-09-21 06:00:35 +02:00
|
|
|
}
|
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
Poll::Ready(Ok(()))
|
|
|
|
})
|
2022-09-21 06:00:35 +02:00
|
|
|
}
|
2022-11-07 00:27:21 +01:00
|
|
|
}
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
impl<'d, T: Instance> Drop for BufferedUart<'d, T> {
|
|
|
|
fn drop(&mut self) {
|
|
|
|
unsafe {
|
|
|
|
T::Interrupt::steal().disable();
|
|
|
|
let state = T::state();
|
|
|
|
state.tx_buf.deinit();
|
|
|
|
state.rx_buf.deinit();
|
2022-09-21 06:00:35 +02:00
|
|
|
}
|
|
|
|
}
|
2022-11-07 00:27:21 +01:00
|
|
|
}
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
impl<'d, T: Instance> Drop for BufferedUartRx<'d, T> {
|
|
|
|
fn drop(&mut self) {
|
|
|
|
unsafe {
|
|
|
|
T::Interrupt::steal().disable();
|
|
|
|
let state = T::state();
|
|
|
|
state.tx_buf.deinit();
|
|
|
|
state.rx_buf.deinit();
|
|
|
|
}
|
2022-09-21 06:00:35 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
impl<'d, T: Instance> Drop for BufferedUartTx<'d, T> {
|
|
|
|
fn drop(&mut self) {
|
2022-08-26 09:05:12 +02:00
|
|
|
unsafe {
|
2022-11-07 00:27:21 +01:00
|
|
|
T::Interrupt::steal().disable();
|
|
|
|
let state = T::state();
|
|
|
|
state.tx_buf.deinit();
|
|
|
|
state.rx_buf.deinit();
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
2022-08-26 09:05:12 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
pub(crate) unsafe fn on_interrupt<T: Instance>(_: *mut ()) {
|
|
|
|
trace!("on_interrupt");
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
let r = T::regs();
|
|
|
|
let s = T::state();
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
unsafe {
|
|
|
|
// RX
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
let ris = r.uartris().read();
|
|
|
|
// Clear interrupt flags
|
|
|
|
r.uarticr().write(|w| {
|
|
|
|
w.set_rxic(true);
|
|
|
|
w.set_rtic(true);
|
|
|
|
});
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
if ris.peris() {
|
|
|
|
warn!("Parity error");
|
|
|
|
r.uarticr().write(|w| {
|
|
|
|
w.set_peic(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
if ris.feris() {
|
|
|
|
warn!("Framing error");
|
|
|
|
r.uarticr().write(|w| {
|
|
|
|
w.set_feic(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
if ris.beris() {
|
|
|
|
warn!("Break error");
|
|
|
|
r.uarticr().write(|w| {
|
|
|
|
w.set_beic(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
if ris.oeris() {
|
|
|
|
warn!("Overrun error");
|
|
|
|
r.uarticr().write(|w| {
|
|
|
|
w.set_oeic(true);
|
|
|
|
});
|
|
|
|
}
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
let mut rx_writer = s.rx_buf.writer();
|
2022-12-27 10:20:51 +01:00
|
|
|
let rx_buf = rx_writer.push_slice();
|
|
|
|
let mut n_read = 0;
|
|
|
|
for rx_byte in rx_buf {
|
|
|
|
if r.uartfr().read().rxfe() {
|
|
|
|
break;
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
2022-12-27 10:20:51 +01:00
|
|
|
*rx_byte = r.uartdr().read().data();
|
|
|
|
n_read += 1;
|
|
|
|
}
|
|
|
|
if n_read > 0 {
|
|
|
|
rx_writer.push_done(n_read);
|
2022-11-07 00:27:21 +01:00
|
|
|
s.rx_waker.wake();
|
|
|
|
}
|
|
|
|
|
|
|
|
// TX
|
|
|
|
let mut tx_reader = s.tx_buf.reader();
|
2022-12-27 10:20:51 +01:00
|
|
|
let tx_buf = tx_reader.pop_slice();
|
|
|
|
if tx_buf.len() == 0 {
|
|
|
|
// Disable interrupt until we have something to transmit again
|
2022-11-07 00:27:21 +01:00
|
|
|
r.uartimsc().modify(|w| {
|
2022-12-27 10:20:51 +01:00
|
|
|
w.set_txim(false);
|
2022-11-07 00:27:21 +01:00
|
|
|
});
|
|
|
|
} else {
|
|
|
|
r.uartimsc().modify(|w| {
|
2022-12-27 10:20:51 +01:00
|
|
|
w.set_txim(true);
|
2022-11-07 00:27:21 +01:00
|
|
|
});
|
2022-12-27 10:20:51 +01:00
|
|
|
|
|
|
|
let mut n_written = 0;
|
|
|
|
for tx_byte in tx_buf.iter_mut() {
|
|
|
|
if r.uartfr().read().txff() {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
r.uartdr().write(|w| w.set_data(*tx_byte));
|
|
|
|
n_written += 1;
|
|
|
|
}
|
|
|
|
if n_written > 0 {
|
|
|
|
tx_reader.pop_done(n_written);
|
|
|
|
s.tx_waker.wake();
|
|
|
|
}
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl embedded_io::Error for Error {
|
|
|
|
fn kind(&self) -> embedded_io::ErrorKind {
|
|
|
|
embedded_io::ErrorKind::Other
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embedded_io::Io for BufferedUart<'d, T> {
|
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance> embedded_io::Io for BufferedUartRx<'d, T> {
|
2022-09-09 10:36:27 +02:00
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance> embedded_io::Io for BufferedUartTx<'d, T> {
|
2022-09-09 10:36:27 +02:00
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-08-26 09:05:12 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUart<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
BufferedUartRx::<'d, T>::read(buf).await
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUartRx<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self::read(buf).await
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUart<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
BufferedUartRx::<'d, T>::fill_buf().await
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
fn consume(&mut self, amt: usize) {
|
2022-11-07 00:27:21 +01:00
|
|
|
BufferedUartRx::<'d, T>::consume(amt)
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUartRx<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self::fill_buf().await
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
fn consume(&mut self, amt: usize) {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self::consume(amt)
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUart<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
BufferedUartTx::<'d, T>::write(buf).await
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
BufferedUartTx::<'d, T>::flush().await
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUartTx<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self::write(buf).await
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self::flush().await
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|