2023-02-01 00:48:33 +01:00
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//! Successive Approximation Analog-to-Digital Converter (SAADC) driver.
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2021-10-11 01:22:01 +02:00
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#![macro_use]
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2022-09-22 16:42:49 +02:00
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use core::future::poll_fn;
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2021-03-24 18:33:17 +01:00
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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2022-06-12 22:15:44 +02:00
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2023-07-28 13:23:22 +02:00
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use embassy_hal_internal::drop::OnDrop;
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use embassy_hal_internal::{impl_peripheral, into_ref, PeripheralRef};
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2022-08-22 21:46:09 +02:00
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use embassy_sync::waitqueue::AtomicWaker;
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2021-03-24 18:33:17 +01:00
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use pac::{saadc, SAADC};
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2022-06-12 22:15:44 +02:00
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use saadc::ch::config::{GAIN_A, REFSEL_A, RESP_A, TACQ_A};
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2021-10-13 22:01:49 +02:00
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// We treat the positive and negative channels with the same enum values to keep our type tidy and given they are the same
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pub(crate) use saadc::ch::pselp::PSELP_A as InputChannel;
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2022-06-12 22:15:44 +02:00
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use saadc::oversample::OVERSAMPLE_A;
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use saadc::resolution::VAL_A;
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2021-10-13 22:01:49 +02:00
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2022-07-23 15:13:47 +02:00
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use self::sealed::Input as _;
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2023-06-08 16:08:40 +02:00
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use crate::interrupt::InterruptExt;
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2022-06-12 22:15:44 +02:00
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use crate::ppi::{ConfigurableChannel, Event, Ppi, Task};
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use crate::timer::{Frequency, Instance as TimerInstance, Timer};
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2022-07-23 14:00:19 +02:00
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use crate::{interrupt, pac, peripherals, Peripheral};
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2021-03-24 18:33:17 +01:00
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2023-02-01 00:48:33 +01:00
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/// SAADC error
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2021-03-24 18:33:17 +01:00
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {}
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2023-03-05 21:56:22 +01:00
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/// Interrupt handler.
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pub struct InterruptHandler {
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_private: (),
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}
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2023-06-08 16:08:40 +02:00
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impl interrupt::typelevel::Handler<interrupt::typelevel::SAADC> for InterruptHandler {
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2023-03-05 21:56:22 +01:00
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unsafe fn on_interrupt() {
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let r = unsafe { &*SAADC::ptr() };
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if r.events_calibratedone.read().bits() != 0 {
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r.intenclr.write(|w| w.calibratedone().clear());
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WAKER.wake();
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}
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if r.events_end.read().bits() != 0 {
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r.intenclr.write(|w| w.end().clear());
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WAKER.wake();
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}
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if r.events_started.read().bits() != 0 {
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r.intenclr.write(|w| w.started().clear());
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WAKER.wake();
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}
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}
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2021-03-24 18:33:17 +01:00
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}
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2021-09-01 23:54:26 +02:00
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static WAKER: AtomicWaker = AtomicWaker::new();
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2021-03-24 18:33:17 +01:00
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/// Used to configure the SAADC peripheral.
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///
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/// See the `Default` impl for suitable default values.
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2021-10-07 09:00:03 +02:00
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#[non_exhaustive]
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2021-03-24 18:33:17 +01:00
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pub struct Config {
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/// Output resolution in bits.
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pub resolution: Resolution,
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/// Average 2^`oversample` input samples before transferring the result into memory.
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pub oversample: Oversample,
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2021-10-07 09:00:03 +02:00
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}
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impl Default for Config {
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/// Default configuration for single channel sampling.
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fn default() -> Self {
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Self {
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2021-10-12 02:24:26 +02:00
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resolution: Resolution::_12BIT,
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2021-10-07 09:00:03 +02:00
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oversample: Oversample::BYPASS,
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}
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}
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}
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/// Used to configure an individual SAADC peripheral channel.
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///
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/// See the `Default` impl for suitable default values.
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#[non_exhaustive]
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2021-10-10 23:52:45 +02:00
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pub struct ChannelConfig<'d> {
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2021-03-24 18:33:17 +01:00
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/// Reference voltage of the SAADC input.
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pub reference: Reference,
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/// Gain used to control the effective input range of the SAADC.
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pub gain: Gain,
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/// Positive channel resistor control.
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pub resistor: Resistor,
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/// Acquisition time in microseconds.
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pub time: Time,
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2021-10-07 09:00:03 +02:00
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/// Positive channel to sample
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2022-07-23 15:13:47 +02:00
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p_channel: PeripheralRef<'d, AnyInput>,
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2021-10-07 09:00:03 +02:00
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/// An optional negative channel to sample
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2022-07-23 15:13:47 +02:00
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n_channel: Option<PeripheralRef<'d, AnyInput>>,
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2022-07-21 16:42:46 +02:00
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}
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2021-10-10 23:52:45 +02:00
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impl<'d> ChannelConfig<'d> {
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2021-10-07 09:00:03 +02:00
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/// Default configuration for single ended channel sampling.
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2022-07-23 14:00:19 +02:00
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pub fn single_ended(input: impl Peripheral<P = impl Input> + 'd) -> Self {
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into_ref!(input);
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2021-10-07 09:00:03 +02:00
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Self {
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reference: Reference::INTERNAL,
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gain: Gain::GAIN1_6,
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resistor: Resistor::BYPASS,
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time: Time::_10US,
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2022-07-23 15:13:47 +02:00
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p_channel: input.map_into(),
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2021-10-07 09:00:03 +02:00
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n_channel: None,
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}
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}
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/// Default configuration for differential channel sampling.
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pub fn differential(
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2022-07-23 14:00:19 +02:00
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p_input: impl Peripheral<P = impl Input> + 'd,
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n_input: impl Peripheral<P = impl Input> + 'd,
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2021-10-07 09:00:03 +02:00
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) -> Self {
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2022-07-23 14:00:19 +02:00
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into_ref!(p_input, n_input);
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2021-03-24 18:33:17 +01:00
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Self {
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2021-10-15 09:45:53 +02:00
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reference: Reference::INTERNAL,
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2021-10-07 09:00:03 +02:00
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gain: Gain::GAIN1_6,
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2021-03-24 18:33:17 +01:00
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resistor: Resistor::BYPASS,
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2021-10-07 09:00:03 +02:00
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time: Time::_10US,
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2022-07-23 15:13:47 +02:00
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p_channel: p_input.map_into(),
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n_channel: Some(n_input.map_into()),
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2021-03-24 18:33:17 +01:00
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}
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}
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}
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2023-02-01 00:48:33 +01:00
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/// Value returned by the SAADC callback, deciding what happens next.
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2021-10-12 02:24:26 +02:00
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#[derive(PartialEq)]
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2023-02-01 00:48:33 +01:00
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pub enum CallbackResult {
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/// The SAADC should keep sampling and calling the callback.
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Continue,
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/// The SAADC should stop sampling, and return.
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Stop,
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2021-10-12 02:24:26 +02:00
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}
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2023-03-05 21:56:22 +01:00
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/// One-shot and continuous SAADC.
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pub struct Saadc<'d, const N: usize> {
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_p: PeripheralRef<'d, peripherals::SAADC>,
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}
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2021-10-12 02:24:26 +02:00
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impl<'d, const N: usize> Saadc<'d, N> {
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2023-02-01 00:48:33 +01:00
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/// Create a new SAADC driver.
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2021-03-24 18:33:17 +01:00
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pub fn new(
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2022-07-23 15:13:47 +02:00
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saadc: impl Peripheral<P = peripherals::SAADC> + 'd,
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2023-06-08 16:08:40 +02:00
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_irq: impl interrupt::typelevel::Binding<interrupt::typelevel::SAADC, InterruptHandler> + 'd,
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2021-03-24 18:33:17 +01:00
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config: Config,
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2021-10-07 09:00:03 +02:00
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channel_configs: [ChannelConfig; N],
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2021-03-24 18:33:17 +01:00
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) -> Self {
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2023-03-05 21:56:22 +01:00
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into_ref!(saadc);
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2021-03-24 18:33:17 +01:00
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let r = unsafe { &*SAADC::ptr() };
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2022-06-12 22:15:44 +02:00
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let Config { resolution, oversample } = config;
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2021-03-24 18:33:17 +01:00
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2021-10-07 09:00:03 +02:00
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// Configure channels
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2021-03-24 18:33:17 +01:00
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r.enable.write(|w| w.enable().enabled());
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2021-11-21 02:02:59 +01:00
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r.resolution.write(|w| w.val().variant(resolution.into()));
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2022-06-12 22:15:44 +02:00
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r.oversample.write(|w| w.oversample().variant(oversample.into()));
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2021-03-24 18:33:17 +01:00
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2021-10-07 09:00:03 +02:00
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for (i, cc) in channel_configs.iter().enumerate() {
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2022-07-23 15:13:47 +02:00
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r.ch[i].pselp.write(|w| w.pselp().variant(cc.p_channel.channel()));
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if let Some(n_channel) = &cc.n_channel {
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r.ch[i]
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.pseln
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.write(|w| unsafe { w.pseln().bits(n_channel.channel() as u8) });
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2021-03-24 18:33:17 +01:00
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}
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2021-10-07 09:00:03 +02:00
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r.ch[i].config.write(|w| {
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2021-11-21 02:02:59 +01:00
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w.refsel().variant(cc.reference.into());
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w.gain().variant(cc.gain.into());
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w.tacq().variant(cc.time.into());
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2021-10-07 09:00:03 +02:00
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if cc.n_channel.is_none() {
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w.mode().se();
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} else {
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w.mode().diff();
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}
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2021-11-21 02:02:59 +01:00
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w.resp().variant(cc.resistor.into());
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2021-10-07 09:00:03 +02:00
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w.resn().bypass();
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if !matches!(oversample, Oversample::BYPASS) {
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w.burst().enabled();
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} else {
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w.burst().disabled();
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}
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w
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});
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}
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2021-03-24 18:33:17 +01:00
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0x003F_FFFF) });
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2023-06-08 16:08:40 +02:00
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interrupt::SAADC.unpend();
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unsafe { interrupt::SAADC.enable() };
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2021-09-01 23:54:26 +02:00
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2022-07-23 15:13:47 +02:00
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Self { _p: saadc }
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2021-03-24 18:33:17 +01:00
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}
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2021-09-01 23:54:26 +02:00
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fn regs() -> &'static saadc::RegisterBlock {
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2021-03-24 18:33:17 +01:00
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unsafe { &*SAADC::ptr() }
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}
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2021-05-22 15:42:14 +02:00
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2022-02-26 08:15:37 +01:00
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/// Perform SAADC calibration. Completes when done.
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pub async fn calibrate(&self) {
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let r = Self::regs();
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// Reset and enable the end event
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r.events_calibratedone.reset();
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r.intenset.write(|w| w.calibratedone().set());
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// Order is important
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compiler_fence(Ordering::SeqCst);
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r.tasks_calibrateoffset.write(|w| unsafe { w.bits(1) });
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// Wait for 'calibratedone' event.
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poll_fn(|cx| {
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let r = Self::regs();
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WAKER.register(cx.waker());
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if r.events_calibratedone.read().bits() != 0 {
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r.events_calibratedone.reset();
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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}
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2021-10-12 02:24:26 +02:00
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/// One shot sampling. The buffer must be the same size as the number of channels configured.
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2022-08-30 01:49:04 +02:00
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/// The sampling is stopped prior to returning in order to reduce power consumption (power
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2022-08-30 12:56:56 +02:00
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/// consumption remains higher if sampling is not stopped explicitly). Cancellation will
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/// also cause the sampling to be stopped.
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2021-10-07 09:00:03 +02:00
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pub async fn sample(&mut self, buf: &mut [i16; N]) {
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2022-08-30 12:56:56 +02:00
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// In case the future is dropped, stop the task and wait for it to end.
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2023-01-18 04:17:50 +01:00
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let on_drop = OnDrop::new(Self::stop_sampling_immediately);
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2022-08-30 12:56:56 +02:00
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2021-09-01 23:54:26 +02:00
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let r = Self::regs();
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2021-05-22 15:42:14 +02:00
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// Set up the DMA
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2022-06-12 22:15:44 +02:00
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r.result.ptr.write(|w| unsafe { w.ptr().bits(buf.as_mut_ptr() as u32) });
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r.result.maxcnt.write(|w| unsafe { w.maxcnt().bits(N as _) });
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2021-05-22 15:42:14 +02:00
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// Reset and enable the end event
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r.events_end.reset();
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r.intenset.write(|w| w.end().set());
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// Don't reorder the ADC start event before the previous writes. Hopefully self
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// wouldn't happen anyway.
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compiler_fence(Ordering::SeqCst);
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r.tasks_start.write(|w| unsafe { w.bits(1) });
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r.tasks_sample.write(|w| unsafe { w.bits(1) });
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// Wait for 'end' event.
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poll_fn(|cx| {
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2021-09-01 23:54:26 +02:00
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let r = Self::regs();
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WAKER.register(cx.waker());
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2021-05-22 15:42:14 +02:00
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if r.events_end.read().bits() != 0 {
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r.events_end.reset();
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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2023-01-18 04:17:50 +01:00
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drop(on_drop);
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2021-05-22 15:42:14 +02:00
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}
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2021-10-12 02:24:26 +02:00
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2021-10-18 02:45:23 +02:00
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/// Continuous sampling with double buffers.
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2021-10-16 21:56:56 +02:00
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///
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2022-03-07 02:45:37 +01:00
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/// A TIMER and two PPI peripherals are passed in so that precise sampling
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/// can be attained. The sampling interval is expressed by selecting a
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/// timer clock frequency to use along with a counter threshold to be reached.
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/// For example, 1KHz can be achieved using a frequency of 1MHz and a counter
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/// threshold of 1000.
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2022-02-26 08:15:37 +01:00
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///
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2021-10-16 21:56:56 +02:00
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/// A sampler closure is provided that receives the buffer of samples, noting
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/// that the size of this buffer can be less than the original buffer's size.
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/// A command is return from the closure that indicates whether the sampling
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/// should continue or stop.
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2022-03-07 02:45:37 +01:00
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///
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/// NOTE: The time spent within the callback supplied should not exceed the time
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/// taken to acquire the samples into a single buffer. You should measure the
|
|
|
|
/// time taken by the callback and set the sample buffer size accordingly.
|
|
|
|
/// Exceeding this time can lead to samples becoming dropped.
|
2022-08-30 12:56:56 +02:00
|
|
|
///
|
|
|
|
/// The sampling is stopped prior to returning in order to reduce power consumption (power
|
|
|
|
/// consumption remains higher if sampling is not stopped explicitly), and to
|
|
|
|
/// free the buffers from being used by the peripheral. Cancellation will
|
|
|
|
/// also cause the sampling to be stopped.
|
|
|
|
|
2023-02-01 00:48:33 +01:00
|
|
|
pub async fn run_task_sampler<F, T: TimerInstance, const N0: usize>(
|
2021-10-16 21:56:56 +02:00
|
|
|
&mut self,
|
2022-03-07 02:45:37 +01:00
|
|
|
timer: &mut T,
|
|
|
|
ppi_ch1: &mut impl ConfigurableChannel,
|
|
|
|
ppi_ch2: &mut impl ConfigurableChannel,
|
|
|
|
frequency: Frequency,
|
|
|
|
sample_counter: u32,
|
2021-10-16 22:51:53 +02:00
|
|
|
bufs: &mut [[[i16; N]; N0]; 2],
|
2023-02-01 00:48:33 +01:00
|
|
|
callback: F,
|
2021-10-16 21:56:56 +02:00
|
|
|
) where
|
2023-02-01 00:48:33 +01:00
|
|
|
F: FnMut(&[[i16; N]]) -> CallbackResult,
|
2021-10-16 21:56:56 +02:00
|
|
|
{
|
2022-03-07 02:45:37 +01:00
|
|
|
let r = Self::regs();
|
|
|
|
|
|
|
|
// We want the task start to effectively short with the last one ending so
|
|
|
|
// we don't miss any samples. It'd be great for the SAADC to offer a SHORTS
|
|
|
|
// register instead, but it doesn't, so we must use PPI.
|
2022-06-12 22:15:44 +02:00
|
|
|
let mut start_ppi =
|
|
|
|
Ppi::new_one_to_one(ppi_ch1, Event::from_reg(&r.events_end), Task::from_reg(&r.tasks_start));
|
2022-03-07 02:45:37 +01:00
|
|
|
start_ppi.enable();
|
|
|
|
|
2023-04-11 23:00:14 +02:00
|
|
|
let timer = Timer::new(timer);
|
2022-03-07 02:45:37 +01:00
|
|
|
timer.set_frequency(frequency);
|
|
|
|
timer.cc(0).write(sample_counter);
|
|
|
|
timer.cc(0).short_compare_clear();
|
|
|
|
|
2023-06-30 11:50:27 +02:00
|
|
|
let timer_cc = timer.cc(0);
|
2023-06-30 11:47:20 +02:00
|
|
|
|
2023-06-30 11:50:27 +02:00
|
|
|
let mut sample_ppi = Ppi::new_one_to_one(ppi_ch2, timer_cc.event_compare(), Task::from_reg(&r.tasks_sample));
|
2022-03-07 02:45:37 +01:00
|
|
|
|
|
|
|
timer.start();
|
|
|
|
|
|
|
|
self.run_sampler(
|
|
|
|
bufs,
|
|
|
|
None,
|
|
|
|
|| {
|
|
|
|
sample_ppi.enable();
|
|
|
|
},
|
2023-02-01 00:48:33 +01:00
|
|
|
callback,
|
2022-03-07 02:45:37 +01:00
|
|
|
)
|
|
|
|
.await;
|
2021-10-16 21:56:56 +02:00
|
|
|
}
|
|
|
|
|
2023-02-01 00:48:33 +01:00
|
|
|
async fn run_sampler<I, F, const N0: usize>(
|
2021-10-12 02:24:26 +02:00
|
|
|
&mut self,
|
2021-10-16 22:51:53 +02:00
|
|
|
bufs: &mut [[[i16; N]; N0]; 2],
|
2021-10-18 02:42:30 +02:00
|
|
|
sample_rate_divisor: Option<u16>,
|
2022-02-26 08:15:37 +01:00
|
|
|
mut init: I,
|
2023-02-01 00:48:33 +01:00
|
|
|
mut callback: F,
|
2021-10-12 02:24:26 +02:00
|
|
|
) where
|
2022-02-26 08:15:37 +01:00
|
|
|
I: FnMut(),
|
2023-02-01 00:48:33 +01:00
|
|
|
F: FnMut(&[[i16; N]]) -> CallbackResult,
|
2021-10-12 02:24:26 +02:00
|
|
|
{
|
2022-08-30 12:56:56 +02:00
|
|
|
// In case the future is dropped, stop the task and wait for it to end.
|
2023-01-18 04:17:50 +01:00
|
|
|
let on_drop = OnDrop::new(Self::stop_sampling_immediately);
|
2022-08-30 12:56:56 +02:00
|
|
|
|
2021-10-12 02:24:26 +02:00
|
|
|
let r = Self::regs();
|
|
|
|
|
|
|
|
// Establish mode and sample rate
|
2021-10-18 02:42:30 +02:00
|
|
|
match sample_rate_divisor {
|
2021-10-16 21:56:56 +02:00
|
|
|
Some(sr) => {
|
2021-10-16 21:26:06 +02:00
|
|
|
r.samplerate.write(|w| unsafe {
|
2021-10-16 21:56:56 +02:00
|
|
|
w.cc().bits(sr);
|
2021-10-16 21:26:06 +02:00
|
|
|
w.mode().timers();
|
2021-10-14 23:12:13 +02:00
|
|
|
w
|
|
|
|
});
|
|
|
|
r.tasks_sample.write(|w| unsafe { w.bits(1) }); // Need to kick-start the internal timer
|
|
|
|
}
|
2021-10-16 21:56:56 +02:00
|
|
|
None => r.samplerate.write(|w| unsafe {
|
2021-10-16 21:26:06 +02:00
|
|
|
w.cc().bits(0);
|
|
|
|
w.mode().task();
|
2021-10-12 02:24:26 +02:00
|
|
|
w
|
|
|
|
}),
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set up the initial DMA
|
|
|
|
r.result
|
|
|
|
.ptr
|
|
|
|
.write(|w| unsafe { w.ptr().bits(bufs[0].as_mut_ptr() as u32) });
|
2022-06-12 22:15:44 +02:00
|
|
|
r.result.maxcnt.write(|w| unsafe { w.maxcnt().bits((N0 * N) as _) });
|
2021-10-12 02:24:26 +02:00
|
|
|
|
|
|
|
// Reset and enable the events
|
|
|
|
r.events_end.reset();
|
|
|
|
r.events_started.reset();
|
2021-10-16 21:28:19 +02:00
|
|
|
r.intenset.write(|w| {
|
|
|
|
w.end().set();
|
|
|
|
w.started().set();
|
|
|
|
w
|
|
|
|
});
|
2021-10-12 02:24:26 +02:00
|
|
|
|
|
|
|
// Don't reorder the ADC start event before the previous writes. Hopefully self
|
|
|
|
// wouldn't happen anyway.
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
|
|
|
|
r.tasks_start.write(|w| unsafe { w.bits(1) });
|
|
|
|
|
2022-02-26 08:15:37 +01:00
|
|
|
let mut inited = false;
|
|
|
|
|
2021-10-12 02:24:26 +02:00
|
|
|
let mut current_buffer = 0;
|
|
|
|
|
|
|
|
// Wait for events and complete when the sampler indicates it has had enough.
|
2023-01-18 04:17:50 +01:00
|
|
|
let r = poll_fn(|cx| {
|
2021-10-12 02:24:26 +02:00
|
|
|
let r = Self::regs();
|
|
|
|
|
|
|
|
WAKER.register(cx.waker());
|
|
|
|
|
|
|
|
if r.events_end.read().bits() != 0 {
|
2021-10-18 02:28:43 +02:00
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
|
2021-10-12 02:24:26 +02:00
|
|
|
r.events_end.reset();
|
|
|
|
r.intenset.write(|w| w.end().set());
|
|
|
|
|
2023-02-01 00:48:33 +01:00
|
|
|
match callback(&bufs[current_buffer]) {
|
|
|
|
CallbackResult::Continue => {
|
|
|
|
let next_buffer = 1 - current_buffer;
|
|
|
|
current_buffer = next_buffer;
|
|
|
|
}
|
|
|
|
CallbackResult::Stop => {
|
|
|
|
return Poll::Ready(());
|
|
|
|
}
|
|
|
|
}
|
2021-10-12 02:24:26 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if r.events_started.read().bits() != 0 {
|
|
|
|
r.events_started.reset();
|
|
|
|
r.intenset.write(|w| w.started().set());
|
|
|
|
|
2022-02-26 08:15:37 +01:00
|
|
|
if !inited {
|
|
|
|
init();
|
|
|
|
inited = true;
|
|
|
|
}
|
|
|
|
|
2021-10-12 02:24:26 +02:00
|
|
|
let next_buffer = 1 - current_buffer;
|
|
|
|
r.result
|
|
|
|
.ptr
|
|
|
|
.write(|w| unsafe { w.ptr().bits(bufs[next_buffer].as_mut_ptr() as u32) });
|
|
|
|
}
|
|
|
|
|
|
|
|
Poll::Pending
|
|
|
|
})
|
|
|
|
.await;
|
2023-01-18 04:17:50 +01:00
|
|
|
|
|
|
|
drop(on_drop);
|
|
|
|
|
|
|
|
r
|
2022-08-26 06:40:20 +02:00
|
|
|
}
|
|
|
|
|
2022-08-30 12:56:56 +02:00
|
|
|
// Stop sampling and wait for it to stop in a blocking fashion
|
|
|
|
fn stop_sampling_immediately() {
|
|
|
|
let r = Self::regs();
|
|
|
|
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
|
|
|
|
r.events_stopped.reset();
|
|
|
|
r.tasks_stop.write(|w| unsafe { w.bits(1) });
|
|
|
|
|
|
|
|
while r.events_stopped.read().bits() == 0 {}
|
|
|
|
r.events_stopped.reset();
|
|
|
|
}
|
2021-03-24 18:33:17 +01:00
|
|
|
}
|
|
|
|
|
2021-10-16 22:02:17 +02:00
|
|
|
impl<'d> Saadc<'d, 1> {
|
2021-10-18 02:45:23 +02:00
|
|
|
/// Continuous sampling on a single channel with double buffers.
|
2021-10-16 22:02:17 +02:00
|
|
|
///
|
|
|
|
/// The internal clock is to be used with a sample rate expressed as a divisor of
|
2022-03-07 02:45:37 +01:00
|
|
|
/// 16MHz, ranging from 80..2047. For example, 1600 represents a sample rate of 10KHz
|
2021-10-16 22:02:17 +02:00
|
|
|
/// given 16_000_000 / 10_000_000 = 1600.
|
|
|
|
///
|
|
|
|
/// A sampler closure is provided that receives the buffer of samples, noting
|
|
|
|
/// that the size of this buffer can be less than the original buffer's size.
|
|
|
|
/// A command is return from the closure that indicates whether the sampling
|
|
|
|
/// should continue or stop.
|
2022-02-26 08:15:37 +01:00
|
|
|
pub async fn run_timer_sampler<I, S, const N0: usize>(
|
2021-10-16 22:02:17 +02:00
|
|
|
&mut self,
|
2021-10-16 22:51:53 +02:00
|
|
|
bufs: &mut [[[i16; 1]; N0]; 2],
|
2021-10-18 02:42:30 +02:00
|
|
|
sample_rate_divisor: u16,
|
2021-10-16 22:02:17 +02:00
|
|
|
sampler: S,
|
|
|
|
) where
|
2023-02-01 00:48:33 +01:00
|
|
|
S: FnMut(&[[i16; 1]]) -> CallbackResult,
|
2021-10-16 22:02:17 +02:00
|
|
|
{
|
2022-06-12 22:15:44 +02:00
|
|
|
self.run_sampler(bufs, Some(sample_rate_divisor), || {}, sampler).await;
|
2021-10-16 22:02:17 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-10-12 02:24:26 +02:00
|
|
|
impl<'d, const N: usize> Drop for Saadc<'d, N> {
|
2021-03-24 18:33:17 +01:00
|
|
|
fn drop(&mut self) {
|
2021-09-01 23:54:26 +02:00
|
|
|
let r = Self::regs();
|
2021-03-24 18:33:17 +01:00
|
|
|
r.enable.write(|w| w.enable().disabled());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-11-21 02:02:59 +01:00
|
|
|
impl From<Gain> for GAIN_A {
|
|
|
|
fn from(gain: Gain) -> Self {
|
|
|
|
match gain {
|
|
|
|
Gain::GAIN1_6 => GAIN_A::GAIN1_6,
|
|
|
|
Gain::GAIN1_5 => GAIN_A::GAIN1_5,
|
|
|
|
Gain::GAIN1_4 => GAIN_A::GAIN1_4,
|
|
|
|
Gain::GAIN1_3 => GAIN_A::GAIN1_3,
|
|
|
|
Gain::GAIN1_2 => GAIN_A::GAIN1_2,
|
|
|
|
Gain::GAIN1 => GAIN_A::GAIN1,
|
|
|
|
Gain::GAIN2 => GAIN_A::GAIN2,
|
|
|
|
Gain::GAIN4 => GAIN_A::GAIN4,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Gain control
|
|
|
|
#[non_exhaustive]
|
|
|
|
#[derive(Clone, Copy)]
|
|
|
|
pub enum Gain {
|
|
|
|
/// 1/6
|
|
|
|
GAIN1_6 = 0,
|
|
|
|
/// 1/5
|
|
|
|
GAIN1_5 = 1,
|
|
|
|
/// 1/4
|
|
|
|
GAIN1_4 = 2,
|
|
|
|
/// 1/3
|
|
|
|
GAIN1_3 = 3,
|
|
|
|
/// 1/2
|
|
|
|
GAIN1_2 = 4,
|
|
|
|
/// 1
|
|
|
|
GAIN1 = 5,
|
|
|
|
/// 2
|
|
|
|
GAIN2 = 6,
|
|
|
|
/// 4
|
|
|
|
GAIN4 = 7,
|
|
|
|
}
|
|
|
|
|
|
|
|
impl From<Reference> for REFSEL_A {
|
|
|
|
fn from(reference: Reference) -> Self {
|
|
|
|
match reference {
|
|
|
|
Reference::INTERNAL => REFSEL_A::INTERNAL,
|
|
|
|
Reference::VDD1_4 => REFSEL_A::VDD1_4,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Reference control
|
|
|
|
#[non_exhaustive]
|
|
|
|
#[derive(Clone, Copy)]
|
|
|
|
pub enum Reference {
|
|
|
|
/// Internal reference (0.6 V)
|
|
|
|
INTERNAL = 0,
|
|
|
|
/// VDD/4 as reference
|
|
|
|
VDD1_4 = 1,
|
|
|
|
}
|
|
|
|
|
|
|
|
impl From<Resistor> for RESP_A {
|
|
|
|
fn from(resistor: Resistor) -> Self {
|
|
|
|
match resistor {
|
|
|
|
Resistor::BYPASS => RESP_A::BYPASS,
|
|
|
|
Resistor::PULLDOWN => RESP_A::PULLDOWN,
|
|
|
|
Resistor::PULLUP => RESP_A::PULLUP,
|
|
|
|
Resistor::VDD1_2 => RESP_A::VDD1_2,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Positive channel resistor control
|
|
|
|
#[non_exhaustive]
|
|
|
|
#[derive(Clone, Copy)]
|
|
|
|
pub enum Resistor {
|
|
|
|
/// Bypass resistor ladder
|
|
|
|
BYPASS = 0,
|
|
|
|
/// Pull-down to GND
|
|
|
|
PULLDOWN = 1,
|
|
|
|
/// Pull-up to VDD
|
|
|
|
PULLUP = 2,
|
|
|
|
/// Set input at VDD/2
|
|
|
|
VDD1_2 = 3,
|
|
|
|
}
|
|
|
|
|
|
|
|
impl From<Time> for TACQ_A {
|
|
|
|
fn from(time: Time) -> Self {
|
|
|
|
match time {
|
|
|
|
Time::_3US => TACQ_A::_3US,
|
|
|
|
Time::_5US => TACQ_A::_5US,
|
|
|
|
Time::_10US => TACQ_A::_10US,
|
|
|
|
Time::_15US => TACQ_A::_15US,
|
|
|
|
Time::_20US => TACQ_A::_20US,
|
|
|
|
Time::_40US => TACQ_A::_40US,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Acquisition time, the time the SAADC uses to sample the input voltage
|
|
|
|
#[non_exhaustive]
|
|
|
|
#[derive(Clone, Copy)]
|
|
|
|
pub enum Time {
|
|
|
|
/// 3 us
|
|
|
|
_3US = 0,
|
|
|
|
/// 5 us
|
|
|
|
_5US = 1,
|
|
|
|
/// 10 us
|
|
|
|
_10US = 2,
|
|
|
|
/// 15 us
|
|
|
|
_15US = 3,
|
|
|
|
/// 20 us
|
|
|
|
_20US = 4,
|
|
|
|
/// 40 us
|
|
|
|
_40US = 5,
|
|
|
|
}
|
|
|
|
|
|
|
|
impl From<Oversample> for OVERSAMPLE_A {
|
|
|
|
fn from(oversample: Oversample) -> Self {
|
|
|
|
match oversample {
|
|
|
|
Oversample::BYPASS => OVERSAMPLE_A::BYPASS,
|
|
|
|
Oversample::OVER2X => OVERSAMPLE_A::OVER2X,
|
|
|
|
Oversample::OVER4X => OVERSAMPLE_A::OVER4X,
|
|
|
|
Oversample::OVER8X => OVERSAMPLE_A::OVER8X,
|
|
|
|
Oversample::OVER16X => OVERSAMPLE_A::OVER16X,
|
|
|
|
Oversample::OVER32X => OVERSAMPLE_A::OVER32X,
|
|
|
|
Oversample::OVER64X => OVERSAMPLE_A::OVER64X,
|
|
|
|
Oversample::OVER128X => OVERSAMPLE_A::OVER128X,
|
|
|
|
Oversample::OVER256X => OVERSAMPLE_A::OVER256X,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Oversample control
|
|
|
|
#[non_exhaustive]
|
|
|
|
#[derive(Clone, Copy)]
|
|
|
|
pub enum Oversample {
|
|
|
|
/// Bypass oversampling
|
|
|
|
BYPASS = 0,
|
|
|
|
/// Oversample 2x
|
|
|
|
OVER2X = 1,
|
|
|
|
/// Oversample 4x
|
|
|
|
OVER4X = 2,
|
|
|
|
/// Oversample 8x
|
|
|
|
OVER8X = 3,
|
|
|
|
/// Oversample 16x
|
|
|
|
OVER16X = 4,
|
|
|
|
/// Oversample 32x
|
|
|
|
OVER32X = 5,
|
|
|
|
/// Oversample 64x
|
|
|
|
OVER64X = 6,
|
|
|
|
/// Oversample 128x
|
|
|
|
OVER128X = 7,
|
|
|
|
/// Oversample 256x
|
|
|
|
OVER256X = 8,
|
|
|
|
}
|
|
|
|
|
|
|
|
impl From<Resolution> for VAL_A {
|
|
|
|
fn from(resolution: Resolution) -> Self {
|
|
|
|
match resolution {
|
|
|
|
Resolution::_8BIT => VAL_A::_8BIT,
|
|
|
|
Resolution::_10BIT => VAL_A::_10BIT,
|
|
|
|
Resolution::_12BIT => VAL_A::_12BIT,
|
|
|
|
Resolution::_14BIT => VAL_A::_14BIT,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Set the resolution
|
|
|
|
#[non_exhaustive]
|
|
|
|
#[derive(Clone, Copy)]
|
|
|
|
pub enum Resolution {
|
|
|
|
/// 8 bits
|
|
|
|
_8BIT = 0,
|
|
|
|
/// 10 bits
|
|
|
|
_10BIT = 1,
|
|
|
|
/// 12 bits
|
|
|
|
_12BIT = 2,
|
|
|
|
/// 14 bits
|
|
|
|
_14BIT = 3,
|
|
|
|
}
|
|
|
|
|
2021-10-13 22:01:39 +02:00
|
|
|
pub(crate) mod sealed {
|
|
|
|
use super::*;
|
|
|
|
|
|
|
|
pub trait Input {
|
|
|
|
fn channel(&self) -> InputChannel;
|
|
|
|
}
|
2021-03-24 18:33:17 +01:00
|
|
|
}
|
|
|
|
|
2021-10-13 22:01:39 +02:00
|
|
|
/// An input that can be used as either or negative end of a ADC differential in the SAADC periperhal.
|
2022-07-23 15:13:47 +02:00
|
|
|
pub trait Input: sealed::Input + Into<AnyInput> + Peripheral<P = Self> + Sized + 'static {
|
2023-02-01 00:48:33 +01:00
|
|
|
/// Convert this SAADC input to a type-erased `AnyInput`.
|
|
|
|
///
|
|
|
|
/// This allows using several inputs in situations that might require
|
|
|
|
/// them to be the same type, like putting them in an array.
|
2022-07-21 16:42:46 +02:00
|
|
|
fn degrade_saadc(self) -> AnyInput {
|
|
|
|
AnyInput {
|
|
|
|
channel: self.channel(),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2021-10-13 22:01:39 +02:00
|
|
|
|
2023-02-01 00:48:33 +01:00
|
|
|
/// A type-erased SAADC input.
|
|
|
|
///
|
|
|
|
/// This allows using several inputs in situations that might require
|
|
|
|
/// them to be the same type, like putting them in an array.
|
2022-07-23 15:13:47 +02:00
|
|
|
pub struct AnyInput {
|
|
|
|
channel: InputChannel,
|
|
|
|
}
|
|
|
|
|
|
|
|
impl_peripheral!(AnyInput);
|
|
|
|
|
|
|
|
impl sealed::Input for AnyInput {
|
|
|
|
fn channel(&self) -> InputChannel {
|
|
|
|
self.channel
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl Input for AnyInput {}
|
|
|
|
|
2021-10-11 01:22:01 +02:00
|
|
|
macro_rules! impl_saadc_input {
|
|
|
|
($pin:ident, $ch:ident) => {
|
2022-07-23 15:13:47 +02:00
|
|
|
impl_saadc_input!(@local, crate::peripherals::$pin, $ch);
|
|
|
|
};
|
|
|
|
(@local, $pin:ty, $ch:ident) => {
|
|
|
|
impl crate::saadc::sealed::Input for $pin {
|
2021-10-11 01:22:01 +02:00
|
|
|
fn channel(&self) -> crate::saadc::InputChannel {
|
|
|
|
crate::saadc::InputChannel::$ch
|
2021-10-07 09:00:03 +02:00
|
|
|
}
|
2021-10-11 01:22:01 +02:00
|
|
|
}
|
2022-07-23 15:13:47 +02:00
|
|
|
impl crate::saadc::Input for $pin {}
|
|
|
|
|
|
|
|
impl From<$pin> for crate::saadc::AnyInput {
|
|
|
|
fn from(val: $pin) -> Self {
|
|
|
|
crate::saadc::Input::degrade_saadc(val)
|
|
|
|
}
|
|
|
|
}
|
2021-10-07 09:00:03 +02:00
|
|
|
};
|
|
|
|
}
|
2022-07-23 15:13:47 +02:00
|
|
|
|
|
|
|
/// A dummy `Input` pin implementation for SAADC peripheral sampling from the
|
|
|
|
/// internal voltage.
|
|
|
|
pub struct VddInput;
|
|
|
|
|
|
|
|
impl_peripheral!(VddInput);
|
|
|
|
#[cfg(not(feature = "_nrf9160"))]
|
|
|
|
impl_saadc_input!(@local, VddInput, VDD);
|
|
|
|
#[cfg(feature = "_nrf9160")]
|
|
|
|
impl_saadc_input!(@local, VddInput, VDDGPIO);
|
|
|
|
|
|
|
|
/// A dummy `Input` pin implementation for SAADC peripheral sampling from the
|
|
|
|
/// VDDH / 5 voltage.
|
|
|
|
#[cfg(any(feature = "_nrf5340-app", feature = "nrf52833", feature = "nrf52840"))]
|
|
|
|
pub struct VddhDiv5Input;
|
|
|
|
|
|
|
|
#[cfg(any(feature = "_nrf5340-app", feature = "nrf52833", feature = "nrf52840"))]
|
|
|
|
impl_peripheral!(VddhDiv5Input);
|
|
|
|
|
|
|
|
#[cfg(any(feature = "_nrf5340-app", feature = "nrf52833", feature = "nrf52840"))]
|
|
|
|
impl_saadc_input!(@local, VddhDiv5Input, VDDHDIV5);
|