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F4: Add PWR configuration to PLL

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This commit is contained in:
Thales Fragoso 2021-07-29 18:36:04 -03:00
parent 5cfb9adad8
commit 0421c57bd6
4 changed files with 16 additions and 3 deletions
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1
embassy-stm32/src/pwr/mod.rs
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@ -1,4 +1,5 @@
#[cfg_attr(any(pwr_h7, pwr_h7smps), path = "h7.rs")]
#[cfg_attr(not(any(pwr_h7, pwr_h7smps)), path = "none.rs")]
mod _version;
pub use _version::*;

1
embassy-stm32/src/pwr/none.rs Normal file
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@ -0,0 +1 @@

15
embassy-stm32/src/rcc/f4/mod.rs
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@ -1,4 +1,4 @@
use crate::pac::{FLASH, RCC};
use crate::pac::{FLASH, PWR, RCC};
use crate::peripherals;
use crate::rcc::{get_freqs, set_freqs, Clocks};
use crate::time::Hertz;
@ -39,6 +39,7 @@ impl<'d> Rcc<'d> {
}
fn freeze(mut self) -> Clocks {
use super::sealed::RccPeripheral;
use crate::pac::rcc::vals::{Hpre, Hsebyp, Ppre, Sw};
let pllsrcclk = self.config.hse.map(|hse| hse.0).unwrap_or(HSI);
@ -138,7 +139,17 @@ impl<'d> Rcc<'d> {
if plls.use_pll {
unsafe {
RCC.cr().modify(|w| w.set_pllon(true));
// TODO: PWR setup for HCLK > 168MHz
if hclk > 168_000_000 {
peripherals::PWR::enable();
PWR.cr().modify(|w| w.set_oden(true));
while !PWR.csr().read().odrdy() {}
PWR.cr().modify(|w| w.set_odswen(true));
while !PWR.csr().read().odswrdy() {}
}
while !RCC.cr().read().pllrdy() {}
}
}

2
stm32-data

@ -1 +1 @@
Subproject commit 62c8985228186a02a623d1acfb59b75a4865d303
Subproject commit 0ad27b2fd1126c6c9d9f4602d1331f5d82f4aa26