F4: Add PWR configuration to PLL
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@ -1,4 +1,5 @@
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#[cfg_attr(any(pwr_h7, pwr_h7smps), path = "h7.rs")]
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#[cfg_attr(any(pwr_h7, pwr_h7smps), path = "h7.rs")]
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#[cfg_attr(not(any(pwr_h7, pwr_h7smps)), path = "none.rs")]
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mod _version;
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mod _version;
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pub use _version::*;
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pub use _version::*;
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1
embassy-stm32/src/pwr/none.rs
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1
embassy-stm32/src/pwr/none.rs
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@ -1,4 +1,4 @@
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use crate::pac::{FLASH, RCC};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::peripherals;
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use crate::peripherals;
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use crate::rcc::{get_freqs, set_freqs, Clocks};
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use crate::rcc::{get_freqs, set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::time::Hertz;
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@ -39,6 +39,7 @@ impl<'d> Rcc<'d> {
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}
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}
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fn freeze(mut self) -> Clocks {
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fn freeze(mut self) -> Clocks {
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use super::sealed::RccPeripheral;
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use crate::pac::rcc::vals::{Hpre, Hsebyp, Ppre, Sw};
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use crate::pac::rcc::vals::{Hpre, Hsebyp, Ppre, Sw};
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let pllsrcclk = self.config.hse.map(|hse| hse.0).unwrap_or(HSI);
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let pllsrcclk = self.config.hse.map(|hse| hse.0).unwrap_or(HSI);
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@ -138,7 +139,17 @@ impl<'d> Rcc<'d> {
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if plls.use_pll {
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if plls.use_pll {
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unsafe {
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unsafe {
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RCC.cr().modify(|w| w.set_pllon(true));
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RCC.cr().modify(|w| w.set_pllon(true));
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// TODO: PWR setup for HCLK > 168MHz
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if hclk > 168_000_000 {
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peripherals::PWR::enable();
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PWR.cr().modify(|w| w.set_oden(true));
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while !PWR.csr().read().odrdy() {}
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PWR.cr().modify(|w| w.set_odswen(true));
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while !PWR.csr().read().odswrdy() {}
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}
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while !RCC.cr().read().pllrdy() {}
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while !RCC.cr().read().pllrdy() {}
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}
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}
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}
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}
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@ -1 +1 @@
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Subproject commit 62c8985228186a02a623d1acfb59b75a4865d303
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Subproject commit 0ad27b2fd1126c6c9d9f4602d1331f5d82f4aa26
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