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Workaround for L4

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This commit is contained in:
Ulf Lilleengen 2021-06-08 10:57:52 +02:00
parent ee47a3e802
commit 459049d604
1 changed files with 11 additions and 6 deletions
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17
stm32-metapac/build.rs
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@ -219,17 +219,22 @@ fn main() {
}
"spi" => {
if let Some(clock) = &p.clock {
// Workaround for APB1 register being split on some chip families
let reg = if chip.family == "STM32H7" && clock == "APB1" {
format!("{}l", clock.to_ascii_lowercase())
// Workaround for APB1 register being split on some chip families. Assume
// first register until we can find a way to hint which register is used
let reg = clock.to_ascii_lowercase();
let (enable_reg, reset_reg) = if chip.family == "STM32H7" && clock == "APB1"
{
(format!("{}lenr", reg), format!("{}lrstr", reg))
} else if chip.family == "STM32L4" && clock == "APB1" {
(format!("{}enr1", reg), format!("{}rstr1", reg))
} else {
clock.to_ascii_lowercase()
(format!("{}enr", reg), format!("{}rstr", reg))
};
let field = name.to_ascii_lowercase();
peripheral_rcc_table.push(vec![
name.clone(),
format!("{}enr", reg),
format!("{}rstr", reg),
enable_reg,
reset_reg,
format!("set_{}en", field),
format!("set_{}rst", field),
]);