Merge pull request #1873 from vDorst/adin1110-pr3
Adin1110: documents and comment fixes
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
48154e18bf
@ -32,6 +32,7 @@ pub use regs::{Config0, Config2, SpiRegisters as sr, Status0, Status1};
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use crate::fmt::Bytes;
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use crate::regs::{LedCntrl, LedFunc, LedPol, LedPolarity, SpiHeader};
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/// ADIN1110 intern PHY ID
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pub const PHYID: u32 = 0x0283_BC91;
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/// Error values ADIN1110
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@ -53,7 +54,9 @@ pub enum AdinError<E> {
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MDIO_ACC_TIMEOUT,
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}
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/// Type alias `Result` type with `AdinError` as error type.
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pub type AEResult<T, SPIError> = core::result::Result<T, AdinError<SPIError>>;
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/// Internet PHY address
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pub const MDIO_PHY_ADDR: u8 = 0x01;
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@ -104,6 +107,7 @@ impl<const N_RX: usize, const N_TX: usize> State<N_RX, N_TX> {
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}
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}
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/// ADIN1110 embassy-net driver
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#[derive(Debug)]
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pub struct ADIN1110<SPI> {
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/// SPI bus
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@ -116,6 +120,7 @@ pub struct ADIN1110<SPI> {
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}
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impl<SPI: SpiDevice> ADIN1110<SPI> {
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/// Create a new ADIN1110 instance.
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pub fn new(spi: SPI, spi_crc: bool, append_fcs_on_tx: bool) -> Self {
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Self {
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spi,
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@ -124,6 +129,7 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
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}
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}
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/// Read a SPI register
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pub async fn read_reg(&mut self, reg: sr) -> AEResult<u32, SPI::Error> {
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let mut tx_buf = Vec::<u8, 16>::new();
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@ -162,6 +168,7 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
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Ok(value)
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}
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/// Write a SPI register
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pub async fn write_reg(&mut self, reg: sr, value: u32) -> AEResult<(), SPI::Error> {
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let mut tx_buf = Vec::<u8, 16>::new();
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@ -427,9 +434,9 @@ impl<SPI: SpiDevice> mdio::MdioBus for ADIN1110<SPI> {
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}
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}
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/// Background runner for the ADIN110.
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/// Background runner for the ADIN1110.
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///
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/// You must call `.run()` in a background task for the ADIN1100 to operate.
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/// You must call `.run()` in a background task for the ADIN1110 to operate.
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pub struct Runner<'d, SPI, INT, RST> {
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mac: ADIN1110<SPI>,
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ch: ch::Runner<'d, MTU>,
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@ -32,11 +32,12 @@ enum Reg13Op {
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PostReadIncAddr = 0b10 << 14,
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Read = 0b11 << 14,
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}
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/// `MdioBus` trait
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/// Driver needs to implement the Clause 22
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/// Optional Clause 45 is the device supports this.
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///
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/// Claus 45 methodes are bases on <https://www.ieee802.org/3/efm/public/nov02/oam/pannell_oam_1_1102.pdf>
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/// Clause 45 methodes are bases on <https://www.ieee802.org/3/efm/public/nov02/oam/pannell_oam_1_1102.pdf>
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pub trait MdioBus {
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type Error;
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@ -87,89 +88,89 @@ pub trait MdioBus {
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}
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}
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// #[cfg(test)]
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// mod tests {
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// use core::convert::Infallible;
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#[cfg(test)]
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mod tests {
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use core::convert::Infallible;
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// use super::{MdioBus, PhyAddr, RegC22, RegVal};
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use super::{MdioBus, PhyAddr, RegC22, RegVal};
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// #[derive(Debug, PartialEq, Eq)]
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// enum A {
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// Read(PhyAddr, RegC22),
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// Write(PhyAddr, RegC22, RegVal),
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// }
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#[derive(Debug, PartialEq, Eq)]
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enum A {
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Read(PhyAddr, RegC22),
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Write(PhyAddr, RegC22, RegVal),
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}
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// struct MockMdioBus(Vec<A>);
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struct MockMdioBus(Vec<A>);
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// impl MockMdioBus {
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// pub fn clear(&mut self) {
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// self.0.clear();
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// }
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// }
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impl MockMdioBus {
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pub fn clear(&mut self) {
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self.0.clear();
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}
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}
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// impl MdioBus for MockMdioBus {
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// type Error = Infallible;
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impl MdioBus for MockMdioBus {
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type Error = Infallible;
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// fn write_cl22(
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// &mut self,
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// phy_id: super::PhyAddr,
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// reg: super::RegC22,
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// reg_val: super::RegVal,
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// ) -> Result<(), Self::Error> {
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// self.0.push(A::Write(phy_id, reg, reg_val));
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// Ok(())
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// }
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async fn write_cl22(
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&mut self,
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phy_id: super::PhyAddr,
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reg: super::RegC22,
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reg_val: super::RegVal,
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) -> Result<(), Self::Error> {
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self.0.push(A::Write(phy_id, reg, reg_val));
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Ok(())
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}
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// fn read_cl22(
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// &mut self,
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// phy_id: super::PhyAddr,
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// reg: super::RegC22,
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// ) -> Result<super::RegVal, Self::Error> {
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// self.0.push(A::Read(phy_id, reg));
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// Ok(0)
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// }
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// }
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async fn read_cl22(
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&mut self,
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phy_id: super::PhyAddr,
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reg: super::RegC22,
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) -> Result<super::RegVal, Self::Error> {
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self.0.push(A::Read(phy_id, reg));
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Ok(0)
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}
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}
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// #[test]
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// fn read_test() {
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// let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
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#[futures_test::test]
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async fn read_test() {
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let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
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// mdiobus.clear();
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// mdiobus.read_cl22(0x01, 0x00).unwrap();
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// assert_eq!(mdiobus.0, vec![A::Read(0x01, 0x00)]);
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mdiobus.clear();
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mdiobus.read_cl22(0x01, 0x00).await.unwrap();
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assert_eq!(mdiobus.0, vec![A::Read(0x01, 0x00)]);
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// mdiobus.clear();
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// mdiobus.read_cl45(0x01, (0xBB, 0x1234)).unwrap();
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// assert_eq!(
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// mdiobus.0,
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// vec![
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// #[allow(clippy::identity_op)]
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// A::Write(0x01, 13, (0b00 << 14) | 27),
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// A::Write(0x01, 14, 0x1234),
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// A::Write(0x01, 13, (0b11 << 14) | 27),
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// A::Read(0x01, 14)
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// ]
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// );
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// }
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mdiobus.clear();
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mdiobus.read_cl45(0x01, (0xBB, 0x1234)).await.unwrap();
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assert_eq!(
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mdiobus.0,
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vec![
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#[allow(clippy::identity_op)]
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A::Write(0x01, 13, (0b00 << 14) | 27),
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A::Write(0x01, 14, 0x1234),
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A::Write(0x01, 13, (0b11 << 14) | 27),
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A::Read(0x01, 14)
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]
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);
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}
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// #[test]
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// fn write_test() {
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// let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
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#[futures_test::test]
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async fn write_test() {
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let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
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// mdiobus.clear();
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// mdiobus.write_cl22(0x01, 0x00, 0xABCD).unwrap();
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// assert_eq!(mdiobus.0, vec![A::Write(0x01, 0x00, 0xABCD)]);
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mdiobus.clear();
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mdiobus.write_cl22(0x01, 0x00, 0xABCD).await.unwrap();
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assert_eq!(mdiobus.0, vec![A::Write(0x01, 0x00, 0xABCD)]);
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// mdiobus.clear();
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// mdiobus.write_cl45(0x01, (0xBB, 0x1234), 0xABCD).unwrap();
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// assert_eq!(
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// mdiobus.0,
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// vec![
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// A::Write(0x01, 13, 27),
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// A::Write(0x01, 14, 0x1234),
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// A::Write(0x01, 13, (0b01 << 14) | 27),
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// A::Write(0x01, 14, 0xABCD)
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// ]
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// );
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// }
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// }
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mdiobus.clear();
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mdiobus.write_cl45(0x01, (0xBB, 0x1234), 0xABCD).await.unwrap();
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assert_eq!(
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mdiobus.0,
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vec![
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A::Write(0x01, 13, 27),
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A::Write(0x01, 14, 0x1234),
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A::Write(0x01, 13, (0b01 << 14) | 27),
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A::Write(0x01, 14, 0xABCD)
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]
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);
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}
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}
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@ -111,6 +111,7 @@ pub mod RegsC45 {
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}
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}
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/// 10-BASE-T1x PHY functions.
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pub struct Phy10BaseT1x(u8);
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impl Default for Phy10BaseT1x {
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