stm32/dma: complete initial ringbuf impl.
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xoviat
parent
8064f4bfe0
commit
603c4cb4fa
@ -7,7 +7,7 @@ use core::task::{Context, Poll, Waker};
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use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use super::ringbuffer::{DmaCtrl, OverrunError, ReadableDmaRingBuffer};
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use super::ringbuffer::{DmaCtrl, OverrunError, ReadableDmaRingBuffer, WritableDmaRingBuffer};
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use super::word::{Word, WordSize};
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use super::Dir;
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use crate::_generated::DMA_CHANNEL_COUNT;
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@ -806,3 +806,172 @@ impl<'a, C: Channel, W: Word> Drop for ReadableRingBuffer<'a, C, W> {
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fence(Ordering::SeqCst);
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}
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}
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pub struct WritableRingBuffer<'a, C: Channel, W: Word> {
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cr: regs::Cr,
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channel: PeripheralRef<'a, C>,
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ringbuf: WritableDmaRingBuffer<'a, W>,
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}
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impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
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pub unsafe fn new_read(
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channel: impl Peripheral<P = C> + 'a,
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_request: Request,
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peri_addr: *mut W,
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buffer: &'a mut [W],
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options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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let len = buffer.len();
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assert!(len > 0 && len <= 0xFFFF);
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let dir = Dir::MemoryToPeripheral;
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let data_size = W::size();
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let channel_number = channel.num();
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let dma = channel.regs();
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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let mut w = regs::Cr(0);
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w.set_dir(dir.into());
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w.set_msize(data_size.into());
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w.set_psize(data_size.into());
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w.set_pl(vals::Pl::VERYHIGH);
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w.set_minc(vals::Inc::INCREMENTED);
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w.set_pinc(vals::Inc::FIXED);
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w.set_teie(true);
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w.set_htie(options.half_transfer_ir);
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w.set_tcie(true);
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w.set_circ(vals::Circ::ENABLED);
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#[cfg(dma_v1)]
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w.set_trbuff(true);
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#[cfg(dma_v2)]
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w.set_chsel(_request);
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w.set_pburst(options.pburst.into());
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w.set_mburst(options.mburst.into());
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w.set_pfctrl(options.flow_ctrl.into());
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w.set_en(true);
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let buffer_ptr = buffer.as_mut_ptr();
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let mut this = Self {
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channel,
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cr: w,
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ringbuf: WritableDmaRingBuffer::new(buffer),
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};
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this.clear_irqs();
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(&mut *this.channel, _request);
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let ch = dma.st(channel_number);
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ch.par().write_value(peri_addr as u32);
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ch.m0ar().write_value(buffer_ptr as u32);
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ch.ndtr().write_value(regs::Ndtr(len as _));
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ch.fcr().write(|w| {
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if let Some(fth) = options.fifo_threshold {
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// FIFO mode
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w.set_dmdis(vals::Dmdis::DISABLED);
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w.set_fth(fth.into());
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} else {
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// Direct mode
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w.set_dmdis(vals::Dmdis::ENABLED);
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}
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});
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this
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}
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pub fn start(&mut self) {
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let ch = self.channel.regs().st(self.channel.num());
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ch.cr().write_value(self.cr);
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}
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pub fn clear(&mut self) {
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self.ringbuf.clear(DmaCtrlImpl(self.channel.reborrow()));
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}
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/// Write elements from the ring buffer
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/// Return a tuple of the length written and the length remaining in the buffer
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pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
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self.ringbuf.write(DmaCtrlImpl(self.channel.reborrow()), buf)
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}
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/// Write an exact number of elements from the ringbuffer.
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pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, OverrunError> {
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use core::future::poll_fn;
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use core::sync::atomic::compiler_fence;
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let mut written_data = 0;
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let buffer_len = buffer.len();
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poll_fn(|cx| {
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self.set_waker(cx.waker());
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compiler_fence(Ordering::SeqCst);
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match self.write(&buffer[written_data..buffer_len]) {
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Ok((len, remaining)) => {
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written_data += len;
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if written_data == buffer_len {
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Poll::Ready(Ok(remaining))
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} else {
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Poll::Pending
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}
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}
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Err(e) => Poll::Ready(Err(e)),
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}
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})
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.await
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}
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// The capacity of the ringbuffer
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pub fn cap(&self) -> usize {
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self.ringbuf.cap()
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}
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pub fn set_waker(&mut self, waker: &Waker) {
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STATE.ch_wakers[self.channel.index()].register(waker);
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}
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fn clear_irqs(&mut self) {
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let channel_number = self.channel.num();
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let dma = self.channel.regs();
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let isrn = channel_number / 4;
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let isrbit = channel_number % 4;
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dma.ifcr(isrn).write(|w| {
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w.set_htif(isrbit, true);
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w.set_tcif(isrbit, true);
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w.set_teif(isrbit, true);
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});
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}
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pub fn request_stop(&mut self) {
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let ch = self.channel.regs().st(self.channel.num());
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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ch.cr().write(|w| {
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w.set_teie(true);
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w.set_htie(true);
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w.set_tcie(true);
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});
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}
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pub fn is_running(&mut self) -> bool {
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let ch = self.channel.regs().st(self.channel.num());
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ch.cr().read().en()
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}
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}
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impl<'a, C: Channel, W: Word> Drop for WritableRingBuffer<'a, C, W> {
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fn drop(&mut self) {
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self.request_stop();
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while self.is_running() {}
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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}
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}
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@ -228,9 +228,24 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
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/// Return a tuple of the length written and the capacity remaining to be written in the buffer
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pub fn write(&mut self, mut dma: impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), OverrunError> {
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let start = self.pos(dma.get_remaining_transfers());
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if start < self.end && self.end + buf.len() < self.cap() {
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// The available, unwritten portion in the ring buffer DOES NOT wrap
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// and copying elements into the buffer will not cause it to
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if start > self.end {
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// The occupied portion in the ring buffer DOES wrap
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let len = self.copy_from(buf, self.end..start);
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compiler_fence(Ordering::SeqCst);
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// Confirm that the DMA is not inside data we could have written
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let pos = self.pos(dma.get_remaining_transfers());
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if (pos > self.end && pos <= start) || dma.get_complete_count() > 1 {
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Err(OverrunError)
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} else {
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self.end = (self.end + len) % self.cap();
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Ok((len, self.cap() - (start - self.end)))
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}
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} else if start <= self.end && self.end + buf.len() < self.cap() {
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// The occupied portion in the ring buffer DOES NOT wrap
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// and copying elements into the buffer WILL NOT cause it to
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// Copy into the dma buffer
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let len = self.copy_from(buf, self.end..self.cap());
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@ -239,36 +254,31 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
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// Confirm that the DMA is not inside data we could have written
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let pos = self.pos(dma.get_remaining_transfers());
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if pos > self.end || pos <= start || dma.get_complete_count() > 1 {
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if pos > self.end || pos < start || dma.get_complete_count() > 1 {
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Err(OverrunError)
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} else {
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self.end = (self.end + len) % self.cap();
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Ok((len, self.cap() - (self.end - start)))
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}
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} else if self.end > start {
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// The available, unwritten portion in the ring buffer DOES wrap
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let len = self.copy_from(buf, self.end..start);
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compiler_fence(Ordering::SeqCst);
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dma.get_complete_count();
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todo!()
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} else if start < self.end && self.end + buf.len() >= self.cap() {
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// The available, unwritten portion in the ring buffer DOES NOT wrap
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// and copying elements into the buffer will cause it to
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} else {
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// The occupied portion in the ring buffer DOES NOT wrap
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// and copying elements into the buffer WILL cause it to
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let tail = self.copy_from(buf, self.end..self.cap());
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let head = self.copy_from(&buf[tail..], 0..start);
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compiler_fence(Ordering::SeqCst);
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dma.reset_complete_count();
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// Confirm that the DMA is not inside data we could have written
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let pos = self.pos(dma.get_remaining_transfers());
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if pos > self.end || pos < start || dma.reset_complete_count() > 1 {
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Err(OverrunError)
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} else {
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self.end = head;
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todo!()
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} else {
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todo!()
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Ok((tail + head, self.cap() - (start - self.end)))
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}
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}
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}
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/// Copy into the dma buffer at `data_range` from `buf`
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