address irq nits
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b58cc2aa23
commit
8926397f45
@ -227,10 +227,4 @@ impl cyw43::SpiBusCyw43 for MySpi {
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self.read(read).await;
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self.cs.set_high();
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}
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async fn wait_for_event(&mut self) {}
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fn clear_event(&mut self) {}
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}
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@ -170,9 +170,6 @@ where
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async fn wait_for_event(&mut self) {
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self.sm.wait_irq(0).await;
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}
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fn clear_event(&mut self) {
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self.sm.clear_irq(0);
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}
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}
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12
src/bus.rs
12
src/bus.rs
@ -1,5 +1,6 @@
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use core::slice;
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use embassy_futures::yield_now;
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use embassy_time::{Duration, Timer};
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use embedded_hal_1::digital::OutputPin;
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use futures::FutureExt;
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@ -20,8 +21,11 @@ pub trait SpiBusCyw43 {
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/// Callers that want to read `n` word from the backplane, have to provide a slice that is `n+1` words long.
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async fn cmd_read(&mut self, write: u32, read: &mut [u32]);
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async fn wait_for_event(&mut self);
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fn clear_event(&mut self);
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/// Wait for events from the Device. A typical implementation would wait for the IRQ pin to be high.
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/// The default implementation always reports ready, resulting in active polling of the device.
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async fn wait_for_event(&mut self) {
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yield_now().await;
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}
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}
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pub(crate) struct Bus<PWR, SPI> {
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@ -305,10 +309,6 @@ where
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pub async fn wait_for_event(&mut self) {
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self.spi.wait_for_event().await;
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}
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pub fn clear_event(&mut self) {
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self.spi.clear_event();
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}
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}
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fn swap16(x: u32) -> u32 {
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@ -1,7 +1,6 @@
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use core::slice;
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use embassy_futures::select::{select3, Either3};
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use embassy_futures::yield_now;
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use embassy_net_driver_channel as ch;
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use embassy_sync::pubsub::PubSubBehavior;
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use embassy_time::{block_for, Duration, Timer};
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@ -304,7 +303,6 @@ where
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/// Wait for IRQ on F2 packet available
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async fn handle_irq(&mut self, buf: &mut [u32; 512]) {
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self.bus.clear_event();
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// Receive stuff
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let irq = self.bus.read16(FUNC_BUS, REG_BUS_INTERRUPT).await;
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trace!("irq{}", FormatInterrupt(irq));
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@ -331,8 +329,6 @@ where
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} else {
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break;
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}
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yield_now().await;
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}
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}
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