address irq nits

This commit is contained in:
kbleeke 2023-03-27 14:37:39 +02:00
parent b58cc2aa23
commit 8926397f45
4 changed files with 6 additions and 19 deletions

View File

@ -227,10 +227,4 @@ impl cyw43::SpiBusCyw43 for MySpi {
self.read(read).await;
self.cs.set_high();
}
async fn wait_for_event(&mut self) {}
fn clear_event(&mut self) {}
}

View File

@ -170,9 +170,6 @@ where
async fn wait_for_event(&mut self) {
self.sm.wait_irq(0).await;
}
fn clear_event(&mut self) {
self.sm.clear_irq(0);
}
}

View File

@ -1,5 +1,6 @@
use core::slice;
use embassy_futures::yield_now;
use embassy_time::{Duration, Timer};
use embedded_hal_1::digital::OutputPin;
use futures::FutureExt;
@ -20,8 +21,11 @@ pub trait SpiBusCyw43 {
/// Callers that want to read `n` word from the backplane, have to provide a slice that is `n+1` words long.
async fn cmd_read(&mut self, write: u32, read: &mut [u32]);
async fn wait_for_event(&mut self);
fn clear_event(&mut self);
/// Wait for events from the Device. A typical implementation would wait for the IRQ pin to be high.
/// The default implementation always reports ready, resulting in active polling of the device.
async fn wait_for_event(&mut self) {
yield_now().await;
}
}
pub(crate) struct Bus<PWR, SPI> {
@ -305,10 +309,6 @@ where
pub async fn wait_for_event(&mut self) {
self.spi.wait_for_event().await;
}
pub fn clear_event(&mut self) {
self.spi.clear_event();
}
}
fn swap16(x: u32) -> u32 {

View File

@ -1,7 +1,6 @@
use core::slice;
use embassy_futures::select::{select3, Either3};
use embassy_futures::yield_now;
use embassy_net_driver_channel as ch;
use embassy_sync::pubsub::PubSubBehavior;
use embassy_time::{block_for, Duration, Timer};
@ -304,7 +303,6 @@ where
/// Wait for IRQ on F2 packet available
async fn handle_irq(&mut self, buf: &mut [u32; 512]) {
self.bus.clear_event();
// Receive stuff
let irq = self.bus.read16(FUNC_BUS, REG_BUS_INTERRUPT).await;
trace!("irq{}", FormatInterrupt(irq));
@ -331,8 +329,6 @@ where
} else {
break;
}
yield_now().await;
}
}