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Fix RTC for v2l0 & v2l1

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This commit is contained in:
Mathias 2022-10-11 10:28:28 +02:00
parent aff265a7f5
commit 9223b67306
3 changed files with 32 additions and 61 deletions
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46
embassy-stm32/src/rtc/v2/v2l0.rs
View File

@ -1,40 +1,26 @@
pub const BACKUP_REGISTER_COUNT: usize = 20;
/// Unlock the backup domain
pub(super) unsafe fn unlock_backup_domain(_clock_config: u8) {
// FIXME:
// crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
// while !crate::pac::PWR.cr1().read().dbp() {}
pub(super) unsafe fn unlock_backup_domain(clock_config: u8) {
// TODO: Missing from PAC?
// crate::pac::PWR.cr().modify(|w| w.set_dbp(true));
// while !crate::pac::PWR.cr().read().dbp() {}
// let reg = crate::pac::RCC.bdcr().read();
// assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
let reg = crate::pac::RCC.csr().read();
// if !reg.rtcen() || reg.rtcsel().0 != clock_config {
// crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
if !reg.rtcen() || reg.rtcsel().0 != clock_config {
crate::pac::RCC.csr().modify(|w| {
// Select RTC source
w.set_rtcsel(crate::pac::rcc::vals::Rtcsel(clock_config));
w.set_rtcen(true);
// crate::pac::RCC.bdcr().modify(|w| {
// // Reset
// w.set_bdrst(false);
// // Select RTC source
// w.set_rtcsel(Rtcsel(clock_config));
// w.set_rtcen(true);
// // Restore bcdr
// w.set_lscosel(reg.lscosel());
// w.set_lscoen(reg.lscoen());
// w.set_lseon(reg.lseon());
// w.set_lsedrv(reg.lsedrv());
// w.set_lsebyp(reg.lsebyp());
// });
// }
w.set_lseon(reg.lseon());
w.set_lsedrv(reg.lsedrv());
w.set_lsebyp(reg.lsebyp());
});
}
}
pub(crate) unsafe fn enable_peripheral_clk() {
// // enable peripheral clock for communication
// crate::pac::rcc.apb1enr1().modify(|w| w.set_rtcapben(true));
// // read to allow the pwr clock to enable
// crate::pac::PWR.cr1().read();
// Nothing to do
}

44
embassy-stm32/src/rtc/v2/v2l1.rs
View File

@ -1,40 +1,24 @@
pub const BACKUP_REGISTER_COUNT: usize = 20;
/// Unlock the backup domain
pub(super) unsafe fn unlock_backup_domain(_clock_config: u8) {
// FIXME:
// crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
// while !crate::pac::PWR.cr1().read().dbp() {}
pub(super) unsafe fn unlock_backup_domain(clock_config: u8) {
crate::pac::PWR.cr().modify(|w| w.set_dbp(true));
while !crate::pac::PWR.cr().read().dbp() {}
// let reg = crate::pac::RCC.bdcr().read();
// assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
let reg = crate::pac::RCC.csr().read();
// if !reg.rtcen() || reg.rtcsel().0 != clock_config {
// crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
if !reg.rtcen() || reg.rtcsel().0 != clock_config {
crate::pac::RCC.csr().modify(|w| {
// Select RTC source
w.set_rtcsel(crate::pac::rcc::vals::Rtcsel(clock_config));
w.set_rtcen(true);
// crate::pac::RCC.bdcr().modify(|w| {
// // Reset
// w.set_bdrst(false);
// // Select RTC source
// w.set_rtcsel(Rtcsel(clock_config));
// w.set_rtcen(true);
// // Restore bcdr
// w.set_lscosel(reg.lscosel());
// w.set_lscoen(reg.lscoen());
// w.set_lseon(reg.lseon());
// w.set_lsedrv(reg.lsedrv());
// w.set_lsebyp(reg.lsebyp());
// });
// }
w.set_lseon(reg.lseon());
w.set_lsebyp(reg.lsebyp());
});
}
}
pub(crate) unsafe fn enable_peripheral_clk() {
// // enable peripheral clock for communication
// crate::pac::rcc.apb1enr1().modify(|w| w.set_rtcapben(true));
// // read to allow the pwr clock to enable
// crate::pac::PWR.cr1().read();
// Nothing to do
}

3
embassy-stm32/src/rtc/v3.rs
View File

@ -32,7 +32,8 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
feature = "stm32wl54jc-cm0p",
feature = "stm32wle5ub",
feature = "stm32g0c1ve",
feature = "stm32wl55jc-cm4"
feature = "stm32wl55jc-cm4",
feature = "stm32wl55uc-cm4"
)))]
let config_rtcsel = stm32_metapac::rtc::vals::Rtcsel(config_rtcsel);
#[cfg(feature = "stm32g0c1ve")]