max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix RTC for v2l0 & v2l1

Browse Source
This commit is contained in:
Mathias 2022-10-11 10:28:28 +02:00
parent aff265a7f5
commit 9223b67306
3 changed files with 32 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
embassy-stm32/src/rtc/v2/v2l0.rs
View File

@ -1,40 +1,26 @@
pub const BACKUP_REGISTER_COUNT: usize = 20; pub const BACKUP_REGISTER_COUNT: usize = 20;
/// Unlock the backup domain /// Unlock the backup domain
pub(super) unsafe fn unlock_backup_domain(_clock_config: u8) { pub(super) unsafe fn unlock_backup_domain(clock_config: u8) {
// FIXME: // TODO: Missing from PAC?
// crate::pac::PWR.cr1().modify(|w| w.set_dbp(true)); // crate::pac::PWR.cr().modify(|w| w.set_dbp(true));
// while !crate::pac::PWR.cr1().read().dbp() {} // while !crate::pac::PWR.cr().read().dbp() {}
// let reg = crate::pac::RCC.bdcr().read(); let reg = crate::pac::RCC.csr().read();
// assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
// if !reg.rtcen() || reg.rtcsel().0 != clock_config { if !reg.rtcen() || reg.rtcsel().0 != clock_config {
// crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true)); crate::pac::RCC.csr().modify(|w| {
// Select RTC source
w.set_rtcsel(crate::pac::rcc::vals::Rtcsel(clock_config));
w.set_rtcen(true);
// crate::pac::RCC.bdcr().modify(|w| { w.set_lseon(reg.lseon());
// // Reset w.set_lsedrv(reg.lsedrv());
// w.set_bdrst(false); w.set_lsebyp(reg.lsebyp());
});
// // Select RTC source }
// w.set_rtcsel(Rtcsel(clock_config));
// w.set_rtcen(true);
// // Restore bcdr
// w.set_lscosel(reg.lscosel());
// w.set_lscoen(reg.lscoen());
// w.set_lseon(reg.lseon());
// w.set_lsedrv(reg.lsedrv());
// w.set_lsebyp(reg.lsebyp());
// });
// }
} }
pub(crate) unsafe fn enable_peripheral_clk() { pub(crate) unsafe fn enable_peripheral_clk() {
// // enable peripheral clock for communication // Nothing to do
// crate::pac::rcc.apb1enr1().modify(|w| w.set_rtcapben(true));
// // read to allow the pwr clock to enable
// crate::pac::PWR.cr1().read();
} }

44
embassy-stm32/src/rtc/v2/v2l1.rs
View File

@ -1,40 +1,24 @@
pub const BACKUP_REGISTER_COUNT: usize = 20; pub const BACKUP_REGISTER_COUNT: usize = 20;
/// Unlock the backup domain /// Unlock the backup domain
pub(super) unsafe fn unlock_backup_domain(_clock_config: u8) { pub(super) unsafe fn unlock_backup_domain(clock_config: u8) {
// FIXME: crate::pac::PWR.cr().modify(|w| w.set_dbp(true));
// crate::pac::PWR.cr1().modify(|w| w.set_dbp(true)); while !crate::pac::PWR.cr().read().dbp() {}
// while !crate::pac::PWR.cr1().read().dbp() {}
// let reg = crate::pac::RCC.bdcr().read(); let reg = crate::pac::RCC.csr().read();
// assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
// if !reg.rtcen() || reg.rtcsel().0 != clock_config { if !reg.rtcen() || reg.rtcsel().0 != clock_config {
// crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true)); crate::pac::RCC.csr().modify(|w| {
// Select RTC source
w.set_rtcsel(crate::pac::rcc::vals::Rtcsel(clock_config));
w.set_rtcen(true);
// crate::pac::RCC.bdcr().modify(|w| { w.set_lseon(reg.lseon());
// // Reset w.set_lsebyp(reg.lsebyp());
// w.set_bdrst(false); });
}
// // Select RTC source
// w.set_rtcsel(Rtcsel(clock_config));
// w.set_rtcen(true);
// // Restore bcdr
// w.set_lscosel(reg.lscosel());
// w.set_lscoen(reg.lscoen());
// w.set_lseon(reg.lseon());
// w.set_lsedrv(reg.lsedrv());
// w.set_lsebyp(reg.lsebyp());
// });
// }
} }
pub(crate) unsafe fn enable_peripheral_clk() { pub(crate) unsafe fn enable_peripheral_clk() {
// // enable peripheral clock for communication // Nothing to do
// crate::pac::rcc.apb1enr1().modify(|w| w.set_rtcapben(true));
// // read to allow the pwr clock to enable
// crate::pac::PWR.cr1().read();
} }

3
embassy-stm32/src/rtc/v3.rs
View File

@ -32,7 +32,8 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
feature = "stm32wl54jc-cm0p", feature = "stm32wl54jc-cm0p",
feature = "stm32wle5ub", feature = "stm32wle5ub",
feature = "stm32g0c1ve", feature = "stm32g0c1ve",
feature = "stm32wl55jc-cm4" feature = "stm32wl55jc-cm4",
feature = "stm32wl55uc-cm4"
)))] )))]
let config_rtcsel = stm32_metapac::rtc::vals::Rtcsel(config_rtcsel); let config_rtcsel = stm32_metapac::rtc::vals::Rtcsel(config_rtcsel);
#[cfg(feature = "stm32g0c1ve")] #[cfg(feature = "stm32g0c1ve")]